Page 1
Preliminary Spec.
Some contents are subject to change without notice.
for easy interchange or addition of modules.
4096 refresh cycle /64ms
TSOP and industry standard EEPROM in TSSOP
(Component SDRAM)
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64DBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
FEATURES
CLK Access Time
5.4ns(CL=3)
6.0ns(CL=2)
6.0ns(CL=3)
-6,-6L
-7,-7L
-8,-8L
Frequency
133MHz
100MHz
100MHz
Utilizes industry standard 4M x 16 Synchronous DRAMs
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
LVTTL Interface
PCB Outline
(Front)
(Back)
APPLICATION
main memory or graphic memory in computer systems
1
2
143
144
MIT-DS-0340-0.3
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Page 2
Preliminary Spec.
Some contents are subject to change without notice.
PIN CONFIGURATION
Number
Pin Name
Pin Name
Number
135
79111315
17
1924
6
810121416
18
20
Number
Pin Name
Pin Name
Number
73
74
75
76
777879
80
81
82
83
84
85
86
87
88
899091
92
212293
94
232495
96
252697
98
272899
1002930
101
102
3132103
104
3334105
106
3536107
108
3738109
110
3940111
1124142
113
114
4344115
116
4546117
118
4748119
120
4950121
1225152
123
124
5354125
126
5556127
128
5758129
130
5960131
132
6162133
1346364
135
136
6566137
138
6768139
140
6970141
142
7172143
144
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
NC
CLK1
Vss
VssNCNC
NC
NC
Vcc
Vcc
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
Vss
Vss
DQ20
DQ52
DQMB0
DQMB4
DQ21
DQ53
DQMB1
DQMB5
DQ22
DQ54
Vcc
Vcc
DQ23
DQ55
A0A3Vcc
Vcc
A1A4A6
A7
A2A5A8
BA0
Vss
Vss
Vss
Vss
DQ8
DQ40
A9
BA1
DQ9
DQ41
A10
A11
DQ10
DQ42
Vcc
Vcc
DQ11
DQ43
DQMB2
DQMB6
Vcc
Vcc
DQMB3
DQMB7
DQ12
DQ44
Vss
Vss
DQ13
DQ45
DQ24
DQ56
DQ14
DQ46
DQ25
DQ57
DQ15
DQ47
DQ26
DQ58
Vss
Vss
DQ27
DQ59
NCNCVcc
VccNCNC
DQ28
DQ60
CLK0
CKE0
DQ29
DQ61
Vcc
Vcc
DQ30
DQ62
/RAS
/CAS
DQ31
DQ63
/WE
CKE1
Vss
Vss
/S0NCSDA
SCL
/S1NCVcc
Vcc
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
PIN
Front side
PIN
Back side
PIN
Front side
PIN
Back side
MIT-DS-0340-0.3
NC = No Connection
MITSUBISHI
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Page 3
Preliminary Spec.
Some contents are subject to change without notice.
Block Diagram
/S0
/S1
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10Ω
CLK1
CLK0
CKE0
CKE1
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
MIT-DS-0340-0.3
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
/CS
D0
/CS
D1
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
4loads
4loads
D0 - D3
D4 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
/CS
D4
/CS
D5
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
MITSUBISHI
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SCL
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SERIAL PD
A0 A1 A2
/CS
D2
/CS
D3
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDA
27.Mar.2001
/CS
D6
/CS
D7
Page 4
Preliminary Spec.
Some contents are subject to change without notice.
Serial Presence Detect Table I
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Non-PARITY
Minimum Clock Delay,Back to Back Random Column Addresses
1/2/4/8/Full page
non-buffered,non-registered
Precharge All,Auto precharge
SDRAM Access form Clock(2nd highest CAS latency)
SDRAM Access form Clock(3rd highest CAS latency)
-8,-8L
-8,-8L
-7,-7L
-7,-7L
-6,-6L
-6,-6L
-6,-6L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Byte
0
Defines # bytes written into serial memory at module mfgr
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 SDRAM Cycle time(3rd highest CAS latency) N/A 00
26
27
# Column Addresses on this assembly
Voltage interface standard of this assembly LVTTL 01
DIMM Configuration type (Non-parity,Parity,ECC)
SDRAM Cycle time(2nd highest CAS latency)
Function described
Total # bytes of SPD memory device
Fundamental memory type
# Row Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
... Data Width continuation
Cycle time for CL=3
SDRAM Access from Clock
tAC for CL=3
Refresh Rate/Type
SDRAM width,Primary DRAM
Error Checking SDRAM data width
Burst Lengths Supported
# Banks on Each SDRAM device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes:General
Cycle time for CL=2
tAC for CL=2
Precharge to Active Minimum
-7,-7L,-8,-8L
-7,-7L,-8,-8L
SPD enrty data SPD DATA(hex)
128
256 Bytes
SDRAM
A0-A11 0C
A0-A7 08
2BANK 02
x64 40
0 00
10ns
5.4ns
6ns
self refresh(15.625uS)
x16
N/A
1 01
4bank
2/3
0
0
10ns
10ns
13ns
6ns
6ns
7ns 7 0
N/A 00
20ns 14
80
08
04
757.5ns
A0
54
60
00
80
10
00
8F
04
06
01
01
00
0E
A0
A0
D0
60
60
28
29
30
Row Active to Row Active Min. 15ns 0F
RAS to CAS Delay Min
Active to Precharge Min
MIT-DS-0340-0.3
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ELECTRIC
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4
20ns 14
20ns 14
45ns 2D
50ns 32
27.Mar.2001
Page 5
Preliminary Spec.
Some contents are subject to change without notice.
Serial Presence Detect Table II
Manufacturing date
4D483853363444424B472D36202020202020
-6,-6L,-7,-7L
-8,-8L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
-6,-6L
-7,-7L,-8,-8L
4D483853363444424B472D364C2020202020
4D483853363444424B472D37202020202020
4D483853363444424B472D374C2020202020
4D483853363444424B472D38202020202020
4D483853363444424B472D384C2020202020
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
31 Density of each bank on module 32MByte 08
32 Command and Address signal input setup time
33 Command and Address signal input hold time
34 Data signal input setup time
35
36-61 Superset Information (may be used in future)
62 SPD Revision
Data signal input hold time
1.5ns 15
2ns 20
0.8ns 08
1ns 10
2ns
0.8ns 08
1ns 10
option 00
rev 1.2B 12
151.5ns
20
63 Checksum for bytes 0-62
64-71
72 Manufacturing location
73-90 Manufactures Part Number
91-92 Revision Code PCB revision rrrr
93-94
95-98 Assembly Serial Number serial number ssssssss
99-125
126 Intetl specification frequency 100MHz 64
127 Intel specification CAS# Latency support
128+ Unused storage locations open 00
Manufactures Jedec ID code per JEP-108E
Manufacture Specific Data
Check sum for -6,-6L
Check sum for -7,-7L 05
Check sum for -8,-8L 45
MITSUBISHI 1CFFFFFFFFFFFFFF
Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
MH8S64DBKG-6
MH8S64DBKG-6L
MH8S64DBKG-7
MH8S64DBKG-7L
MH8S64DBKG-8
MH8S64DBKG-8L
year/week code yyww
option
9E
00
CFCL=2/3,AP,CK0,1
CDCL=3,AP,CK0,1
MIT-DS-0340-0.3
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Page 6
Preliminary Spec.
Some contents are subject to change without notice.
Power Supply
SDA
PIN FUNCTION
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CLK
(CLK0 ~ CLK1)
CKE0, CKE1 Input
/S0, /S1
/RAS,/CAS,/WE Input Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
BA0,1 Input
DQ0-63
DQMB0-7 Input
Vdd,Vss
SCL
MIT-DS-0340-0.3
Input/Output
Input
Output
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Data In and Data out are referenced to the rising edge
of CK
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply for the memory mounted module.
Serial clock for serial PD
Serial data for serial PD
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Page 7
Preliminary Spec.
Some contents are subject to change without notice.
The MH8S64DBKG provides basic functions,bank(row)activate,burst read / write,
To know the detailed definition of commands please see the command truth table.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BASIC FUNCTIONS
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh
command
Precharge Option @precharge or read/write
command
define basic commands
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0340-0.3
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Page 8
Preliminary Spec.
Some contents are subject to change without notice.
Precharge All Bank
COMMAND TRUTH TABLE
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X
No Operation NOP H X L H H H X X X
CKE
n-1
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
n
/S
/RAS
/CAS
/WE BA0,1 A10
A11
X
X
A0-9
Row Adress Entry &
Bank Activate
Single Bank Precharge PRE H X L L H L V L X
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh REFA H H L L L H X X X
Self-Refresh Entry REFS H L L L L H X X X
Self-Refresh Exit REFSX L H H X X X X X X
Burst Terminate TERM
Mode Register Set
ACT H X L L H H V V V
PREA
WRITE
WRITEA H X L H L L V H V
READ H X L H L H V L V
READA H X L H L H V H V
MRS
H X L L H L X H X
H X L H L L V L V
L H L H H H X X X
H X L H H L X X X
H X L L L L L L
V
X
X
V
V
V
V
X
X
X
X
X
L
V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0340-0.3
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Page 9
Preliminary Spec.
Some contents are subject to change without notice.
FUNCTION TRUTH TABLE
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Current State /S /RAS /CAS /WE Address
IDLE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L
L H L X
L L H H
L L H L
L L L H X REFA
L L L L
ROW ACTIVE H X X X X DESEL NOP
L H H H X NOP NOP
L H H L X TBST NOP
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Precharge/Precharge All
L L L H X REFA ILLEGAL
L L L L
READ H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L
L H L H BA,CA,A10 READ/READA
L H L L BA,CA,A10 WRITE/WRITEA
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
X TBST ILLEGAL*2
BA,CA,A10
BA,RA
BA,A10 PRE/PREA NOP*4
Op-Code,
Mode-Add
Op-Code,
Mode-Add
X
Op-Code,
Mode-Add
Command
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
Auto-Refresh*5
MRS Mode Register Set*5
Begin Read,Latch CA,
Determine Auto-Precharge
WRITE/
WRITEA
MRS ILLEGAL
TBST Terminate Burst
MRS ILLEGAL
Begin Write,Latch CA,
Determine Auto-Precharge
Terminate Burst,Latch CA,
Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
Action
MIT-DS-0340-0.3
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ELECTRIC
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Page 10
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
WRITE H X X X X DESEL NOP(Continue Burst to END)
L H H H X NOP NOP(Continue Burst to END)
L H H L X TBST Terminate Burst
L H L H BA,CA,A10
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA Terminate Burst,Precharge
L L L H X REFA ILLEGAL
L L L L
READ with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L X TBST ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H BA,RA ACT Bank Active/ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
WRITE with H X X X X DESEL NOP(Continue Burst to END)
AUTO L H H H X NOP NOP(Continue Burst to END)
PRECHARGE L H H L
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
L L H H
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
X
BA,RA
Op-Code,
Mode-Add
Command
Terminate Burst,Latch CA,
READ/READA
WRITE/
WRITEA
MRS ILLEGAL
WRITE/
WRITEA
MRS ILLEGAL
TBST ILLEGAL
WRITE/
WRITEA
ACT Bank Active/ILLEGAL*2
MRS ILLEGAL
Begin Read,Determine AutoPrecharge*3
Terminate Burst,Latch CA,
Begin Write,Determine AutoPrecharge*3
ILLEGAL
ILLEGAL
Action
MIT-DS-0340-0.3
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ELECTRIC
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27.Mar.2001
Page 11
Preliminary Spec.
Some contents are subject to change without notice.
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
MITSUBISHI LSIs
Current State /S /RAS /CAS /WE Address
PRE - H X X X X DESEL NOP(Idle after tRP)
CHARGING L H H H X NOP NOP(Idle after tRP)
L H H L X TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA NOP*4(Idle after tRP)
L L L H X REFA ILLEGAL
L L L L
ROW H X X X X DESEL NOP(Row Active after tRCD
ACTIVATING L H H H X NOP NOP(Row Active after tRCD
L H H L X TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
Op-Code,
Mode-Add
Command
MRS ILLEGAL
MRS ILLEGAL
Action
WRITE RE- H X X X X DESEL NOP
COVERING L H H H X NOP NOP
L H H L X TBST ILLEGAL*2
L H L X BA,CA,A10 READ/WRITE ILLEGAL*2
L L H H BA,RA ACT ILLEGAL*2
L L H L BA,A10 PRE/PREA ILLEGAL*2
L L L H X REFA ILLEGAL
L L L L
MIT-DS-0340-0.3
Op-Code,
Mode-Add
MITSUBISHI
MRS ILLEGAL
ELECTRIC
( / 51 )
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Page 12
Preliminary Spec.
Some contents are subject to change without notice.
1. All entries assume that CKE was High during the preceding clock cycle and the current
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE(continued)
Current State /S /RAS /CAS /WE Address Command Action
RE- H X X X X DESEL NOP(Idle after tRC)
FRESHING L H H H X NOP
L H H L X TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
NOP(Idle after tRC)
MITSUBISHI LSIs
L L L L
MODE H X X X X DESEL NOP(Idle after tRSC)
REGISTER L H H H X NOP NOP(Idle after tRSC)
SETTING L H H L X TBST ILLEGAL
L H L X BA,CA,A10 READ/WRITE ILLEGAL
L L H H BA,RA ACT ILLEGAL
L L H L BA,A10 PRE/PREA ILLEGAL
L L L H X REFA ILLEGAL
L L L L
Op-Code,
MRS ILLEGAL
Mode-Add
Op-Code,
MRS ILLEGAL
Mode-Add
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
MIT-DS-0340-0.3
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Preliminary Spec.
Some contents are subject to change without notice.
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
FUNCTION TRUTH TABLE FOR CKE
CK
Current State
n-1
CK
/RAS /CAS /WE Add Action
/S
n
MITSUBISHI LSIs
SELF - H X X X X X X
REFRESH*1 L H H X X X X
L H L H H H X
L H L H H L X
L H L H L X X
L H L L X X X
L L X X X X X
POWER H X X X X X X
DOWN L H X X X X X
L L X X X X X
ALL BANKS H H X X X X X
IDLE*2 H L L L L H X
H L H X X X X
H L L H H H X
H L L H H L X
H L L H L X X
H L L L X X X
L X X X X X X
ANY STATE H H X X X X X
other than H L X X X X X
listed above L H X X X X X
L L X X X X X
INVALID
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
ILLEGAL
ILLEGAL
NOP(Maintain Self-Refresh)
INVALID
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0340-0.3
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Preliminary Spec.
Some contents are subject to change without notice.
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SIMPLIFIED STATE DIAGRAM
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
CKEH
WRITEA READA
MRS
IDLE
ACT
CKEL
CKEH
ROW
ACTIVE
WRITE READ
READA
READ
READA
WRITE
WRITEA
WRITE
WRITEA
REFA
CKEL
CKEH
TERMTERM
READ
AUTO
REFRESH
POWER
DOWN
CKEL
CKEH
READ
SUSPEND
MIT-DS-0340-0.3
WRITEA
SUSPEND
POWER
APPLIED
CKEL
CKEH
POWER
ON
WRITEA
PRE PRE
PRE
PRE
PRE
CHARGE
MITSUBISHI
ELECTRIC
( / 51 )
14
READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
27.Mar.2001
Page 15
Preliminary Spec.
Some contents are subject to change without notice.
POWER ON SEQUENCE
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
SDRAM is ready for new command.
LENGTH
Before starting normal operation, the following power on sequence is necessary to prevent
After these sequence, the SDRAM is idle state and ready for normal operation.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock.Attempt to maintain CKE high,DQM0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
register(MRS). The mode register stores these date until the next MRS command, which
may be issued when both banks are in idle state. After tRSC from a MRS command, the
LATENCY
MODE
WRITE
MODE
00
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0
/CAS LATENCY
BURST
SINGLE BIT
WM
R
R
2
3
R
R
R
R
0 0
LTMODE BT BL
BURST
BURST
TYPE
R:Reserved for Future Use
FP: Full Page
BA0,1 A11-0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
CK
/S
/RAS
/CAS
/WE
BT= 0 BT= 1
1
2
4
8
R
R
R
FP
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
MIT-DS-0340-0.3
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Preliminary Spec.
Some contents are subject to change without notice.
CK
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Command
Address
DQ
Initial Address
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
CL= 3
BL= 4
BL
8
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Write
Y
D0 D1
D2
D3
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
MIT-DS-0340-0.3
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
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Preliminary Spec.
Some contents are subject to change without notice.
OPERATION DESCRIPTION
defined by the Burst Type. Minimum delay time of a READ command after an ACT command
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CK
Command
A0-9,11
BA0,1
A10
DQ
ACT
Xa
Xa
00
tRRD
ACT
Xb
Xb
01
tRCD
READ
Yb
0
01
PRE
tRP
1
Qb0 Qb1 Qb2 Qb3
Precharge all
ACT
Xa
Xa
00
READ
A READ command can be issued to any active bank. The start address is specified by A07(x16) . 1st output data is available after the /CAS Latency from the READ. The consecutive
data length is defined by the Burst Length. The address sequence of the burst data is
to the same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
tRASmin must be met.
MIT-DS-0340-0.3
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Preliminary Spec.
Some contents are subject to change without notice.
Internal precharge starts
BL
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command
A0-9, 11
ACT
Xa
tRCD
READ
Ya
ACT
tRCD
Xb
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
READ
PRE
tRP
Yb
ACT
Xa
A10
BA0,1
DQ
CK
Command
A0-9, 11
A10
BA0,1
DQ
00
0
Xb
01
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Xa
00
READ with Auto-Precharge (BL=4, CL=2)
ACT
Xa
Xa
00
READ
tRCD tRP
Ya
1
00
BL
Qa0 Qa1 Qa2 Qa3
01
0
0
00
ACT
Xa
00
Qb3
Xa
Xa
00
CK
Command
CL=3
CL=2
ACT READ
DQ Qa0 Qa1 Qa2 Qa3
DQ Qa0 Qa1 Qa2 Qa3
MIT-DS-0340-0.3
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
tRCD
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ACT
27.Mar.2001
Page 19
Preliminary Spec.
Some contents are subject to change without notice.
WRITE command can be issued to any active bank. The start address is specified by A0-7
performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till
previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
WRITE
A
(x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to
be written is defined by the Burst Length. The address sequence of burst data is defined by
the Burst Type. Minimum delay time of a WRITE command after an ACT command to the
same bank is tRCD. From the last input data to the PRE command, the write recovery time
(tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is
the internal precharge is complete. The internal precharge starts at tWR after the last input
data cycle. The next ACT command can be issued after (BL + tWR -1 + tRP) from the
WRITE (BL=4)
CK
Command
A0-9, 11
A10
BA0,1
DQ
CK
Command
A0-9, 11
A10
BA0,1
DQ
ACT
Xa
Xa
00
Write
tRCD BL
Ya
0
00
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
ACT
Xa
Xa
00
Write
tRCD
Ya
1
00
Da0 Da1 Da2 Da3
BL
tWR
tWR
PRE
0
ACT
tRP
Xa
Xa
00
ACT
tRP
Xa
Xa
00
Internal precharge begins
MIT-DS-0340-0.3
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Preliminary Spec.
Some contents are subject to change without notice.
Burst read oparation can be interrupted by new read of the same or the other bank. Random
Output disable
by DQM
by WRITE
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
MITSUBISHI LSIs
Command
A0-9,11
A10
BA0,1
DQ
READ
Ya
0
00
READ
READ
Yb
Yc
0
0
00
10
Qa0 Qa2 Qb0 Qc0Qa1 Qc1 Qc2
Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 2 cycle after WRITE
assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command
ACT
READ
Write
A0-9,11
A10
BA0,1
DQMB0-7
DQ
MIT-DS-0340-0.3
X a
00
Xa
Ya
0
00
Qa0
Ya
0
00
Da0 Da1 Da2 Da3
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Preliminary Spec.
Some contents are subject to change without notice.
/CAS Latency.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by precharge of the same bank. READ to PRE
interval is minimum 1 CK. A PRE command output disable latency is equivalent to the
Read Interrupted by Precharge (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ PRE
Q0 Q1
READ PRE
Q0 Q1
READ PRE
Q0
READ
READ PRE
PRE
Q0 Q2Q1
Q0
Q1
Q2
MIT-DS-0340-0.3
Command
DQ
READ PRE
Q0
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Preliminary Spec.
Some contents are subject to change without notice.
and disable the data output. The terminated bank remains active,READ to TBST interval is
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation
minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS
Latency.
Read Interrupted by Terminate (BL=4)
CK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ TBST
Q0 Q1
READ
READ
READ
READ
TBST
Q0 Q1
TBST
Q0
TBST
Q0 Q1 Q2
TBST
Q0 Q1
Q2
Command
DQ
MIT-DS-0340-0.3
READ TBST
Q0
MITSUBISHI
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Preliminary Spec.
Some contents are subject to change without notice.
Burst write operation can be interrupted by read of any active bank. Random column
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9, 11
A10
BA0,1
DQ
Write
Ya
0
00
Da0 Da1 Da2 Db0 Dc0 Dc1
Write
Yb
0
00
Write
Yc
0
10
Dc2 Dc3
[ Write Interrupted by Read ]
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command
ACT
Write
READ
A0-9,11
A10
BA0,1
DQ
MIT-DS-0340-0.3
Xa
Xa
00
Ya
0
00
Da1
don't care
Yb
0
00
Qb0
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23
Qb1Da0
Qb2 Qb3
27.Mar.2001
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write
recovery time(tWR) is required from the last data to PRE command. During write
recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQMB0-7
DQ
ACT
Xa
0
00
Write
Ya
0
00
Da0 Da1
tWR
PRE
0
00
ACT
tRP
Xa
0
00
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active.The WRITE to TBST
minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
Command
A0-9,11
BA0,1
MIT-DS-0340-0.3
CK
A10
DQ
ACT
Xa
0
00
Write
Ya
0
00
Da0 Da1
TBST
( / 51 )
24
Write
Yb
0
00
Db0 Db1 Db2 Db3
MITSUBISHI
ELECTRIC
27.Mar.2001
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Preliminary Spec.
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MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank.
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Autoprecharge interrrupted by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to another bank (BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
CK
Command
A0-9,11
A10
Write
Ya
1
00
Da0 Da1
auto-precharge
WRITEA interrupted by READ to another bank (CL=2,BL=4)
Write
Ya
1
Write
BL
Ya
tWR
0
10
Db0 Db1 Db2 Db3
interrupted
Read
BL
Yb
tWR
0
ACT
tRP
Xa
Xa
00
activate
ACT
tRP
Xa
Xa
BA0,1
DQ
MIT-DS-0340-0.3
00
Da0 Da1
auto-precharge
10
interrupted
00
Db0 Db1 Db2 Db3
activate
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Preliminary Spec.
Some contents are subject to change without notice.
Full page burst length is available for only the sequential burst type. Full page burst
issued. In case of the full page burst , a read or write with auto-precharge command
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]
Burst read with auto-precharge can be interrupted by read toanother bank. Next
ACT command can be issued after (BL+tRP) from the READA. Auto-precharge
interrrupted by a command to the same bank is inhibited.
READA Interrupted by READ to another bank (CL=2,BL=4)
CK
Command
A0-9,11
A10
BA0,1
DQ
Read
Ya
1
00
auto-precharge interrupted
Read
BL
Ya
0
10
Qa0 Qa1
ACT
tRP
Xa
Xa
00
Qb0 Qb1 Qb2 Qb3
activate
Full Page Burst
read or write is repeated untill aPrecharge or a Burst Terminate command is
is illegal.
Single Write
When single write mode is set, burst length for write is always one, independently
of Burst Length defined by (A2-0).
MIT-DS-0340-0.3
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Preliminary Spec.
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AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally.4096 REFA
cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
4banks concurrently. Before performing an auto-refresh, all banks must be in the
idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command
must not be issued before tRFC from the REFA command.
Auto-Refresh
CK
/S
/RAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
NOP or DESLECT
/CAS
/WE
CKE
A0-11
BA0,1
minimum tRFC
Auto Refresh on All Banks Auto Refresh on All Banks
MIT-DS-0340-0.3
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Preliminary Spec.
Some contents are subject to change without notice.
new command
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H.
After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and
a new command can be issued after, but DESEL or NOP commands must be
asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
Self Refresh Exit
X
00
minimum tRFC
for recovery
MIT-DS-0340-0.3
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Page 29
Preliminary Spec.
Some contents are subject to change without notice.
(ext.CLK)
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle. A command at the suspended cycle is ignored.
CK
tIH tIS tIH tIS
CKE
int.CLK
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CK
CKE
Command
CKE
Command
CK
CKE
PRE
ACT
NOP
NOP
Power Down by CKE
Standby Power Down
NOP NOP
Active Power Down
NOP NOP
DQ Suspend by CKE
MIT-DS-0340-0.3
Command
DQ
Write
D0 D1 D2 D3
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READ
MITSUBISHI
ELECTRIC
Q0 Q1 Q2 Q3
27.Mar.2001
Page 30
Preliminary Spec.
Some contents are subject to change without notice.
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to Data In latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
CK
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DQM Function
Command
DQMB0-7
DQ
Write
D0 D2 D3
masked by DQMB=H
READ
Q0 Q1 Q3
disabled by DQMB=H
MIT-DS-0340-0.3
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Page 31
Preliminary Spec.
Some contents are subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
mA
CAPACITANCE
VI = 1.4V
f=1MHz
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Symbol Parameter
Vdd
VI
VO
IO
Pd
Topr
Tstg
Supply Voltage
Input Voltage
Output Voltage
Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Condition Ratings Unit
with respect to Vss
with respect to Vss
with respect to Vss
Ta=25°C
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Symbol
Vdd
Parameter
Supply Voltage
-0.5 ~ 4.6
-0.5 ~ Vdd+0.5
-0.5 ~ Vdd+0.5
50
8
0 ~ 70
-40 ~ 100
Limits
Min. Typ. Max.
3.0
3.3
3.6
V
V
V
W
°C
°C
Unit
V
Vss
VIH
VIL
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
Supply Voltage
0
2.0
-0.3
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Symbol
CI(A)
CI(C)
CI(K)
CI/O
MIT-DS-0340-0.3
Parameter
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK pin
Input Capacitance, I/O pin
Test Condition Limits(max.)
Vi=200mVrms
MITSUBISHI
ELECTRIC
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31
0
0
Vdd+0.3
0.8
V
V
V
Unit
45
45
35
22
pF
pF
pF
pF
27.Mar.2001
Page 32
Preliminary Spec.
Some contents are subject to change without notice.
AVERAGE SUPPLY CURRENT from Vdd
Limits
(max)
in power-down mode
in non power-down mode
one bank active (discrete)
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
MITSUBISHI LSIs
Parameter
operating current
one bank active (discrete)
precharge stanby
current
precharge stanby current
active stanby current
in non power-down mode
burst current
auto-refresh current
self-refresh current
Note)
1:Icc(max) is specified at the output open condition.
2.Input signals are changed one time during 30ns.
Symbol
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3N
Icc3NS
Icc4
Icc5
Icc6
tRC=min.tCLK=min, BL=1,CL=3
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
CKE=CLK=L, /CS>Vcc-0.2V
CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(fixed)
CKE=H,tCLK=15ns
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
tRC=min, tCLK=min
CKE <0.2V
Test Condition
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
16
8
8
-7,-7L,
-8,-8L
440
16
160
120
240
200
440
880
-6,-6L
460
160
120
240
200
520
1040
-6,-7,-8
-6L,-7L,-8L 4 4
Unit
mA
mA
8
mA
mA
mA
mA
mA
mA
mA
mA
8
mA
Symbol Parameter Test Condition
VOH(DC)
VOL(DC)
IOZ Off-stare Output Current
VOH(AC) High-Level Output Voltage(AC) CL=50pF, IOH=-
VOL(AC) Low-Level Output Voltage(AC) CL=50pF, IOL=2mA 0.8 V
MIT-DS-0340-0.3
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
Input Current
Ii
IOH=-2mA
IOL=2mA
Q floating VO=0 ~ Vdd -10 10 uA
2mA
VIH=0 ~ Vdd+0.3V
MITSUBISHI
Limits
Min. Max.
2.4 V
0.4 V
2 V
40
-40
ELECTRIC
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Unit
uA
27.Mar.2001
Page 33
Preliminary Spec.
Some contents are subject to change without notice.
AC TIMING REQUIREMENTS
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
Input Setup time(all inputs)
Row to Column Delay
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Limits
Symbol Parameter
-6,-6L
Min. Max.
-7,-7L
Min. Max.
MITSUBISHI LSIs
-8,-8L
Unit
Min. Max.
tCLK
CK cycle time
CL=2
CL=3
tCH CK High pulse width 3
tCL CK Low pilse width 3 ns
tT Transition time of CK 1 10 ns
tIS
tIH Input Hold time(all inputs) 1 ns
tRC Row cycle time 70 ns
tRFC Refresh Cycle time 80 ns
tRCD
tRAS Row Active time 50 100K ns
tRP Row Precharge time 20 ns
tWR Write Recovery time 12 ns
tRRD
Act to Act Deley time
tRSC Mode Register Set Cycle time 10 ns
tREF Refresh Interval time 64 ms
10
7.5
2.5
2.5
1 10
1.5
0.8
67.5
75
20
45 100K
20
12
15
10
10
10 10
2 ns
20 ns
20 ns
64
13
3
3
1 10
2
1
70
80
20
50 100K
20
12
20
10
64
ns
ns
ns
CK
1.4V
Any AC timing is
referenced to the input
Signal
1.4V
signal crossing
through 1.4V.
MIT-DS-0340-0.3
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Page 34
Preliminary Spec.
Some contents are subject to change without notice.
1.4V
1.4V
SWITCHING CHARACTERISTICS
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
(SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
Symbol Parameter
Min.
-6,-6L
Max.
-7,-7L
Min.
Max.
MITSUBISHI LSIs
-8,-8L
Min. Max.
Unit
tAC
tOH
tOLZ
tOHZ
Access time from CK
Output Hold time
from CK
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
VOUT
CL=2
CL=3
CL=2
2.7CL=3
0
2.7
6
5.4
3
3
6
6
3 ns
7
6
ns
ns
3 ns3
0 ns
3 ns
6
1.4V
1.4V
CK
5.4
0
3
6
DQ
MIT-DS-0340-0.3
50pF
CK
DQ
tOLZ
tAC tOH
tOHZ
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Output Timing
Measurement
Reference Point
27.Mar.2001
Page 35
Preliminary Spec.
Some contents are subject to change without notice.
Burst Write (single bank) @BL=4
/WE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
/RAS
/CAS
CKE
DQM
A0-7
A10
A8-9,11
X
X
X
tRCD
tRAS
tWR
Y
tRP
tRCD
tWR
X
X
X
Y
BA0,1
0
DQ
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
MIT-DS-0340-0.3
0 0
D0 D0 D0 D0
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35
0
0
D0 D0 D0 D0
Italic parameter indicates minimum case
0
PRE#0
27.Mar.2001
Page 36
Preliminary Spec.
Some contents are subject to change without notice.
Burst Write (multi bank) @BL=4
/WE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CLK
/CS
/RAS
/CAS
CKE
DQM
A0-7
X
tRRD
tRCD
tRC
tRAS
tRCD
tWR
Y
X
Y
tRP
tRC
X
tRCD
tWR
Y
X
A10
A8-9,11
BA0,1
DQ
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
MIT-DS-0340-0.3
X
X
0
X
X
0 1
1
D0 D0 D0 D0
ACT#1
WRITEA#1
(Auto-Precharge)
0
D1 D1 D1 D1
MITSUBISHI
X
X
0
Italic parameter indicates minimum case
0
D0 D0 D0 D0
X
X
1
ACT#1
0
PRE#0
27.Mar.2001
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Page 37
Preliminary Spec.
Some contents are subject to change without notice.
Burst Read (single bank) @BL=4 CL=2
/WE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
/RAS
/CAS
CKE
DQM
A0-7
A10
A8-9,11
X
X
X
tRCD
tRAS
Y
tRP
X
X
X
tRAS
tRCD
Y
BA0,1
0
DQ
ACT#0 READ#0 PRE#0 ACT#0 READ#0
MIT-DS-0340-0.3
0 0
Q0 Q0 Q0 Q0
0
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0
Q0 Q0
Italic parameter indicates minimum case
0
Q0 Q0
PRE#0
27.Mar.2001
Page 38
Preliminary Spec.
Some contents are subject to change without notice.
/WE
Burst Read (multiple bank) @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tRC
tRC
/RAS
/CAS
CKE
DQM
A0-7
A10
A8-9,11
tRRD
tRCD tRCD
X
X
X
Y
tRCD
X
X
X
Y
X
X
X
tRAS
Y
X
X
X
BA0,1
DQ
MIT-DS-0340-0.3
0
ACT#0 READA#0
0
ACT#1
1
Q0 Q0 Q0 Q0
1
READA#1 ACT#1
0
Q1 Q1 Q1 Q1
0
READ#0
Italic parameter indicates minimum case
1 0
Q0 Q0 Q0 Q0
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PRE#0ACT#0
27.Mar.2001
Page 39
Preliminary Spec.
Some contents are subject to change without notice.
Write Interrupted by Write @BL=4
/WE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tWR
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0
Y
X
X
X
0 1
1
D0 D0
WRITE#0
ACT#1
D0 D0
WRITE#0
interrupt
same bank
Y
0
Y
D1 D1 D1 D1
WRITEA#1
interrupt
other bank
Y
0
D0 D0 D0 D0
WRITE#0
interrupt
other bank
PRE #0
0
X
X
X
1
ACT#1
MIT-DS-0340-0.3
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Italic parameter indicates minimum case
27.Mar.2001
Page 40
Preliminary Spec.
Some contents are subject to change without notice.
Read Interrupted by Read @BL=4 CL=2
/WE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0
Y
0
READ#0
ACT#1
X
X
X
1
Y
1
Q0 Q0 Q0 Q0
READ#1
interrupt
other bank
Y
1
Q1 Q1 Q1 Q1
READA#1
interurrpt
same bank
Italic parameter indicates minimum case
Y
0
READ#0
interurrpt
other bank
X
X
X
1
Q0 Q0 Q0 Q0
ACT#1
MIT-DS-0340-0.3
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27.Mar.2001
Page 41
Preliminary Spec.
Some contents are subject to change without notice.
/WE
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tRCD
tWR
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 PRE #1
X
X
X
1
D0 D0
ACT#1
Y
0 1
Y
READ#1
Q1 Q1 D1
WRITE#1
Y
1
D1 D1 D1
1
MIT-DS-0340-0.3
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Italic parameter indicates minimum case
27.Mar.2001
Page 42
Preliminary Spec.
Some contents are subject to change without notice.
/WE
Write/Read Terminated by Precharge @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
tRCD
/CAS
tWR
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tRC
tRP tRAS
tRCD
tRP
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0 ACT#0
Y
0 0
D0
D0
PRE#0
WRITE#0
Termination
X
X
X
0
ACT#0
Y
0
READ#0
0
Q0
Q0
PRE#0
Termination
X
X
X
0
MIT-DS-0340-0.3
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Italic parameter indicates minimum case
27.Mar.2001
Page 43
Preliminary Spec.
Some contents are subject to change without notice.
/WE
Write/Read Terminated by Burst Terminate @BL=4,CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tWR
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
Y
0
D0
Y
0 0
D0 D0
TBST WRITE#0
READ#0
Q0 Q0
TBST
Y
D0
0
D0 D0 D0
PRE#0
MIT-DS-0340-0.3
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Italic parameter indicates minimum case
27.Mar.2001
Page 44
Preliminary Spec.
Some contents are subject to change without notice.
Single
Write Burst Read @BL=4 CL=2
/WE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0
Y
0 0
D0 Q0 Q0
WRITE#0
Y
Q0
READ#0
Q0
MIT-DS-0340-0.3
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Italic parameter indicates minimum case
27.Mar.2001
Page 45
Preliminary Spec.
Some contents are subject to change without notice.
Power-Up Sequence and Intialize
/WE
CLK
200us
/CS
tRP
tRFC
/RAS
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tRFC
tRSC
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
NOP
Power On
PRE ALL
REFA
REFA
Minimum 8 REFA cycles
REFA
MA
0
0
0
MRS
X
X
X
0
ACT#0
MIT-DS-0340-0.3
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27.Mar.2001
Page 46
Preliminary Spec.
Some contents are subject to change without notice.
/WE
Auto Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRFC
/CS
/RAS
tRP
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tRCD
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
PRE ALL REFA ACT#0 WRITE#0
Y
0
D0 D0
D0
D0
MIT-DS-0340-0.3
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Italic parameter indicates minimum case
27.Mar.2001
Page 47
Preliminary Spec.
Some contents are subject to change without notice.
/WE
Self Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
tRP
/RAS
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
tRFC
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
PRE ALL
Self Refresh Entry Self RefreshExit
X
X
X
0
ACT#0
MIT-DS-0340-0.3
All banks must be idle before REFS is issued.
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27.Mar.2001
Page 48
Preliminary Spec.
Some contents are subject to change without notice.
/WE
CLK Suspension @BL=4 CL=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
tRCD
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
X
X
X
0
ACT#0
Y
0
D0
D0 D0
WRITE#0
D0
Internal CLK
suspended
Y
0
READ#0
Q0 Q0D0
Q0 Q0
Internal CLK
suspended
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Italic parameter indicates minimum case
27.Mar.2001
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Preliminary Spec.
Some contents are subject to change without notice.
/WE
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
CKE
DQM
A0-7
A10
A8-9,11
BA0,1
DQ
PRE ALL
Stanby Power Down
Active Power Down
X
X
X
0
ACT#0
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ELECTRIC
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Page 50
Preliminary Spec.
Some contents are subject to change without notice.
OUTLINE
31.75
20.00
4.00
6.00
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
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Preliminary Spec.
Some contents are subject to change without notice.
flammable material or (iii) prevention against any malfunction or mishap.
a device or system that is used under circumstances in which human life is potentially at stake.
product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
MITSUBISHI LSIs
MH8S64DBKG -6,-6L-7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
4.When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and
products.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater use.
6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
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