Datasheet MCP19114, MCP19115 Datasheet

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Page 1

MCP19114/5

Digitally Enhanced Po wer An alog Syn chr onous Low-Si de PWM Controller

Features:

• Input Voltage: 4.5V to 42V

• Can be configured with Multiple Topologies including but not limited to:

-Flyback

- Ćuk

-Boost

- SEPIC (Single-Ended Primary-Inductor

Converter)

• Capable of Quasi-Resonant or Fixed-Frequency Operation

• Low Quiescent Current: 5 mA Typical

• Low Sleep Current: 30 µA Typical

• Low-Side Gate Drivers:

- +5V Gate Drive

- 0.5A Sink/Source Current

-+10V Gate Drive

- 1A Sink/Source Current

• Peak Current Mode Control

• Differential Remote Output Sense

• Multiple Output Systems:

- Master or Slave

• Configurable Parameters:

-V

, Precision I

REF

- Input Undervoltage Lockout (UVLO)

- Input Overvoltage Lockout (OVLO)

- Detection and Protection

- Primary Current Leading Edge Blanking (0,

50 ns, 100 ns and 200 ns)

- Gate Drive Dead Time (16 ns to 256 ns)

- Fixed Switching Frequency Range:

31.25 kHz to 2.0 MHz

- Slope Compensation

- Quasi-Resonant Configuration with Built-in

Comparator and Programmable Offset Voltage Adjustment

- Primary Current Offset Adjustment

- Configurable GPIO Pin Options

• Integrated Low-Side Differential Current Sense Amplifier

• ±5% Current Regulation

• Thermal Shutdown

OUT/VOUT

Set Point (DAC)

Microcontroller Features:

• Precision 8 MHz Internal Oscillator Block:

- Factory-calibrated to ±1%, typical

• Interrupt Capable

-Firmware

- Interrupt-on-Change Pins

• Only 35 Instructions to Learn

• 4096 Words On-Chip Program Memory

• High Endurance Flash:

- 100,000 write Flash Endurance

- Flash Retention: >40 years

• Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• Eight I/O Pins and One Input-Only Pin

- Two Open Drain Pins

• Analog-to-Digital Converter (ADC):

- 10-bit Resolution

- Five External Channels

• Timer0: 8-bit Timer/Counter with 8-bit Prescaler

• Enhanced Timer1:

- 16-bit Timer with Prescaler

- Two Selectable Clock Sources

• Timer2: 8-Bit Timer with Prescaler

- 8-bit Period Register

• I

CTM Communication:

- 7-bit Address Masking

- Two Dedicated Address Registers

 2014 Microchip Technology Inc. DS20005281A-page 1

Page 2

MCP19114/5

MCP19114

EXP-25

GPA0/AN0/TEST_OUT

GPA1/AN1/CLKPIN

GPA2/AN2/T0CKI/INT

GPA3/AN3

GPA7/SCL/ICSPCLK

GPA6/CCD/ICSPDAT

GPA5/MCLR/TEST_EN

GPB0/SDA

DESAT

SOUT

GND

SDRV

PDRV

GPB1/AN4/VREF2

COMP

Pin Diagram – 24-Pin QFN (MCP19114)

DS20005281A-page 2  2014 Microchip Technology Inc.

Page 3

TABLE 1: 24-PIN SUMMARY

MCP19114/5

I/O

ANSEL

A/D

Timers

24-Pin QFN

MSSP

Interrupt

Basic Additional

Pull-up

GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output

GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out

GPA2 3 Y AN2 T0CKI — IOC

Y — —

(2)

INT

GPA3 4 Y AN3 — — IOC Y — —

GPA5 7 N — — — IOC

(4)

(5)

MCLR Test Enable Input

GPA6 6 N — — — IOC Y ICSPDAT Dual Capture/Compare Input

GPA7 5 N — — SCL IOC N ICSPCLK —

GPB0 8 N — — SDA IOC N — —

GPB1 24 Y AN4 — — IOC Y — V

DESAT

DESATP/

SOUT

9 N — — — — — — DESAT Negative Input

10 N — — — — — — DESATP Input or I

11 N — — — — Y — Current Sense Amplifier Positive

REF2

Output

(3)

(6)

SOUT

Input

12 N — — — — — — Current Sense Amplifier

Negative Input

GND

13 N — — — — — — Primary Input Current Sense

14 N — — — — — A

15 N — — — — — P

GND

Small Signal Ground

Large Signal Ground

SDRV 16 N — — — — — — Secondary LS Gate Drive

Output

PDRV 17 N — — — — — — Primary LS Gate Drive

Output

COMP

18 N — — — — — V

19 N — — — — — V

20 N — — — — — V

Gate Drive Supply Voltage

VDD Output

Input Supply Voltage

21 N — — — — — — Output Voltage Sense

22 N — — — — — — Error Amplifier Feedback Input

23 N — — — — — — Error Amplifier Output

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the

MODECON register.

3: V

output selected when configured as master by proper configuration of the MSC<1:0> bits in the

REF2

MODECON register.

4: The IOC is disabled when MCLR 5: Weak pull-up always enabled when MCLR 6: When RFB of MODECON<5> = 0, internal feedback resistor and DESAT

RFB = 1, I

SOUT

is enabled.

is enabled, otherwise the pull-up is under user control.

input are enabled. When

(1)

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MCP19114/5

MCP19115

715

EXP-29

GPA1/AN1/CLKPIN

GPA2/AN2/T0CKI/INT

GPB4/AN5/ICSPDAT

GPA3/AN3

GPA7/SCL

GPA6/CCD

GPA0/AN0/TEST_OUT

GPB6/AN7

GPB5/AN6/ICSPCLK

GPB1/AN4/VREF2

COMP

PDRV

SDRV

GND

GPA5/MCLR/TEST_EN

GPB7_CCD

GPB0/SDA

DESAT

SOUT

Pin Diagram – 28-Pin QFN (MCP19115)

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Page 5

TABLE 2: 28-PIN SUMMARY

MCP19114/5

I/O

ANSEL

A/D

Timers

28-Pin QFN

MSSP

Interrupt

Pull-up

Basic Additional

GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output

GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out

GPA2 3 Y AN2 T0CKI — IOC

Y — —

(2)

INT

GPA3 5 Y AN3 — — IOC Y — —

GPA5 8 N — — — IOC

(4)

(5)

MCLR Test Enable Input

GPA6 7 N — — — IOC Y — Dual Capture/Single

Compare1 Input

GPA7 6 N — — SCL IOC N — —

GPB0 10 N — — SDA IOC N — —

GPB1 26 Y AN4 — — IOC Y — V

REF2

(3)

GPB4 4 Y AN5 — — IOC Y ICSPDAT —

GPB5 27 Y AN6 — — IOC Y ICSPCLK —

GPB6 28 Y AN7 — — IOC Y — —

GPB7 9 Y — — — IOC Y — Single Compare2 Input

DESATP/

SOUT

12 N — — — — — — DESATP input or I

Output

(6)

SOUT

DESATN11 N — — — — — — DESAT Negative Input

13 N — — — — Y — Current Sense Amplifier

Non-Inverting Input

14 N — — — — — — Current Sense Amplifier

Inverting Input

GND

15 N — — — — — — Primary Input Current Sense

16 N — — — — — A

17 N — — — — — P

GND

Small Signal Ground

Large Signal Ground

SDRV 18 N — — — — — — Secondary LS Gate Drive

Output

PDRV 19 N — — — — — — Primary LS Gate Drive Output

COMP

20 N — — — — — V

21 N — — — — — V

22 N — — — — — V

Gate Drive Supply Voltage

VDD Output

Input Supply Voltage

23 N — — — — — — Output Voltage Sense

24 N — — — — — — Error Amplifier Feedback input

25 N — — — — — — Error Amplifier Output

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the

MODECON register.

3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the

MODECON register.

4: The IOC is disabled when MCLR 5: Weak pull-up always enabled when MCLR 6: When RFB of MODECON<6> =0 Internal feedback resistor is enabled allow with DESAT

RFB=1, I

SOUT

is enabled.

is enabled, otherwise the pull-up is under user control.

input. When

(1)

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MCP19114/5

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Pin Description ........................................................................................................................................................................... 13

3.0 Functional Description ................................................................................................................................................................ 19

4.0 Electrical Characteristics............................................................................................................................................................ 22

5.0 Digital Electrical Characteristics................................................................................................................................................. 29

6.0 Configuring the MCP19114/5 ..................................................................................................................................................... 37

7.0 Typical Performance Curves ...................................................................................................................................................... 53

8.0 System Bench Testing................................................................................................................................................................ 57

9.0 Device Calibration ...................................................................................................................................................................... 59

10.0 Memory Organization ................................................................................................................................................................. 67

11.0 Device Configuration.................................................................................................................................................................. 79

12.0 Oscillator Modes......................................................................................................................................................................... 81

13.0 Resets ........................................................................................................................................................................................ 83

14.0 Interrupts .................................................................................................................................................................................... 91

15.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 99

16.0 Watchdog Timer (WDT)............................................................................................................................................................ 101

17.0 Flash Program Memory Control ............................................................................................................................................... 103

18.0 I/O Ports ................................................................................................................................................................................... 109

19.0 Interrupt-On-Change .................................................................................................................................................................119

20.0 Internal Temperature Indicator Module..................................................................................................................................... 123

21.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 125

22.0 Timer0 Module.......................................................................................................................................................................... 135

23.0 Timer1 Module with Gate Control ............................................................................................................................................. 137

24.0 Timer2 Module.......................................................................................................................................................................... 141

25.0 Enhanced PWM Module........................................................................................................................................................... 143

26.0 Dual Capture/Compare (CCD) Module..................................................................................................................................... 147

27.0 PWM Control Logic .................................................................................................................................................................. 151

28.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 153

29.0 Instruction Set Summary .......................................................................................................................................................... 195

30.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 205

31.0 Development Support............................................................................................................................................................... 207

32.0 Packaging Information...............................................................................................................................................................211

Appendix A: Revision History............................................................................................................................................................. 217

Index .................................................................................................................................................................................................. 219

The Microchip Web Site..................................................................................................................................................................... 225

Customer Change Notification Service .............................................................................................................................................. 225

Customer Support .............................................................................................................................................................................. 225

Product Identification System............................................................................................................................................................. 227

DS20005281A-page 6  2014 Microchip Technology Inc.

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MCP19114/5

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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using.

Customer Notification System

 2014 Microchip Technology Inc. DS20005281A-page 7

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MCP19114/5

NOTES:

DS20005281A-page 8  2014 Microchip Technology Inc.

Page 9

MCP19114/5

1.0 DEVICE OVERVIEW

The MCP19114/5 are highly integrated, mixed signal low-side synchronous controllers that operate from

4.5V to 42V. The family features an analog PWM controller with an integrated microcontroller core used for LED lighting systems, battery chargers and other low-side switch PWM applications. The devices feature an analog internal PWM controller similar to the MCP1631, and a standard PIC to the PIC12F617.

Complete customization of device operating parameters, start-up or shutdown profiles, protection levels and fault handling procedures are accomplished by setting digital registers using Microchip’s MPLAB Integrated Development Environment software and one of Microchip’s many in-circuit debugger and device programmers.

The MCP19114/5 mixed signal low-side synchronous controllers feature integrated programmable input UVLO/OVLO, programmable output overvoltage (OV), two low-side gate drive outputs with independent programmable dead time, programmable leading edge blanking (four steps), programmable 6-bit slope compensation and an integrated internal programmable oscillator for fixed-frequency applications. An integrated 8-bit reference voltage

) is used for setting output voltage or current. An

REF

internal comparator supports quasi-resonant applications. Additional Capture and Compare modules are integrated for additional control, including enhanced dimming capability. The MCP19114/5 devices contain two internal LDOs. A 5V LDO is used to power the internal processor and provide 5V externally. This 5V external output can be used to supply the gate drive. An analog filter between the V output and the VDR input is recommended when implementing a 5V gate drive supplied from V

4.7 µF capacitors are recommended with one placed as close as possible to V possible to V

, separated by a 10 isolation resistor.

DO NOT exceed 10 µF on the V is required to implement higher gate drive voltages. By utilizing Microchip’s TC1240A voltage doubler supplied from V

to provide VDR, a 10V gate drive can be

achieved. A 4V LDO is used to power the internal analog circuitry. The two low-side drivers can be used to operate the power converter in bidirectional mode, enabling the “shaping” of LED dimming current in LED applications or developing bidirectional power converters for battery-powered applications.

The MCP19114 is packaged in a 24-lead 4 mm x 4 mm QFN. The MCP19115 is packaged in a 28-lead 5 mm x 5 mm QFN.

microcontroller similar

and one as close as

. An external supply

. Two

The ability for system designers to configure application-specific features allows the MCP19114/5 to be offered in smaller packages than currently available in integrated devices today. The General Purpose Input/Output (GPIO) of the MCP19114/5 can be configured to offer a status output, a device enable, to control an external switch, a switching frequency synchronization output or input or even a device status or "heartbeat" indicator. This flexibility allows the MCP19114/5 packages and complete solutions to be smaller, thereby saving size and cost of the system printed circuit boards.

With integrated features like output current adjust and dynamic output voltage positioning, the MCP19114/5 family has the best in class performance and highest integration level currently available.

Power trains supported by this architecture include but are not limited to boost, flyback, quasi-resonant flyback, SEPIC, Ćuk, etc. Two low-side gate drivers are capable of sinking and sourcing 1A at 10V V

. With a

5V gate drive, the driver is capable of 0.5A sink and source. The user has the option to allow the V

UVLO

to shut down the drivers by setting the UVLOEN bit. When this bit is not set, the device drivers will ride through the UVLO condition and continue to operate until VDR reaches the gate drive UVLO value. This value is selectable at 2.7V or 5.4V and is always enabled. An internal reset for the microcontroller core is set to 2.0V. An internal comparator module is used to sense the desaturation of the flyback transformer to synchronize switching for quasi-resonant applications. The operating input voltage for normal device operation ranges from 4.5V to 42V with an absolute maximum of 44V. The maximum transient voltage is 48V for 500 ms.

C serial bus is used for device communications

An I from the PWM controller to the system.

 2014 Microchip Technology Inc. DS20005281A-page 9

Page 10

VDD(5V)

BGAP

UVLO

REF

OV REF

BGAP

PIC CORE

OSC

UVLO

PDRV

A=10

LEB

EA_SC

PWM Comp

PWM Logic

DESAT

QRS

GND

MCLR

DIMI

SDA

TEMP

BIN

I/O x 3

(x7 MCP19115)

Clamp

ccd

EN1

EN2

OVLO

GND

VDD

REF2

MUX to

GPB1

I/O

LDO1 LDO2

Bias Gen

AVDD(4V)

AVDD

REF2

DESAT

MUX

4V to 20V

8.8V to 44V

BGAP

DESAT

SOUT

DD_OK

RFB MUX

5k:

Gate

Drive

Timing

Gate Drive

Timing

P_COMP

OV_REF

REF2

REF

OVLO_REF

UVLO_REF

Interrupt and Logic to

PWM & PIC

FB_INT

AMUX

5V to 10V

4msb

VIN_UVLO

Log

Lin

Slope

Comp

ADJ

Offset

VIN_OVLO

OVLO

DMUX

PWM

VZC

UVLO

BGAP

2.7V or 5.4V

ADC

4msb

2lsb

BGAP

CHS1

CHS2

CHS3

CHS4

CHS5

CHS6

CHS8

CHS9

CHS10

See Electrical Characteristics

For Clamp Voltages

PDRV

SDRV

DESAT

GPIO

GNDPGND

VDD

COMP

4.5V to 42V

4.7 µF

10Ω

Place recommended V

VDD

and VDR4.7 µF

Capacitors as close to respective pins as possible

CHS0

IN/n

DS20005281A-page 10  2014 Microchip Technology Inc.

FIGURE 1-1: MCP19114/5 FLYBACK SYNCHRONOUS QUASI-RESONANT BLOCK DIAGRAM

MCP19114/5

Page 11

MCP19114/5

GND

PDRV

BIN

DIMI

DESAT

MCLR

CCD

MCP19114

COMP

I/O

TEMP SNS

SDRV

GND

4x424LdQFN

I/O

DESAT

I/O

TC1240 VOLTAGE DOUBLER

10V

GND

PDRV

BIN

DIMI

DESAT

MCLR

CCD

MCP19114

COMP

I/O

TEMP SNS

GND

SOUT

4x424LdQFN

I/O

SW1

SW2

DESAT

SDRV

SW1

SW2

I/O

FIGURE 1-2: MCP19114 CUK’ SYNCHRONOUS POSITIVE OUTPUT APPLICATION DIAGRAM

FIGURE 1-3: MCP19114 BOOST QUASI-RESONANT APPLICATION DIAGRAM

 2014 Microchip Technology Inc. DS20005281A-page 11

Page 12

MCP19114/5

Flash

Program Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr

RAM Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

TESTCLKIN

PORTGPA

8 Level Stack

256

4K x 14

bytes

(13-bit)

Power-up

Timer

Power-on

Reset

Watchdog

Timer

MCLR

VIN V

Timer0 Timer1

T0CKI

Configuration

8 MHz Internal

Oscillator

Timer2

I2C

GPA0

GPA1

GPA2 GPA3

GPA5

Analog Interface

SDA SCL

PMDATL

EEADDR

Self read/ write flash memory

Registers

PORTGPB

GPB0

GPB1

GPB6 (MCP19115)

GPB4 (MCP19115)

PWM

GPB5 (MCP19115)

GPA6 GPA7

GPB7 (MCP19115)

Enhanced

CCD

GPA6 GPB7 (MCP19115)

FIGURE 1-4: MICROCONTROLLER CORE BLOCK DIAGRAM

DS20005281A-page 12  2014 Microchip Technology Inc.

Page 13

MCP19114/5

2.0 PIN DESCRIPTION

The 24-lead MCP19114 and 28-lead MCP19115 devices feature pins that have multiple functions associated with each pin. Tab le 2 -1 provides a description of the different functions. Refer to

Section 2.1 “Detailed Pin Functional Description”

for more detailed information.

TABLE 2-1: MCP19114/5 PINOUT DESCRIPTION

Name Function

Input

Type

GPA0/AN0/TEST_OUT GPA0 TTL CMOS General-purpose I/O

AN0 AN — A/D Channel 0 input

TEST_OUT — — Internal analog/digital signal multiplexer output

GPA1/AN1/CLKPIN GPA1 TTL CMOS General-purpose I/O

AN1 AN — A/D Channel 1 input

CLKPIN ST CMOS Switching frequency clock input or output

GPA2/AN2/T0CKI/INT GPA2 ST CMOS General-purpose I/O

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — External interrupt

GPA3/AN3 GPA3 TTL CMOS General-purpose I/O

AN3 AN — A/D Channel 3 input

GPA5/MCLR

GPA5 TTL — General-purpose input only

MCLR

GPA6/CCD/ICSPDAT GPA6 ST CMOS General-purpose I/O

ICSPDAT ST CMOS Serial Programming Data I/O

CCD ST CMOS Single Compare output. Dual Capture input

GPA7/SCL/ICSPCLK GPA7 ST OD General-purpose open drain I/O

SCL I

ICSPCLK ST — Serial Programming Clock

GPB0/SDA GPB0 TTL OD General-purpose I/O

SDA I

GPB1/AN4/VREF2 GPB1 TTL CMOS General-purpose I/O

AN4 AN — A/D Channel 4 input

VREF2 — AN VREF2 DAC Output

GPB4/AN5/ICSPDAT

(MCP19115 Only)

GPB4 TTL CMOS General-purpose I/O

AN5 AN — A/D Channel 5 input

ICSPDAT ST CMOS Primary Serial Programming Data I/O

GPB5/AN6/ICSPCLK

(MCP19115 Only)

GPB5 TTL CMOS General-purpose I/O

AN6 AN — A/D Channel 6 input

ISCPCLK ST — Primary Serial Programming Clock

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the MODECON register. 3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the MODECON

Output

Type

Description

ST — Master Clear with internal pull-up

C™ OD I2C clock

C™ OD I2C data input/output

(3)

C = Schmitt Trigger input with I2C

(1)

(2)

 2014 Microchip Technology Inc. DS20005281A-page 13

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MCP19114/5

TABLE 2-1: MCP19114/5 PINOUT DESCRIPTION (CONTINUED)

Name Function

GPB6/AN7

(MCP19115 Only)

GPB7/CCD

(MCP19115 Only)

GND

GPB6 TTL CMOS General-purpose I/O

AN7 AN — A/D Channel 7 input

GPB7 TTL CMOS General-purpose I/O

CCD ST CMOS Single Compare output. Dual Capture input.

GND

Input Type

PDRV PDRV — — Primary Low-Side MOSFET gate drive

SDRV SDRV — — Secondary Low-Side MOSFET gate drive

COMP

DESATP/I

DESAT

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

SOUT

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

COMP

DESATP/I

DESAT

SOUT

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

Output

Type

Description

— — Device input supply voltage

— — Internal +5V LDO output pin

— — Gate drive supply voltage

— — Small signal quiet ground

— — Large signal power ground

— — Primary input current sense

— — Secondary current sense amplifier negative input

— — Secondary current sense amplifier positive input

— — Sense voltage compared to overvoltage DAC

— — Error amplifier feedback input

— — Error amplifier output

— — DESATP: DESAT detect comparator positive input

: Secondary current sense amplifier output

SOUT

— — DESATN: DESAT detect comparator negative

input

C = Schmitt Trigger input with I2C

DS20005281A-page 14  2014 Microchip Technology Inc.

Page 15

MCP19114/5

2.1 Detailed Pin Functional Description

2.1.1 GPA0 PIN

GPA0 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available.

AN0 is an input to the A/D. To configure this pin to be read by the A/D on channel 0, bits TRISA0 and ANSA0 must be set.

The ABECON register can be configured to set this pin to the TEST_OUT function. It is a buffered output of the internal analog or digital signal multiplexers. Analog signals present on this pin are controlled by the ADCON0 register. Digital signals present on this pin are controlled by the ABECON register.

2.1.2 GPA1 PIN

GPA1 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available.

AN1 is an input to the A/D. To configure this pin to be read by the A/D on channel 1, bits TRISA1 and ANSA1 must be set.

When the MCP19114/5 are configured as a MASTER or SLAVE, this pin is configured to be the switching frequency synchronization input or output (CLKPIN).

2.1.3 GPA2 PIN

GPA2 is a general-purpose ST input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available.

AN2 is an input to the A/D. To configure this pin to be read by the A/D on channel 2, bits TRISA2 and ANSA2 must be set.

When bit T0CS is set in the OPTION_REG register, the

T0CKI function is enabled. Refer to Section 22.0

“Timer0 Module” for more information.

GPA2 can also be configured as an external interrupt

by setting the INTE bit. Refer to Section 14.2

“GPA2/INT Interrupt” for more information.

2.1.5 GPA5 PIN

GPA5 is a general-purpose TTL input only pin. An internal weak pull-up and interrupt-on-change are also available.

For programming purposes, this pin is to be connected to the MCLR

Section 30.0 “In-Circuit Serial Programming™ (ICSP™)” for more information.

This pin is MCLR CONFIG register.

pin of the serial programmer. Refer to

when the MCLRE bit is set in the

2.1.6 GPA6 PIN

GPA6 is a general-purpose CMOS output ST input pin whose data direction is controlled in TRISGPA.

ICSPDAT is a serial programming data I/O function. This can be used in conjunction with ICSPCLK to serial program the device.

GPA6 is part of the CCD Module. For more information,

refer to Section 26.0 “Dual Capture/Compare (CCD)

Module”.

2.1.7 GPA7 PIN

GPA7 is a true open drain general-purpose pin whose data direction is controlled in TRISGPA. There is no internal connection between this pin and device VDD. This pin does not have a weak pull-up, but interrupt-on-change is available.

This pin is the primary ICSPCLK input. For MCP19115, this pin is ALT1_ICSPCLK. This can be used in conjunction with ICSPDAT to serial program the device.

When the MCP19114/5 is configured for I

communication, Section 28.2 “I

GPA7 functions as the I be configured as an input to allow proper operation.

C Mode Overview ”,

C clock (SCL). This pin must

2.1.4 GPA3 PIN

GPA3 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available.

AN3 is an input to the A/D. To configure this pin to be read by the A/D on channel 3, bits TRISA3 and ANSA3 must be set.

 2014 Microchip Technology Inc. DS20005281A-page 15

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MCP19114/5

2.1.8 GPB0 PIN

GPB0 is a true open drain general-purpose pin whose data direction is controlled in TRISGPB. There is no internal connection between this pin and device V This pin does not have a weak pull-up, but interrupt-on-change is available. When the MCP19114/5 are configured for I

Section 28.2 “I

as the I an input to allow proper operation.

C Mode Overvi ew”, GPB0 functions

C clock (SDA). This pin must be configured as

C communication,

2.1.9 GPB1 PIN

GPB1 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available.

AN4 is an input to the A/D. To configure this pin to be read by the A/D on channel 4, bits TRISB1 and ANSB1 must be set.

When the MCP19114/5 are configured as a MASTER, this pin is configured to be the V

DAC output.

REF2

2.1.10 GPB4 PIN (MCP19115 ONLY)

GPB4 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available.

AN5 is an input to the A/D. To configure this pin to be read by the A/D on channel 5, bits TRISB4 and ANSB4 must be set.

ICSPDAT is the primary serial programming data I/O function. This is used in conjunction with ICSPCLK to serial program the device.

2.1.11 GPB5 PIN (MCP19115 ONLY)

GPB5 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available.

AN6 is an input to the A/D. To configure this pin to be read by the A/D on channel 6, bits TRISB5 and ANSB5 must be set.

ICSPCLK is the primary serial programming clock function. This is used in conjunction with ICSPDAT to serial program the device.

2.1.12 GPB6 PIN (MCP19115 ONLY)

GPB6 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available.

AN7 is an input to the A/D. To configure this pin to be read by the A/D on channel 7, bits TRISB6 and ANSB6 must be set.

2.1.13 GPB7 PIN (MCP19115 ONLY)

GPB7 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An

internal weak pull-up and interrupt-on-change are also available.

GPB7 is part of the CCD Module. For more information,

refer to Section 26.0 “Dual Capture/Compare (CCD)

Module”.

2.1.14 DESATN PIN

Internal comparator inverting input. Used during quasi-resonant operation for desaturation detection.

2.1.15 DESATP/I

When using the internal comparator for desaturation detection during quasi-resonant operation, this pin connects to the comparator’s non-inverting input. The output of the remote sense current sense amplifier gets configured to utilize the 5 k internal feedback resistor. When not utilizing the internal comparator and not configured to use the 5 k internal feedback resistor, the current sense amplifier gets connected to this pin

SOUT

and is I

SOUT

2.1.16 ISP PIN

The non-inverting input to internal current sense amplifier, typically used to differentially remote sense secondary current. This pin can be internally pulled-up

by setting the <ISPUEN> bit in the PE1 register.

to V

2.1.17 ISN PIN

The inverting input to internal current sense amplifier, typically used to differentially remote sense secondary current.

2.1.18 IP PIN

Primary input current sense for current mode control and peak current limit. For voltage mode control, this pin can be connected to an artificial ramp.

2.1.19 A

is the small signal ground connection pin. This

GND

pin should be connected to the exposed pad on the bottom of the package.

2.1.20 P

Connect all large signal level ground returns to P These large-signal level ground traces should have a small loop area and minimal length to prevent coupling of switching noise to sensitive traces.

GND

DS20005281A-page 16  2014 Microchip Technology Inc.

Page 17

2.1.21 SDRV PIN

The gate of the low-side secondary MOSFET is connected to SDRV. The PCB trace connecting SDRV to the gate must be of minimal length and appropriate width to handle the high peak drive current and fast voltage transitions.

2.1.22 PDRV PIN

The gate of the low-side primary MOSFET is connected to PDRV. The PCB tracing connecting PDRV to the gate must be of minimal length and appropriate width to handle the high-peak drive currents and fast voltage transitions.

2.1.23 VDR PIN

The supply for the low-side drivers is connected to this pin and has an absolute maximum rating of +13.5V. This pin can be connected by an RC filter to the V pin.

2.1.24 VDD PIN

The output of the internal +5.0V regulator is connected to this pin. It is recommended that a 1.0 µF bypass capacitor be connected between this pin and the GND pin of the device. The bypass capacitor should be physically placed close to the device.

MCP19114/5

2.1.25 VIN PIN

Input power connection pin of the device. It is recommended that capacitance be placed between this pin and the GND pin of the device.

2.1.26 VS PIN

Analog input connected to the non-inverting input of the overvoltage comparator. Typically used as output voltage overvoltage protection. The inverting input of the overvoltage comparator is controlled by the OV REF DAC.

2.1.27 IFB PIN

Error amplifier inverting feedback connection.

2.1.28 I

Error amplifier output signal.

COMP

2.1.29 EXPOSED PAD (EP)

It is recommended to connect the exposed pad to

GND

 2014 Microchip Technology Inc. DS20005281A-page 17

Page 18

MCP19114/5

NOTES:

DS20005281A-page 18  2014 Microchip Technology Inc.

Page 19

3.0 FUNCTIONAL DESCRIPTION

MCP19114/5

3.1 Linear Regulators

The operating input voltage for the MCP19114/5 ranges from 4.5V to 42V. There are two internal Low Dropout (LDO) voltage regulators. A 5V LDO is used to power the internal processor and provide a 5V output for external usage. A second LDO (V regulator and is used to power the remaining analog internal circuitry. Using an LDO to power the MCP19114/5, the input voltage is monitored using a resistor divider. The MCP19114/5 also incorporate

brown-out protection. Refer to Section 13.3

“Brown-out Reset (BOR)” for details. The PIC core

will reset at 2.0V V

AVD D

) is a 4V

3.2 Output Drive Circuitry

The MCP19114/5 integrate two low-side drivers used to drive the external low-side N-Channel power MOSFETs for synchronous applications, such as synchronous flyback and synchronous Ćuk converters. Both converter types can be configured for non-synchronous control by replacing the synchronous FET with a diode. The flyback is also capable of quasi-resonant operation. The MCP19114/5 can also be configured as a Boost or SEPIC switch-mode power supply (SMPS). In Boost mode, non-synchronous fixed-frequency or non-synchronous quasi-resonant control can be utilized. This device can also be used as a SEPIC SMPS in fixed-frequency non-synchronous mode. The low-side drive is capable of switching the MOSFET at high frequency in typical SMPS applications. The gate drive (V 5V to 10V. The drive strength is capable of up to 1A sink/source with 10V gate drive and down to 0.5A sink/source with 5V gate drive. A programmable delay is used to set the gate turn-on dead time. This prevents overlap and shoot-through currents that can decrease the converter efficiency. Each driver shall have its own EN input controlled by the microcontroller core.

) can be supplied from

3.3 Current Sense

The output current is differentially sensed by the MCP19114/5. In low-current applications, this helps maintain high system efficiency by minimizing power dissipation in current sense resistors. Differential current sensing also minimizes external ground shift errors. The internal differential amplifier has a precision gain of 10V/V.

3.4 Peak Current Mode

The MCP19114/5 is a peak current mode controlled device with the current sensing element in series with the primary side MOSFET. Programmable Leading Edge Blanking can be implemented to blank current spikes resulting from turn on. The blank time is controlled from the ICLEBCON register.

Primary Input Current Offset Adjust is also available via user programmability, thus limiting peak primary input current. This offset adjustment is controlled by the ICOACON register.

3.5 Magnetic Desaturation Detection

An internal comparator module is used to detect power train magnetic desaturation for quasi-resonant applications. The comparator output is used as a signal to synchronize the start of the next switching cycle. This operation differs from the traditional fixed-frequency application. The DESAT comparator output can be enabled and routed into the PWM circuitry or disabled for fixed-frequency applications. During Quasi-Resonant (QR) operation, the DESAT comparator output is enabled and combined with a pair of one-shot timers and a flip-flop to sustain PWM operation. Timer2 (TMR2) must be initialized and set to run at a frequency lower than the minimum QR operating frequency. When the CDSWDE bit is set in the DESATCON register, TMR2 serves as a watchdog.

An example of the order of events for a Flyback SMPS in synchronous QR operation is as follows:

The primary gate drive (PDRV) goes high. The output of the DESAT comparator is high. The primary current increases until I and causes PWM comparator output to go low. The PDRV goes low and the secondary gate drive (SDRV) goes high (after programmed dead time). This triggers the first one-shot to send a 200 ns pulse that resets the flip-flop and TMR2 (WDM_RESET). The 200 ns one-shot pulse design is implemented to mask out any spurious transitions at the DESAT comparator output caused by switching noise. The SDRV stays high until the secondary winding completely runs out of energy, at which time the output capacitance begins to source current back through the winding and secondary MOSFET. The DESAT comparator detects this and its output goes low. This sets the flip-flop and triggers the second one-shot to send a 33 ns pulse to the control logic, causing the SDRV to go low and the PDRV to go high (after programmed dead time). The cycle then repeats. If, for any reason, the reset one-shot does not fire, the WDM_RESET signal stays low and TMR2 is allowed to run until the PWM signal kicks off a new cycle.

The desaturation comparator module is controlled by the DESATCON register.

reaches the level of the Error Amp

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Page 20

MCP19114/5

3.6 Start-up

To control the output current during start-up, the MCP19114/5 have the capability to monotonically increase system current, at the user’s discretion. This is accomplished through the control of the reference voltage DAC (V user control via software.

). The entire start-up profile is under

REF

3.7 Driver Control Circuitry

The internal driver control circuitry of the MCP19114/5 is comprised of an error amplifier (EA), a high-speed comparator and a latch similar to the MCP1631.

The error amplifier generates the control voltage used by the high-speed PWM comparator. There is an internally generated reference voltage, V difference or error between this internal reference voltage and the actual feedback voltage is the control voltage. Some applications will implement parked times where the gate drives are not active. For example, when changing between LED strings and after voltage repositioning, the user can disable the gate drives and park the error amplifier output low. During the time when the EA is parked, its output will be clamped low (1 * BG) such that it is in a known state when reactivated. Before the output switches are re-enabled, it may be necessary to re-enable the EA some time prior to enabling the output drivers. This prior-EA enable time will allow the EA to slew towards the intended target and prevent the secondary switch from turning on for an extensive period of time, unintentionally discharging the output capacitance and pulling the output voltage down. External compensation is used to stabilize the control system.

Since the MCP19114/5 are peak current mode controlled, the comparator compares the primary peak current waveform (I flowing in the primary side with the error amplifier control output voltage. This error amplifier control output voltage also has user-programmable slope compensation subtracted from it. In fixed-frequency applications, the slope compensation signal is generated to be greater than 1/2 the down slope of the inductor current waveform and is controlled by the SLPCRCON register. Offset adjust ability is also available to set the peak current limit of the primary switch for overcurrent protection. The range of the slope compensation ramp is specified. When the current sense signal reaches the level of the control voltage minus slope compensation, the on cycle is terminated and the external switch is latched off until the beginning of the next cycle which begins at the next clock cycle.

To improve current regulation at low levels, a pedestal voltage (VZC) set to the BG (1.23V) is implemented. This virtual ground serves as the reference for the error amplifier (A1), slope compensation, current sense amplifier (A2) and the I

) that is based upon the current

offset adjustment.

REF

. The

An S-R latch (Set-Rest-Flip-Flop) is used to prevent the PWM circuitry from turning the external switch on until the beginning of the next clock cycle.

3.8 Fixed PWM Frequency

The switching frequency of the MCP19114/5 while not controlled by the DESAT comparator output is generated by using a single edge of the 8 MHz internal clock. The user sets the MCP19114/5 switching frequency by configuring the PR2 register. The maximum allowable PDRV duty cycle is adjustable and is controlled by the PWMRL register. The programmable range of the switching frequency will be

31.25 kHz to 2 MHz. The available switching frequency below 2 MHz is defined as F a whole number between 4  N  256. Refer to

Section 25.0 “Enhanced PWM Module” for details.

3.9 V

This reference is used to generate the voltage connected to the non-inverting input of the error amplifier. The entire analog control loop is raised to a virtual ground pedestal equal to the Band Gap voltage (1.23V).

REF

= 8 MHz/N, where N is

3.10 OV REF

This reference is used to set the output overvoltage set point. It is compared to the V typically proportional to the output voltage based on a resistor divider. OV protection, when enabled, can be set to a value for the protection of system circuitry or it can be used to “ripple” regulate the converter output voltage for repositioning purposes. For details, refer to

input pin, which is

3.11 Independent Gate Drive with Programmable Delay

Two independent low-side gate drives are integrated for synchronous applications. Programmable delay has been implemented to improve efficiency and prevent shoot-through currents. Each gate drive has an independent enable input controlled by the PE1 register and programmable dead time controlled by the DEADCON register.

DS20005281A-page 20  2014 Microchip Technology Inc.

Page 21

3.12 Temperature Management

3.12.1 THERMAL SHUTDOWN

To protect the MCP19114/5 from overtemperature conditions, a 150°C junction temperature thermal shutdown has been implemented. When the junction temperature reaches this limit, the device disables the output drivers. In Shutdown mode, both PDRV and SDRV outputs are disabled and the overtemperature flag (OTIF) is set in the PIR2 register. When the junction temperature is reduced by 20°C to 130°C, the MCP19114/5 can resume normal output drive switching.

3.12.2 TEMPERATURE REPORTING

The MCP19114/5 have a second on-chip temperature monitoring circuit that can be read by the ADC through

the analog test MUX. Refer to Section 20.0 “In ternal

Temperature Indicator Module” for details on this

internal temperature monitoring circuit.

MCP19114/5

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MCP19114/5

4.0 ELECTRICAL CHARACTERISTICS

4.1 ABSOLUTE MAXIMUM RATINGS †

VIN-V

(transient < 500 ms)............................................................................................................................................+48V

PDRV ..................................................................................................................................(GND - 0.3V) to (V

SDRV ....................................................................... ..........................................................(GND - 0.3V) to (V

Voltage on MCLR

Maximum voltage: any other pin .................................. ...................................................+(V

(operating) .................................................................................................................................................-0.3V to +44V

GND

+0.3V)

Internally Generated ......................................... ...............................................................................................+6.5V

Externally Generated........................................ .............................................................................................+13.5V

with respect to GND.................... ...............................................................................-0.3V to +13.5V

- 0.3V) to (VDD+0.3V)

GND

Maximum output current sunk by any single I/O pin .... ..........................................................................................25 mA

Maximum output current sourced by any single I/O pin ..........................................................................................25 mA

Maximum current sunk by all GPIO.............................. ..........................................................................................90 mA

Maximum current sourced by all GPIO ........................ ..........................................................................................35 mA

Storage Temperature.................................................... ..........................................................................-65°C to +150°C

Maximum Junction Temperature .................................. ........................................................................................+150°C

Operating Junction Temperature.................................. ..........................................................................-40°C to +125°C

ESD protection on all pins (HBM)................................. ......................................................................................... 2.0 kV

ESD protection on all pins (MM)................................... ........................................................................................... 200V

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

4.2 Electrical Characteristics

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Input

Input Voltage V

Input Quiescent

4.5 — 42 V —510 mA Not Switching, +V

Current

Shutdown Current

Linear Regulator V

Internal Circuitry

SHDN

—30150 µA V

4.75 5.0 5.5 VV

Bias Voltage

Maximum External V

Output Current

Line Regulation V

Load Regulation V

Output Short Circuit

DD-OUT

DD_OUT

DD-OUT

DD_SC

* VIN)

35 ——mAV

-0.1 0.002 0.1 %/V (V

-0.65 0.1 +0.65 %I

—50—mAV

Current

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

and VDD.

=+25°C, Boldface specifications

=5V

SEN

= 12V

Note 1

= 6.0V to 42V

= 6.0V to 42V,

Note 3

+1.0V) VIN 20V

Note 3

DD_OUT

= 1 mA to 20 mA

Note 3

=(VDD+1.0V)

Note 3

DS20005281A-page 22  2014 Microchip Technology Inc.

Page 23

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Dropout Voltage VIN-V

Power Supply

PSRR

LDO

—0.30.5 VI

—60—dBf 1000 Hz,

Rejection Ratio

Linear Regulator V

Internal Analog

AVDD

AVD D

—4.0—V

Supply Voltage

Band Gap Voltage BG — 1.23 — V Trimmed at 1.0% tolerance

Band Gap

TOL

-2.5 — +2.5 %

To le r a nc e

Input UVLO Voltage

UVLO Range UVLO

UVLO

Trip

UVLO

TOL

4.0 — 20 VV

-14 — 14 %V

To le r a nc e

UVLO Hysteresis UVLO

HYS

— 4 — % Hysteresis is based upon

Resolution nbits — 6 — Bits Logarithmic Steps

UVLO Comparator

Input-to-Output

TD — 5 — µs 100 ns rise time to 1V

Delay

Input OVLO Voltage

OVLO Range OVLO

OVLO

Trip

OVLO

TOL

8.8 — 44 VV

-14 — 14 %V

To le r a nc e

OVLO Hysteresis OVLO

HYS

— 5 — % Hysteresis is based upon the

Resolution nbits — 6 — Bits Logarithmic Steps

OVLO Comparator

Input-to-Output

TD — 5 — µs 100 ns rise time to 1V

Delay

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

and VDD.

=+25°C, Boldface specifications

DD_OUT

=20mA,

Note 3, Note 4

DD_OUT

=25mA

=0µF, CDD=1µF

Falling

UVLO trip set to 9V VINUVLO = 0x21h

the UVLO

setting UVLO trip set to 9V VINUVLO = 0x21h

overdrive on V

VIN> UVLO to flag set

Rising

OVLO trip set to 18V VINOVLO = 0x1Fh

OVLO

setting OVLO trip set to 18V VINOVLO = 0x1Fh

overdrive on V

VIN> OVLO to flag set

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Page 24

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Output OV DAC

Resolution nbits — 8 — Bits Linear DAC

Full Scale Range FSR 0 — 2 * BG V

To le r a nc e O VR E F

TOL

-10 — +10 % Full Scale, Code = 0xFF

Output OV Comparator

OV Hysteresis OV

Input Bias Current I

Common-Mode

HYS

BIAS

CMR

—50—mV

—±1—µA

0—3.0VNote 2

Input Voltage Range

Input-to-Output

TD — 200 — ns Note 2

Delay

V oltage Reference DAC (V

REF

)

Resolution nbits — 8 — V/V Linear DAC

Full Scale Range FSR BG — 2 * BG V Pedestal set to BG

V oltage Reference DAC (V

REF2

)

Resolution nbits — 8 — Bits Linear DAC

Full Scale Range FSR 0 — BG V

Sink Current I

Source Current I

SINK

SOURCE

To le r a nc e VR E F2

TOL

-3 ——mAV

3 ——mAV

-10 — +10 % Full Scale, Code = 0xFF

Current Sense Amplifier (A2)

Amplifier PSRR PSRR — 65 — dB V

Closed Loop

VCL

—10—V/VR

Voltage Gain

Low-Level Output V

Gain Bandwidth

GBWP — 10 — MHz V

—500—mVR

Product

Input Impedance R

Sink Current I

Source Current I

SOURCE

SINK

—10—k

-3 ——mAI

3 ——mAI

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

and VDD.

=+25°C, Boldface specifications

100 ns rise time to 1V overdrive on V

VS> OV to flag set

=0V,

REF2

=300to BG

=BG,

REF2

=300to GND

=2*BG

=5k to 2.048V,

100 mV < A2 <

– 100 mV, VCM=BG

AVD D

=5k to 2.048V

=4V

AVD D

SP=ISN

=GND

=300 to 2 * BG

=GND

=300 to GND

DS20005281A-page 24  2014 Microchip Technology Inc.

Page 25

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Common Mode

CMR

GND – 0.3 — VBG+0.3 V Note 2

Range

Common Mode

CMRR — 70 — dB

Rejection Ratio

Internal Feedback

FB_INT

—5—k

Resistor

Internal Feedback

FB_INT_TOL

—2—%Trimmed

Resistor Tol

Pedestal Voltage

VZC — BG — V

Level

Error Amplifier (EA)

Input Offset Voltage V

Common Mode

CMRR — 65 — dB V

—2—mV

Rejection Ratio

Open-Loop Voltage

VOL

—70—dBNote 2

Gain

Low-level Clamp

BG - 0.35 BG - 0.22 BG - 0.1 VRL=5k to 2.048V

value

Gain Bandwidth

GBWP — 3.5 — MHz

Product

Error Amplifier Sink

SINK

-3 ——mAV

Current

Error Amplifier

SOURCE

3 ——mAV

Source Current

Maximum Error

EA_MAX

— 2 * BG — V EA Output clamped to Amplifier Output High-Level Clamp

Peak Current Sense Input

Maximum Primary

IP_MAX

—BG1.5VNote 2 Current Sense Signal Voltage

PWM Comparator

Input-to-Output

TD — 20 — ns Note 2

Delay

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

and VDD.

=+25°C, Boldface specifications

= 0V to BG

=BG, IFB=I

REF

RL=150 to 1.5 * BG

=2*BG, IFB=I

REF

RL=150 to 1.5 * BG

2*BG Voltage

COMP

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MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Peak Current Leading Edge Blanking

Resolution LEB — 2 — Bits

Blanking Time

LEB

RANGE

0 — 256 ns 4-Step Programmable Range

Adjustable Range

Offset Adjustment (IP Sense)

Resolution OS

Offset Adjustment

ADJ_RANGE

ADJ

—4—Bits

0—750mV

Range

Offset Adjustment

ADJ_STEP

— 50 — mV Linear Steps

Step Size

Adjustable Slope Compens ation

Resolution SC

RES

— 6 — Bits Log Steps

Slope m 4.1 — 432.5 mV/µs

Slope Step Size SC

Ramp Set Point

STEP

TOL

— 8 — % Log Steps

—±1±30%

To le ra nc e

Desaturation Detection Compa r ator

Input Offset Voltage V

Input Bias Current I

Common-Mode

BIAS

CMR

— ±1 — mV Trimmed, 5 bits adjustable

— ±1 — µA Internal Circuit Dependent

GND – 0.3V — 2.7 V Note 2

Input Voltage Range

Input-to-Output

TD — 20 — ns

Delay

VDR UVLO

UVLO

(2.7V V

UVLO

(2.7 V

UVLO

Rising)

Falling)

DR_UVLO_2.7_F

DR_UVLO_2.7_R

DR_UVLO 2.7 HYS

2.45 — 2.9 V

2.68 — 3.23 V

190 — 415 mV

(2.7V) Hysteresis

UVLO

(5.4V V

UVLO

(5.4V V

UVLO

Falling)

Rising)

DR_UVLO_5.4_F

DR_UVLO_5.4_R

DR_UVLO 5.4 HYS

4.7 — 5.96 V

5.15 — 6.56 V

380 — 830 mV

(5.4V) Hysteresis

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

and VDD.

=+25°C, Boldface specifications

(0, 50,100, and 200 ns)

Note 2

DS20005281A-page 26  2014 Microchip Technology Inc.

Page 27

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

Output Driver (PDRV and SDRV)

PDRV/SDRV Gate

DR-SRC

——13.5  V

Drive Source Resistance

PDRV/SDRV Gate

DR-SINK

——12  V

Drive Sink Resistance

PDRV/SDRV Gate Drive Source

DR-SRC

—0.5—AV

—1.0— Current

PDRV/SDRV Gate Drive Sink Current

DR-SINK

—0.5—AV

—1.0—

Dead Time Adjustment

Resolution DT

Dead Time

RES

RANGE

—4—Bits

16 — 256 ns Adjustable Range

Dead Time Step

STEP

— 16 — ns Linear Steps Size

Dead Time

TOL

—±8—ns To le r a nc e

Oscillator/PWM

Internal Oscillator

OSC

7.60 8.00 8.40 MHz

Frequency

Switching

—F Frequency

Switching

N4—255—F Frequency Range Select

A/D Converter (ADC) Characteristics

Resolution N

Integral Error E

Differential Error E

Offset Error E

Gain Error E

Reference Voltage V

REF_ADC

Full-Scale Range FSR

OFF

A/D

——10Bits

——±1LSbV

— — ±1 LSb No missing code in 10 bits,

— +3.0 +5.0 LSb V

—±2±5LSbV

—V

GND — V

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

/N — MHz

OSC

AVD D

—V

AVD D

—

and VDD.

=+25°C, Boldface specifications

=4.5V

Note 2

=4.5V

Note 2

=5V

=10V

Note 2

=5V

=10V

Note 2

=2MHz

MAX

REF_ADC=VAVD D

 2014 Microchip Technology Inc. DS20005281A-page 27

Page 28

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

Parameters Sym. Min. Typ. Max. Units Conditions

GPIO Pins

Maximum GPIO

SINK_GPIO

——90mANote 5

Sink Current

Maximum GPIO

SOURCE_GPIO

——35mANote 5

Source Current

GPIO Weak Pull-up

PULL-UP_GPIO

50 250 400 µA

Current

GPIO Input Low

GPIO_IL

GND — 0.8 V I/O Port with TTL buffer,

Voltage

GND — 0.2V

GND —

GPIO Input High

GPIO_IH

2.0 — V

Voltage

0.8V

GPIO Output Low

GPIO_OL

——0.12V

Voltage

GPIO Output High

GPIO_OH

VDD-0.7 — — V IOH=2.5mA, VDD=5V

Voltage

GPIO Input

GPIO_I

—±0.1±1 µA Negative current is defined

Leakage Current

Thermal Shutdown

Thermal Shutdown T

Thermal Shutdown

SHD_HYS

SHD

—150—°C

—20—°C

Hysteresis

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested. 3: V

is the voltage present at the VDD pin.

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

maximum of 15 mA.

= 12V, FSW=150kHz, T

— V

0.2V

and VDD.

=+25°C, Boldface specifications

=5V

V I/O Port with Schmitt

Trigger buffer, V

VMCLR

V I/O Port with TTL buffer,

=5V

V I/O Port with Schmitt

Trigger buffer, V

VMCLR

VIOL=7mA, VDD=5V

as current sourced by the pin.

=5V

4.3 Thermal Specifications

Parameters Sym. Min. Typ. Max. Units

Temperature Ranges

Specified Temperature Range T

Operating Junction Temperature Range T

Maximum Junction Temperature T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 24L-QFN 4x4  Thermal Resistance, 28L-QFN 5x5 

DS20005281A-page 28  2014 Microchip Technology Inc.

-40 — +125 °C

——+150°C

-65 — +150 °C

—42—°C/W

— 35.3 — °C/W

Page 29

5.0 DIGITAL ELECTRICAL CHARACTERISTICS

5.1 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

MCP19114/5

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port wr WR mc MCLR Uppercase letters and their meanings:

FFall PPeriod HHigh RRise I Invalid (high-impedance) V Valid L Low Z High-impedance

C only

AA output access High High BUF Bus free Low Low

(I2C specifications only)

CC:ST

HD Hold SU Setup

DAT DATA input hold STO STOP condition STA START condition

3. T

4. Ts (I

(I2C specifications only)

CC:ST

C specifications only)

 2014 Microchip Technology Inc. DS20005281A-page 29

Page 30

MCP19114/5

VDD/2

Pin Pin

RL=464

= 50 pF for all GPIO pins

Load Condition 1 Load Condition 2

OSC

Q4 Q1 Q2 Q3 Q4 Q1

FIGURE 5-1: LOAD CONDITIONS

5.2 AC Characteristics: MCP19114 (Industrial, Extended)

FIGURE 5-2: EXTERNAL CLOCK TIMING

TABLE 5-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

No.

2TCYInstruction Cycle Time

Note 1: Instruction cycle period (T

DS20005281A-page 30  2014 Microchip Technology Inc.

Sym. Characteristic Min. Typ.†Max. Units Conditions

OSC

Oscillator Frequency

Oscillator Period

(1)

—8 —MHz

— 250 — ns

—TCY ns TCY = 4*T

OSC

* These parameters are characterized but not tested. † Data in “Typ.” column is at V

=12V (VDD= 5V), 25°C unless otherwise stated. These parameters are for

design guidance only and are not tested.

) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Page 31

MCP19114/5

OSC

I/O Pin (input)

I/O Pin (output)

Q2 Q3

20, 21

22 23

old value

new value

FIGURE 5-3: I/O TIMING

TABLE 5-2: I/O TIMING REQUIREMENTS

Param.

No.

17 TosH2ioV OSC1 (Q1 cycle) to

18 TosH2ioI OSC1(Q2 cycle) to Port input

19 TioV2osH Port input valid to OSC1

20 TioR Port output rise time — 32 40 ns

21 TioF Port output fall time — 15 30 ns

22* Tinp INT pin high or low time 25 — — ns

23* T

Sym. Characteristic Min. Typ.†Max. Units Conditions

— 50 70* ns

Port out valid

50 — — ns invalid (I/O in hold time)

20 — — ns (I/O in setup time)

RABP

* These parameters are characterized but not tested. † Data in “Typ” column is at V

GPIO interrupt-on-change new input level time

=12V (VDD=5V), 25C unless otherwise stated.

——ns

 2014 Microchip Technology Inc. DS20005281A-page 31

Page 32

MCP19114/5

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

Reset

Watchdog

Timer Reset

I/O Pins

VDD

VHY

VDD+BVHY

Reset (due to BOR)

(device not in Brown-Out Reset) (device in Brown-Out Reset) 64 ms time out (if PWRTE)

FIGURE 5-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 5-5: BROWN-OUT RESET TIMING AND CHARACTERISTICS

DS20005281A-page 32  2014 Microchip Technology Inc.

Page 33

MCP19114/5

T0CKI

TMR0

TABLE 5-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER REQUIREMENTS

Param.

No.

Sym. Characteristic Min. Typ.

†

Max. Units Conditions

30 T

31 T

MCL

WDT

MCLR Pulse Width (low) 2 — — sVDD= 5 V, -40°C to +85°C

Watchdog Timer Time-out

71833msV

Period (No Prescaler)

32 T

OST

Oscillation Start-up Timer

— 1024T

OSC

——T

Period

33* T

34 T

PWRT

IOZ

Power up Timer Period

WDT

)

(4 x T

I/O high-impedance from

Low or Watchdog Timer

MCLR

28 72 132 ms V

——2.0µs

Reset

Brown-out Reset voltage 2.0 — 2.3 V

Brown-out Hysteresis — 100 — mV

Brown-out Reset pulse width 100* — — µs VDD B

Delay from clock edge to timer

TMR

OSC

—7T

OSC

35 T

TCKEZ-

VDD

VHY

BCR

increment

* These parameters are characterized but not tested. † Data in “Typ” column is at V

=12V (VDD=AVDD= 5V), 25°C unless otherwise stated. These parameters

are for design guidance only and are not tested.

FIGURE 5-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMING

= 5 V, -40°C to +85°C

= OSC1 period

OSC

= 5 V, -40°C to +85°C

(D005)

VDD

 2014 Microchip Technology Inc. DS20005281A-page 33

Page 34

MCP19114/5

TCY40+

-----------------------

Note: Refer to Figure 5-1 for load conditions.

53 54

PWM (CLKPIN)

TABLE 5-4: TIMER0EXTERNAL CLOCK REQUIREMENTS

Param.

No.

40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY+20 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5T

42* Tt0P T0CKI Period Greater of:

Sym. Characteristic Min. Typ.

With

Prescaler

With

Prescaler

* These parameters are characterized but not tested. † Data in “Typ.” column is at V

and are not tested.

= 12V, 25°C unless otherwise stated. These parameters are for design guidance only

10 — — ns

+20 — — ns

10 — — ns

20 or

FIGURE 5-7: PWM TIMINGS

†

Max. Units Conditions

— — ns N = prescale

value

(2, 4, ..., 256)

TABLE 5-5: PWM REQUIREMENTS

Param.

Sym. Characteristic Min. Typ.

No.

53* TccR PWM (CLKPIN) output fall time — 10 25 ns

54* TccF PWM (CLKPIN) output fall time — 10 25 ns

* These parameters are characterized but not tested. † Data in “Typ” column is at V

=12V (AVDD= 4V), 25°C unless otherwise stated. Parameters are for

design guidance only and are not tested.

Max

†

Units Conditions

DS20005281A-page 34  2014 Microchip Technology Inc.

Page 35

MCP19114/5

TABLE 5-6: MCP19114/5 A/D CONVERTER (ADC) CHARACTERISTICS

Standard Operat ing Conditi ons (unle ss othe rwis e stated)

Operating temperature -40°C  T

Param.

No.

AD01 N

Sym. Characteristic Min. Typ.

Resolution — — 10 bits bit

AD02 EILIntegral Error — — 1LSbAVDD= 4.0V

AD03 E

AD04 E

AD07 E

AD07 V

AD08 Z

Differential Error — — 1 LSb No missing codes to 10 bits

Offset Error — +1.5 +2.0 LSb AVDD=4.0V

OFF

Gain Error — — 1LSbAVDD=4.0V

Full-Scale Range A

AIN

Recommended Impedance

AIN

of Analog Voltage Source

* These parameters are characterized but not tested. † Data in ‘Typ.’ column is at V

for design guidance only and are not tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: When ADC is off, it will not consume any current other than leakage current. The power-down current

specification includes any such leakage from the ADC module.

 +125°C

†

Max. Units Conditions

=4.0V

GND

—AVDDV

—— 10k

=12V (AVDD= 4V), 25°C unless otherwise stated. These parameters are

TABLE 5-7: MCP19114/5 A/D CONVERSION REQUIREMENTS

Standard Operat ing Conditi ons (unle ss othe rwis e stated) Operating temperature -40°C  T

Param.

AD130* T

Sym. Characteristic Min. Typ.

No.

A/D Clock Period 1.6 — 9.0 µs T

A/D Internal RC

Oscillator Period

AD131 T

CNV

Conversion Time

(not including

Acquisition Time)

AD132* T

AD133* T

ACQ

AMP

Acquisition Time — 11.5 — µs

Amplifier Settling

Time

AD134 T

Q4 to A/D Clock Start — T

* These parameters are characterized but not tested. † Data in ‘Typ.’ column is at VIN=12V (VDD=AVDD= 5V), 25°C unless otherwise stated. These parameters

are for design guidance only and are not tested.

Note 1: ADRESH and ADRESL registers may be read on the following T

 +125°C

†

Max. Units Conditions

1.6 4.0 6.0 µs ADCS<1:0> = 11 (ADRC mode)

—11—TADSet GO/DONE bit to new data in A/D

(1)

—— 5µs

/2 — —

OSC

-based

OSC

Result registers

cycle.

 2014 Microchip Technology Inc. DS20005281A-page 35

Page 36

MCP19114/5

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

NEW_DATA

987 3210

1/2 T

134

DONE

Note 1: If the A/D clock source is selected as RC, a time of T

is added before the A/D clock starts. This

allows the SLEEP instruction to be executed.

FIGURE 5-8: A/D CONVERSION TIMING

DS20005281A-page 36  2014 Microchip Technology Inc.

Page 37

MCP19114/5

6.0 CONFIGURING THE MCP19114/5

The MCP19114/5 are analog controllers with a digital peripheral. This means that device configuration is handled through register settings instead of adding external components. There are several internal configurable comparator modules used to interface analog circuits to digital processing that are very similar to a standard comparator module found in many PIC processors today (i.e. PIC16F1824/1828). The following sections detail how to set the analog control registers for all the configurable parameters.

6.1 Input Undervoltage and Overvoltage Lockout (UVLO and OVLO)

VINCON is the comparator control register for both the VINUVLO and VINOVLO registers. It contains the enable bits, the polarity edge detection bits and the status output bits for both protection circuits. The interrupt flags <UVLOIF> and <OVLOIF> in the PIR2 register are independent of the enable <UVLOEN> and <OVLOEN> bits in the VINCON register. The <UVLOOUT> undervoltage lockout status output bit in the VINCON register indicates if an UVLO event has occurred. The <OVLOOUT> overvoltage lockout status output bit in the VINCON register indicates if an OVLO event has occurred.

The VINUVLO register contains the digital value that sets the input undervoltage lockout. UVLO has a range of 4V to 20V. When the input voltage on the V the MCP19114/5 is below this programmed level and the <UVLOEN> bit in the VINCON register is set, both PDRV and SDRV gate drivers are disabled. This bit is automatically cleared when the MCP19114/5 V voltage rises above this programmed level.

The VINOVLO register contains the digital value that sets the input overvoltage lockout. OVLO has a range of 8.8V to 44V. When the input voltage on the V the MCP19114/5 is above this programmed level and the <OVLOEN> bit in the VINCON register is set, both PDRV and SDRV gate drivers are disabled. This bit is automatically cleared when the MCP19114/5 V voltage drops below this programmed level. Refer to

Figure 27-1.

Note: The UVLOIF and OVLOIF interrupt flag

bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register.

pin to

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0

UVLOEN UVLOOUT UVLOINTP UVLOINTN OVLOEN OVLOOUT OVLOINTP OVLOINTN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

x = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 UVLOEN: UVLO Comparator Module Logic Enable bit

1 = UVLO Comparator Module Logic enabled 0 = UVLO Comparator Module Logic disabled

bit 6 UVLOOUT: Undervoltage Lockout Status Output

1 = UVLO event has occurred 0 = No UVLO event has occurred

bit 5 UVLOINTP: UVLO Comparator Interrupt on Positive Going Edge Enable bit

1 = The UVLOIF interrupt flag will be set upon a positive going edge of the UVLO 0 = No UVLOIF interrupt flag will be set upon a positive going edge of the UVLO

bit 4 UVLOINTN: UVLO Comparator Interrupt on Negative Going Edge Enable bit

1 = The UVLOIF interrupt flag will be set upon a negative going edge of the UVLO 0 = No UVLOIF interrupt flag will be set upon a negative going edge of the UVLO

 2014 Microchip Technology Inc. DS20005281A-page 37

Page 38

MCP19114/5

bit 3 OVLOEN: OVLO Comparator Module Logic enable bit

1 = OVLO Comparator Module Logic enabled 0 = OVLO Comparator Module Logic disabled

bit 2 OVLOOUT: Overvoltage Lockout Status Output bit

1 = OVLO event has occurred 0 = No OVLO event has occurred

bit 1 OVLOINTP: OVLO Comparator Interrupt on Positive Going Edge Enable bit

1 = The OVLOIF interrupt flag will be set upon a positive going edge of the OVLO 0 = No OVLOIF interrupt flag will be set upon a positive going edge of the OVLO

bit 0 OVLOINTN: OVLO Comparator Interrupt on Negative Going Edge Enable bit

1 = The OVLOIF interrupt flag will be set upon a negative going edge of the OVLO 0 = No OVLOIF interrupt flag will be set upon a negative going edge of the OVLO

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 UVLO<5:0>: Undervoltage Lockout Configuration bits

UVLO(V) = 3.5472 * (1.0285

to 63

) where N = the decimal value written to the VINUVLO Register from 0

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— — OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OVLO<5:0>: Overvoltage Lockout Configuration bits

OVLO(V) = 7.4847 * (1.0286

to 63

) where N = the decimal value written to the VINOVLO Register from 0

DS20005281A-page 38  2014 Microchip Technology Inc.

Page 39

MCP19114/5

6.2 Output Overvoltage Protection

The MCP19114/5 feature output overvoltage protection. This feature also utilizes a comparator module similar to the standard PIC comparator module. This is used to prevent the power system from being damaged when the load is disconnected. The OVREFCON register contains the digital value that sets the analog DAC voltage at the inverting input of the comparator. By comparing the divided down power train output voltage connected to the non-inverting input (V voltage, the user will know when an overvoltage event has occurred and can automatically take action.

) of the comparator with the OVREF reference

The OVCON register contains the interrupt flag polarity and OV enable bits along with the output status bit just as VINCON does for the input voltage UVLO and OVLO. When <OVEN> bit in the OVCON register is set and an overvoltage occurs, the control logic will automatically set the secondary gate drive output (SDRV) high and set the primary gate drive output (PDRV) low.

Note: The OVIF interrupt flag bit is set when an

interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register.

U-0 U-0 U-0 U-0 R/W-0 R-0 R/W-0 R/W-0

— — — — OVEN OVOUT OVINTP OVINTN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’ bit 3 OVEN: OV Comparator output enable bit

1 = OV Comparator output is enabled 0 = OV Comparator output is Not enabled

bit 2 OVOUT: Output Overvoltage Status Output bit

1 = Output Overvoltage has occurred 0 = No Output Overvoltage has occurred

bit 1 OVINTP: OV Comparator Interrupt on Positive Going Edge Enable bit

1 = The OVIF interrupt flag will be set upon a positive going edge of the OV 0 = No OVIF interrupt flag will be set upon a positive going edge of the OV

bit 0 OVINTN: OV Comparator Interrupt on Negative Going Edge Enable bit

1 = The OVIF interrupt flag will be set upon a negative going edge of the OV 0 = No OVIF interrupt flag will be set upon a negative going edge of the OV

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

OOV7 OOV6 OOV5 OOV4 OOV3 OOV2 OOV1 OOV0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 OOV<7:0>: Output Overvoltage Detect Level Configuration bits

OV_REF(V)

 2014 Microchip Technology Inc. DS20005281A-page 39

=2*VBG* (OOV(dec)/255)

Page 40

MCP19114/5

//Assumes that calibration words ADCCAL and BUFF are read from //program memory into variables ADCC and BUOFFSET, respectively. extern volatile unsigned int ADRES @ 0x01C; #define OVREFTARGET (unsigned int) 0x0800 // OVREF Target = 2.0 V unsigned long tmp = (unsigned long)ADCC*(OVREFTARGET+BUOFFSET); // ADC Reference + Buffer Offset unsigned int target = (unsigned int)(tmp >> 15) - 3; // Subtract ADC typical offset error 3 unsigned int adc; OVREFCON = 0x00; // Clear OVREFCON ADCON0 = 0x09; // Enable and set channel to OVREF

do { // Adjust OVREFCON

OVREFCON++; NOP(); NOP();

adc = 0; for (unsigned char i = 4; i > 0; i--) {

ADCON0bits.GO_nDONE = 1; while(ADCON0bits.GO_nDONE);

adc += ADRES; } adc >>= 2;

} while ((adc < target) && (OVREFCON != 0xFF));

Note 1: In this example, the LSb weight of OVREFTARGET is set to 1/(2

) volt. Users can choose their own resolution depending on their accuracy requirement. The digital value of 2.0 V is determined as follows: TRUNC(2.0 x 2

) = 2048 (0x0800 hex).

The A/D converter Calibration Word 8 can be used to improve OVREF accuracy. An ADC measurement tar-

An example of OVREF-calibration firmware is as fol-

lows: get (target in Example 6-1) is obtained by adding the analog mux buffer offset (BUOFFSET) to the desired OVREF voltage (OVREFTARGET) and multiplying the result by the ADC gain (GADC). OVREF is adjusted until the ADC reading equals or exceeds the target.

EXAMPLE 6-1: EXAMPLE OVREF CORRECTION ROUTINE

DS20005281A-page 40  2014 Microchip Technology Inc.

Page 41

MCP19114/5

6.3 Desaturation Detection for Quasi-Resonant Operation

The MCP19114/5 have been designed with a built-in desaturation detection comparator module custom made for quasi-resonant topologies. This is especially useful for LED-type applications. Through the use of the MCP19114/5, both synchronous and asynchronous quasi-resonant topologies can be implemented. The DESAT comparator module has the same features as the UVLO/OVLO and OV comparator modules, except that it includes some additional programmable parameters.

The DESATCON register holds the setup control bits for this module. Common control bits are the polarity edge trigger for the interrupt flag <CDSINTP><CDSINTN>, comparator output polarity control <CDSPOL>, output enable <CDSOE> and output status <CDSOUT> bit. As with the other comparator modules, the CDSIF is independent of the CDSOE enable bit. On the front end connected to the DESAT comparator non-inverting input, there is a two-channel MUX that connects either to the DESAT pin or to the fixed internally generated band gap voltage. Additionally, the input offset voltage of the DESAT comparator is factory-trimmed to within ±1 mV typically. These factory-trimmed values are stored in the CALWD2 register at address 2081h. Firmware must read these values into the DSTCAL register (196h). If more offset is desired, the user can adjust the values written to the DSTCAL per their implementation.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CDSMUX CDSWDE Reserved CDSPOL CDSOE CDSOUT CDSINTP CDSINTN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 CDSMUX: DESAT Comparator Module Multiplexer channel selection bit

1 = BG Selected 0 = DESAT

bit 6 CDSWDE: DESAT Comparator Watch Dog Enable bit

1 = Watch Dog signal enables PWM Reset 0 = Watch Dog signal does Not allow PWM reset

bit 5 RESERVED bit 4 CDSPOL: DESAT Comparator Polarity Select bit

1 = DESAT Comparator output is inverted 0 = DESAT Comparator output is Not inverted

bit 3 CDSOE: DESAT Comparator output enable bit

1 = DESAT Comparator output PWM is enabled 0 = DESAT Comparator output PWM is Not enabled

bit 2 CDSOUT: DESAT Comparator Output Status bit

If CDSPOL = 1 (inverted polarity)

1 = CDSVP < CDSVN (DESAT Detected) 0 = CDSVP > CDSVN (DESAT Not Detected)

If CDSPOL = 0 (non-inverted polarity)

1 = CDSVP > CDSVN (DESAT Not Detected) 0 = CDSVP < CDSVN (DESAT Detected)

bit 1 CDSINTP: CDSIF Comparator Interrupt on Positive Going Edge Enable bit

1 = The CDSIF interrupt flag will be set upon a positive going edge 0 = No CDSIF interrupt flag will be set upon a positive going edge

bit 0 CDSINTN: CDSIF Comparator Interrupt on Negative Going Edge Enable bit

1 = The CDSIF interrupt flag will be set upon a negative going edge 0 = No CDSIF interrupt flag will be set upon a negative going edge

Selected (Default)

 2014 Microchip Technology Inc. DS20005281A-page 41

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MCP19114/5

6.4 Primary Input Current Offset Adjust

Primary input current offset adjust provides the ability to add offset to the primary input current signal, thus setting a peak primary current limit. This offset adjust is controlled using the four bits in the ICOACON register.

U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x

— — — — ICOAC3 ICOAC2 ICOAC1 ICOAC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ICOAC<3:0>: Input current offset adjustment Configuration bits

0000 = 0 mV 0001 = 50 mV 0010 = 100 mV 0011 = 150 mV 0100 = 200 mV 0101 = 250 mV 0110 = 300 mV 0111 = 350 mV 1000 = 400 mV 1001 = 450 mV 1010 = 500 mV 1011 = 550 mV 1100 = 600 mV 1101 = 650 mV 1110 = 700 mV 1111 = 750 mV

DS20005281A-page 42  2014 Microchip Technology Inc.

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MCP19114/5

6.5 Leading Edge Blanking

The adjustable Leading Edge Blanking (LEB) is used to blank primary current spikes resulting from primary switch turn-on. Implementing adjustable LEB allows the system to ignore turn-on noise to best suit the application without primary current sense distortion from RC filtering. There are four settings available for LEB, including zero. These settings are controlled via two bits in the ICLEBCON register.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x

— — — — — — ICLEBC1 ICLEBC0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 ICLEBC<1:0>: Input current Leading Edge Blanking Configuration bits

00 = 0 ns 01 = 50 ns 10 = 100 ns 11 = 200 ns

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MCP19114/5

6.6 Slope Compensation

A negative voltage slope is added to the output of the error amplifier. This is done to prevent subharmonic instability when:

1. the operating duty cycle is greater than 50%

2. wide changes in the duty cycle occur

The amount of negative slope added to the error amplifier output is controlled by slope compensation slew rate control bits.

The slope compensation is enabled by clearing the SLPBY bit in the SLPCRCON register.

U-0 R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SLPBY SLPS5 SLPS4 SLPS3 SLPS2 SLPS1 SLPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’ bit 6 SLPBY: Slope Compensation Bypass Control bit

1 = Slope compensation is Bypassed 0 = Slope compensation is not Bypassed

bit 5-0 SLPS<5:0>: Slope Compensation Slew Rate Control bits

SLPS (mV/µs) = 4.1505 mV/µs * e

0.739*(dec)

DS20005281A-page 44  2014 Microchip Technology Inc.

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MCP19114/5

PDT

SDT

PDRV

SDRV

6.7 MOSFET Driver Programmable Dead Time

FIGURE 6-1: MOSFET DRIVER DEAD

TIME

The turn-on dead time of both PDRV and SDRV low-side drive signals can be configured independently to allow different MOSFETs and circuit board layouts to be used to construct an optimized system (refer to

Figure 6-1).

Clearing the PDRVBY and SDRVBY bits in the PE1 register enables the PDRV and SDRV low-side dead timers respectively. The amount of dead time added is controlled in the DEADCON register.

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

PDRVDT3 PDRVDT2 PDRVDT1 PDRVDT0 SDRVDT3 SDRVDT2 SDRVDT1 SDRVDT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 PDRVDT<3:0>: PDRV Dead Time Configuration bits (t

0000 = 16 ns delay 0001 = 32 ns delay 0010 = 48 ns delay 0011 = 64 ns delay 0100 = 80 ns delay 0101 = 96 ns delay 0110 = 112 ns delay 0111 = 128 ns delay 1000 = 144 ns delay 1001 = 160 ns delay 1010 = 176 ns delay 1011 = 192 ns delay 1100 = 208 ns delay 1101 = 224 ns delay 1110 = 240 ns delay 1111 = 256 ns delay

bit 3-0 SDRVDT<3:0>: SDRV Dead Time Configuration bits (t

TD_1

TD_2

)

 2014 Microchip Technology Inc. DS20005281A-page 45

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MCP19114/5

//Assumes that calibration word A2CAL has been read into variable A2COMP

unsigned int VREF1_TEMP = VREFCON*A2COMP; // A2 Gain compensate for VREFCON VREF1_TEMP >>= 7; VREF1_TEMP &= 0x00FF; VREFCON = VREF1_TEMP;

6.8 Output Regulation Reference Voltage Configuration

The VREFCON register controls the error amplifier reference voltage. This reference is used to set the current or voltage regulation set point. VREFCON holds the digital value used by an 8-bit linear DAC setting the analog equivalent that gets summed with the pedestal voltage (VZC) at the non-inverting node of the error amplifier. VZC is equal to the band gap voltage (1.23V). The output of the current sense amplifier A2 is also raised on the pedestal voltage effectively canceling its effect on the input. The pedestal is implemented throughout the analog control loop to improve accuracy at low levels. The VREF DAC can be adjusted in 255 steps of 4.8 mV/step.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREF7 VREF6 VREF5 VREF4 VREF3 VREF2 VREF1 VREF0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 VREF<7:0>: Voltage Controlling Current Regulation Set point bits

VREF(V) = V

To ensure the best regulation accuracy while implementing the Current Sense Amplifier (A2), the initial gain error must be considered. An 8-bit factory-stored calibration value A2CAL<7:0> has been stored in CALWD10 at 208Bh. This value can be used to compensate for A2 gain error by adjusting the V command.

* (VREF(dec)/255)

REF

To get the final commanded value, the CALWD10 value gets multiplied by the original V using the V Rotating the 16 bit result right produces the final compensated command in the least significant byte. The most significant byte is unused.

An example of the firmware is as follows:

expression resulting in a 16-bit word.

REF

EXAMPLE 6-2: EX AMP LE A2 GAIN CORRECTION

decimal command

REF

DS20005281A-page 46  2014 Microchip Technology Inc.

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MCP19114/5

// Assumes that the calibration word ADCCAL has been read into variable ADCC

extern volatile unsigned int ADRES @ 0x01C; #define VREF2TARGET (unsigned int) 0x02CC // VREF2 Target = 0.7 V unsigned long tmp = (unsigned long)ADCC*VREF2TARGET; // ADC Reference unsigned int target = (unsigned int)(tmp >> 15) - 3; // Subtract ADC typical offset error 3 unsigned int adc;

VREF2CON = 0x00; // Clear VREF2CON ADCON = 0x71; // Enable ADC and set channel to GPB1/VREF2

do { // Adjust VREF2CON

VREF2CON++; NOP(); NOP(); adc = 0; for (unsigned char i = 4; i > 0; i--) {

ADCON0bits.GO_nDONE = 1; while(ADCON0bits.GO_nDONE);

adc += ADRES; } adc >>= 2;

} while ((adc < target) && (VREF2CON != 0xFF));

Note 1: In this example, the LSb weight of VREF2TARGET is set to 1/(2

) Volt. Users can choose their own resolution depending on

their accuracy requirement. The digital value of 0.7V is determined as follows: TRUNC(0.7 x 2

) = 716 (0x02CC hex).

(1)

6.9 V

Voltage Reference

REF2

The VREF2CON register controls a second reference DAC that can be used externally. For example, it can be sent off chip and used to set the current regulation set point for a MCP1631 Pulse Width Modulator. The MCP19114/5 must be configured in Master Mode with

connect V is not accessible. VREFCON2 holds the digital value used to set the VREF2 DAC. Since this reference is intended to go off chip, there is no pedestal offset associated with it and it is referenced to GND. It is an 8-bit linear DAC and has a range from 0V to 1.23V (BG) equating to 255 steps at 4.8 mV/step.

to GPB1. In Stand-alone mode, V

REF2

bits MSC<0:1> = 01 in the MODECON register to

VOLTAGE SET POINT REGISTER

REF2

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

VREF27 VREF26 VREF25 VREF24 VREF23 VREF22 VREF21 VREF20

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-0 VR EF2<7:0>: Voltage Controlling Current Regulation Set point bits

The A/D converter Calibration Word 8 can be used to improve V

accuracy. An ADC measurement target

REF2

= VBG* (VREF2(dec)/255)

REF2(V)

An example of V

-correction firmware is as follows:

REF2

(target in Example 6-3) is obtained by multiplying the desired V_{REF2} voltage (VREF2TARGET) by the ADC gain (ADCC). V

is adjusted until the ADC

REF2

reading equals or exceeds the target.

EXAMPLE 6-3: VREF2 CORRECTION ROUTINE

 2014 Microchip Technology Inc. DS20005281A-page 47

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MCP19114/5

6.10 Analog Peripheral Control

The MCP19114/5 have various analog peripherals. These peripherals can be configured to allow customizable operation. Refer to Register 6-13 for more information.

6.10.1 MOSFET GATE DRIVER ENABLES

The MCP19114/5 can enable and/or disable the MOSFET gate driver outputs for the primary drive (PDRV) and the secondary drive (SDRV) independently. Setting the <PDRVEN> bit in the PE1 register enables the primary drive. Setting the <SDRVEN> bit in the PE1 register enables the secondary drive. Refer to Register 6-13 for details.

6.10.2 MOSFET DRIVER DEAD TIME

As described in Section 6.7 “MOSFET Driver

Programmable Dead T ime”, the MOSFET drive dead

time can be adjusted. The dead time can be set independently for each driver from 16 ns to 256 ns in increments of 16 ns using the DEADCON register. Dead time can also be disabled for each driver independently by setting the bypass bits <PDRVBY> and <SDRVBY> in the PE1 register.

6.10.3 SECONDARY CURRENT POSITIVE SENSE PULL-UP

A high-impedance pull-up on the ISP pin can be configured by setting the <ISPUEN> bit in the PE1 register. When set, the I V

. Refer to Register 6-13 for details.

pin is internally pulled-up to

6.10.4 PWM STEERING

The MCP19114/5 have additional control circuitry to allow open-loop repositioning of the output. The PWMSTR_PEN bit enables a primary-only PWM signal of fixed frequency and duty cycle to reposition the output voltage up. The PWMSTR_SEN bit enables a secondary-only PWM signal of fixed frequency and duty cycle to reposition the output voltage down. When repositioning output voltage down, the output overvoltage protection must be active along with PWMSTR_SEN for the PWM to pulse the SDRV. Frequency and duty cycle are controlled through TMR2 registers PR2 and TMR1L. PWMSTPR_PEN and PWMSTR_SEN should never be active at the same time, therefore the PWMSTPR_PEN is the dominant bit. For quasi-resonant operation during open-loop repositioning, the DESAT comparator output should be disabled with the <CDSOE> bit in the DEADCON register.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

PDRVEN SDRVEN PDRVBY SDRVBY

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 PDRVEN: PDRV Gate Drive Enable bit

1 = ENABLED 0 = DISABLED

bit 6 SDRVEN: SDRV Gate Drive Enable bit

1 = ENABLED 0 = DISABLED

bit 5 PDRVBY: PDRV Dead Time Bypass bit

1 = PDRV dead time is bypassed 0 = PDRV dead time is not bypassed

bit 4 SDRVBY: SDRV Dead Time Bypass bit

1 = SDRV dead time is bypassed 0 = SDRV dead time is not bypassed.

bit 3 Unimplemented: Read as ‘0’ bit 2 ISPUEN: I

1 = I

0 = I

Weak Pull-Up Enable bit

weak pull-up is enabled weak pull-up is disabled

— ISPUEN PWMSTR_PEN PWMSTR_SEN

DS20005281A-page 48  2014 Microchip Technology Inc.

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MCP19114/5

bit 1 PWMSTR_PEN: PDRV PWM Steering bit

1 = Enables open-loop PWM control to the PDRV 0 = Disables open-loop PWM control to the PDRV

bit 0 PWMSTR_SEN: SDRV PWM Steering bit

1 = Enables open-loop PWM control to the SDRV 0 = Disables open-loop PWM control to the SDRV

bit

6.11 Analog Blocks Enable Control

Various analog circuit blocks can be enabled or disabled, as shown in the ABECON register. The ABECON register also contains bits controlling analog and digital test signals. These signals can be configured to GPA0. Setting the <DIGOEN> bit enables the digital test signals to be connected to GPA0. <DSEL2:0> selects the digital channels. Setting <ANAOEN> enables the analog test signals to be connected to GPA0. If <ANAOEN> and <DIGOEN> both get set, the DIGOEN bit takes priority. When ANAOEN is not set, the analog test signals are connected to the internal ADC. The analog test channel selections are controlled through the ADCON0 register.

6.11.1 MOSFET DRIVER UNDERVOLTAGE LOCKOUT SELECTION

The MOSFET gate drivers have internal undervoltage protection that is controlled by the <DRUVSEL> bit in the ABECON register. Since the gate drive supply is provided externally through the V capable of driving logic level FETs or higher 10V (13.5V maximum) FETs. <DRUVSEL> defaults to clear, therefore selecting a gate drive UVLO of 2.7V. Setting <DRUVSEL> selects the higher 5.4V gate drive UVLO.

Refer to Section 4.2 “Electrical Characteristics” for

additional electrical specifications.

pin, the drivers are

6.11.2 ERROR AMPLIFIER DISABLE

The error amplifier can be disabled such that its output is parked to a known state. The <EADIS> bit defaults to zero and the error amp is enabled during normal operation. In case the user wants to disable the error amplifier, setting the EADIS bit parks the error amplifier output to just below the low clamp voltage. Under normal operation, the error amplifier output runs between 2 * BG (upper clamp value) and 1 * BG –

150 mV (lower clamp value). The analog feedback circuitry utilizes an offset pedestal (1 * BG) to improve accuracy at low levels.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

DIGOEN DSEL2 DSEL1 DSEL0 DRUVSEL

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DIGOEN: DIG Test MUX to GPA0 connection control

1 = DIG Test MUX output is connected to external pin GPA0 0 = DIG Test MUX output is not connected to external pin GPA0

 2014 Microchip Technology Inc. DS20005281A-page 49

— EADIS ANAOEN

Page 50

MCP19114/5

bit 6-4 DSEL<2:0>

000 = QRS (Output of DESAT comparator) 001 = PWM_L (PWM output after monostable) 010 = PWM (Oscillator output from the micro-controller) 011 = TMR2EQ (When TMR2 equals PR2) 100 = OV (Overvoltage comparator output) 101 = SWFRQ (Switching Frequency Output) 110 = SDRV_ON_ONESHOT (200 nS one-shot signal to reset WDM logic) 111 = Unimplemented

bit 3 DRUVSEL: Selects gate drive undervoltage lockout level

1 = Gate Drive UVLO set to 5.4V 0 = Gate Drive UVLO set to 2.7V

bit 2 Unimplemented: Read as ‘0’ bit 1 EADIS: Error Amplifier Disable bit

1 = Disables the error amplifier (Output parked low, clamped to 1 * BG) 0 = Enables the error amplifier (Normal operation)

bit 0 ANAOEN: Analog MUX Output Control bit

1 = Analog MUX output is connected to external pin GPA0 0 = Analog MUX output is not connected to external pin GPA0

DS20005281A-page 50  2014 Microchip Technology Inc.

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MCP19114/5

6.12 Mode and RFB MUX Control

The MODECON register controls the Master/Slave configuration and the internal resistor feedback MUX for the current sense amplifier while in quasi-resonant mode.

In Master/Slave mode, it allows the V Master MCP19115 device to be buffered and connected to a GPIO pin. This output signal can be connected to a Slave PWM driver (MCP1631) at the

input to regulate current via the Slave PWM

REF

Controller. In Stand-alone mode, the V buffer is not connected to a separate GPIO Pin.

The RFB MUX selects the output of A2 current sense amplifier to be connected to the internal 5 k feedback resistor (quasi-resonant) or to the I

SOUT

R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0

MSC1 MSC0 RFB

bit 7 bit 0

REF2

pin.

signal of the

unity gain

— — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-6 MSC<1:0>: Master/Slave Configuration bits

00 = Device set as stand-alone unit 01 = Device set as MASTER 10 = Device set as SLAVE 11 = RESERVED

bit 5 RFB<5>: Current Sense Amplifier (A2) output resistor feedback MUX Configuration bit

FB_INT

SOUT

5 k

0 = R 1 = I

bit 4-0 Unimplemented: Read as ‘0’

 2014 Microchip Technology Inc. DS20005281A-page 51

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MCP19114/5

NOTES:

DS20005281A-page 52  2014 Microchip Technology Inc.

Page 53

MCP19114/5

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

6.1

-40 -25 -10 5 20 35 50 65 80 95 110 125

VIN= 32V

VIN= 6V

Non-Switching

-40 -25 -10 5 20 35 50 65 80 95 110 125

Sleep Current (µA)

VIN= 32V

VIN= 25V

VIN= 12V

VIN= 6V

5.04

5.05

5.06

5.07

5.08

5.09

5.10

6 8 10 12 14 16 18 20 22 24 26 28 30 32

-40°C

+125°C

+25°C

IDD= 1 mA

5.03

5.04

5.05

5.06

5.07

5.08

5.09

5.10

024681012141618202224262830

Voltage (V)

-40°C

+25°C

+125°C

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

024681012141618202224262830

-40°C

+25°C

+125°C

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-40 -25 -10 5 20 35 50 65 80 95 110 125

7.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

Note: Unless otherwise indicated, V

VIN= 12V

Quiescent Current (mA)

Temperature (°C)

=12V, FSW= 150 kHz, TA=+25°C.

VIN= 25V

FIGURE 7-1: IQ vs. Temperature.

Current (mA)

FIGURE 7-4: Load Regulation.

Dropout Voltage (V)

FIGURE 7-2: IQ vs. Temperature in Sleep Mode.

(V)

FIGURE 7-3: Line Regulation.

 2014 Microchip Technology Inc. DS20005281A-page 53

Temperature (°C)

VIN(V)

FIGURE 7-5: V Output Current (mA).

0.45

Dropout Voltage (V)

FIGURE 7-6: V Temperature.

Current (mA)

Dropout Voltage vs.

Temperature (°C)

Dropout Voltage vs.

IDD= 20 mA

Page 54

MCP19114/5

100

150

200

250

300

02468101214

-40°C

+25°C

+125°C

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

DSon

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

DSon

()

PDRV-SINK

SDRV-SINK

VDR= 10V

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

-40 -25 -10 5 20 35 50 65 80 95 110

125

DSon

( )

PDRV-SINK

SDRV-SINK

VDR= 5V

7.92

7.94

7.96

7.98

8.00

8.02

8.04

8.06

8.08

-40 -25 -10 5 20 35 50 65 80 95 110 125

Oscillator Frequency (MHz)

Note: Unless otherwise indicated, V

PDRV/SDRV Dead Time (ns)

Code (d)

=12V, FSW= 150 kHz, TA=+25°C.

FIGURE 7-7: Output Driver Dead Ti me vs. Code and Temperature.

VDR= 10V

()

PDRV-SOURCE

9.5

9.0

8.5

8.0

7.5

()

7.0

DSon

SDRV-SOURCE

6.5

6.0

5.5

5.0

4.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

PDRV-SOURCE

Temperature (°C)

VDR= 5V

FIGURE 7-10: Sourcing Output Driver R

vs. Temperature.

DSon

SDRV-SOURCE

FIGURE 7-8: Sour ci ng Ou tpu t Driv er R

vs. Temperature.

DSon

Temperature (°C)

FIGURE 7-9: Sinking Output Driver R vs. Temperature.

DS20005281A-page 54  2014 Microchip Technology Inc.

Temperature (°C)

DSon

Temperature (°C)

FIGURE 7-11: Sinking Output Driver R

DSon

vs. Temperature.

Temperature (°C)

FIGURE 7-12: Oscillator Frequency vs. Temperature.

Page 55

0.95

0.96

0.97

0.98

0.99

1.01

1.02

1.03

1.04

-40 -25 -10 5 20 35 50 65 80 95 110

125

Normalized Output Demand

Output Demand = 0.984V

Minimum

Maximum

Typical

Temperature (°C)

FIGURE 7-13: Normalized Output Demand vs. Temperature.

MCP19114/5

 2014 Microchip Technology Inc. DS20005281A-page 55

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MCP19114/5

NOTES:

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MCP19114/5

8.0 SYSTEM BENCH TESTING

Control of the signals present at the output of the unity gain analog buffer is found in the ADCON0 register.

To allow for easier system design and bench testing, the MCP19114/5 feature a multiplexer used to output various internal analog signals. These signals can be measured on the GPA0 pin through a unity gain buffer. The configuration control of the GPA0 pin is found in the ABECON register.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n = Value at POR

‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits

00000 = V 00001 = V 00010 = OV_REF (reference for overvoltage comparator) 00011 = V 00100 = V 00101 = EA_SC (error amplifier after slope compensation output) 00110 = A2 (secondary current sense amplifier output at R 00111 = PEDESTAL (Pedestal Voltage) 01000 =RESERVED 01001 =RESERVED 01010 = IP_ADJ (IP after Pedestal and Offset Adjust (at PWM Comparator)) 01011 = IP_OFF_REF (IP Offset Reference) 01100 = V 01101 = TEMP_SNS (analog voltage representing internal temperature) 01110 = DLL_VCON (Delay Locked Loop Voltage Reference - control voltage for dead time) 01111 = SLPCMP_REF (slope compensation reference) 10000 = Unimplemented 10001 = Unimplemented 10010 = Unimplemented 10011 = Unimplemented 10100 = Unimplemented 10101 = Unimplemented 10110 = Unimplemented 10111 = Unimplemented 11000 = GPA0/AN0 (i.e. ADDR1) 11001 = GPA1/AN1 (i.e. ADDR0) 11010 = GPA2/AN2 (i.e. Temperature Sensor Input) 11011 = GPA3/AN3 (i.e. BIN) 11100 = GPB1/AN4 11101 = GPB4/AN5 (MCP19115 Only) 11110 = GPB5/AN6 (MCP19115 Only) 11111 = GPB6/AN7 (MCP19115 Only)

bit 1 GO/DONE

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

0 = A/D conversion completed/not in progress

bit 0 ADON: A/D Conversion Status bit

1 = A/D converter module is operating 0 = A/D converter is shut off and consumes no operating current

/n analog voltage measurement (VIN/15.5328)

+ VZC (DAC reference voltage + VZC pedestal setting current regulation level)

REF

(band gap reference)

BGR

(voltage proportional to V

/n (VDR/n analog driver voltage measurement = 0.229V/V * VDR)

: A/D Conversion Status bit

This bit is automatically cleared by hardware when the A/D conversion has completed.

OUT

)

connection)

FB_INT

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MCP19114/5

NOTES:

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Page 59

9.0 DEVICE CALIBRATION

Read-only memory locations 2080h through 208Fh

contain factory calibration data. Refer to Section 1 7.0

“Flash Program Memory Control” for information on

how to read from these memory locations.

9.1 Calibration Word 1

The DCSRFB<6:0> bits set the offset calibration for the current sense differential amplifier (A2) when configured using the internal feedback resistor. A calibration range of ±30 mV is provided with 20h and 00h being midscale (no offset). The MSB is polarity only. Firmware must read these values and write them into the DCSCAL register to implement offset calibration.

U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —

bit 13 bit 8

MCP19114/5

U-0

— DCSRFB6 DCSRFB5 DCSRFB4 DCSRFB3 DCSRFB2 DCSRFB1 DCSRFB0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-7 Unused: Read as ‘0’ bit 6-0 DCSRFB<6:0>: Input Differential Current Sense Calibration bits when configured using internal

R/P-1

feedback resistor

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

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MCP19114/5

9.2 Calibration Word 2

Calibration Word 2 is at memory location 2081h. It contains the calibration bits for the desaturation comparator current measurement input offset. Firmware must read these values and write them into the DSTCAL register to implement the factory offset calibration. The factory offset calibration will minimize offset voltage. The desaturation comparator is one of the few examples where the user may want to implement their own offset voltage values. Writing user defined values to the DSTCAL register provides this flexibility. This register also contains the trim bits needed to trim the internal 5k feedback resistor to within 2% using the <RFBT5:0> bits. Firmware must read these values and write them into the RFBTCAL register to implement the factory-trimmed feedback resistor value.

U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— DST4 DST3 DST2 DST1 DST0

bit 13 bit 8

U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— — RFBT5 RFBT4 RFBT3 RFBT2 RFBT1 RFBT0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13 Unused: Read as ‘0’ bit 12-8 DST<4:0>: Desaturation Comparator Current Measure Offset calibration bits bit 7-6 Unused: Read as ‘0’ bit 5-0 RFBT<5:0>: Internal Feedback Resistor Trim bits

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MCP19114/5

9.3 Calibration Word 3

The VRO<5:0> bits at memory location 2082h calibrate the offset of the buffer amplifier of the output voltage regulation reference set point (V read these values and write them to the VROCAL register for proper calibration.

The BGR<3:0> bits at memory location 2082h calibrate the band gap reference. Firmware must read these values and write them to the BGRCAL register for proper calibration.

U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1

— — — — BGR3 BGR2 BGR1 BGR0

bit 7 bit 0

). Firmware must

REF

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

VRO5 VRO4 VRO3 VRO2 VRO1 VRO0

bit 13 bit 8

Legend:

R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-8 VRO<5:0>: Reference voltage (V bit 7-4 Unused: Read as ‘0’ bit 3-0 BGR<3:0>: Band Gap Reference calibration bits

) offset calibration bits

REF

9.4 Calibration Word 4

The TTA<3:0> bits at memory location 2083h contain the calibration bits for the factory-set overtemperature threshold. Firmware must read these values and write them into the TTACAL register for proper calibration.

U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —

bit 13 bit 8

U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1

— — — — T TA3 TTA2 TTA1 TTA0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-4 Unused: Read as ‘0’ bit 3-0 TTACAL<3:0>: Overtemperature threshold calibration bits

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MCP19114/5

9.5 Calibration Word 5

The TANA<9:0> bits at memory location 2084h contain the ADC reading from the internal temperature sensor when the silicon temperature is at 30°C. The temperature coefficient of the internal temperature sensor is 16 mV/°C.

U-0 U-0 U-0 U-0 R/P-1 R/P-1

— — — — TANA9 TANA8

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

TANA7 TANA6 TANA5 TANA4 TANA3 TANA2 TANA1 TANA0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-8 Unused: Read as ‘0’ bit 7-0 TANA<9:0>: ADC reading of internal silicon temperature at 30°C calibration bits

9.6 Calibration Word 6

The FCAL<6:0> bits at memory location 2085h set the internal oscillator calibration. Firmware must read these values and write them to the OSCCAL register for proper calibration.

U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —

bit 13 bit 8

U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

— FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-7 Unused: Read as ‘0’ bit 6-0 FCAL<6:0>: Internal oscillator calibration bits

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Page 63

9.7 Calibration Word 7

The DCS<6:0> bits at memory location 2086h store the factory-set offset calibration for the current sense differential amplifier (A2) when configured using I A configuration range of +/-30 mV is provided with 20h and 00h being midscale (no offset). The MSB is polarity only. Firmware must read this value into the DCSCAL register to implement offset calibration. If using the internal feedback resistor, refer to Register 9-1.

U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —

bit 13 bit 8

SOUT

MCP19114/5

U-0

— DCS6 DCS5 DCS4 DCS3 DCS2 DCS1 DCS0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-7 Unimplemented: Read as ‘0’ bit 6-0 DCS<6:0>: Differential Current Sense Amplifier Calibration bits when used with I

R/P-1

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

SOUT

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MCP19114/5

9.8 Calibration Word 8

The ADCCAL<13:0> bits at memory location 2089h contain the calibration bits for the A/D converter. Calibration Word 8 (ADCCAL <13:0>) contains the factory measurement of the full scale ADC Reference. The value represents the number of A/D converter counts per volt. ADCC<4:0> bits represent the fraction of an A/D converter count, which can provide additional precision when oversampling the ADC for enhanced resolution. This calibration word can be used to calibrate signals read by the Analog-to-Digital Converter.

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

ADCC13 ADCC12 ADCC11 ADCC10 ADCC9 ADCC8

bit 13 bit 8

U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

ADCC7 ADCC6 ADCC5 ADCC4 ADCC3 ADCC2 ADCC1 ADCC0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-5 ADCC<13:5>: Whole number of A/D converter count

111111111 = 511

•

• 000000000 = 0

bit 4-0 ADCC<4:0>: Fraction number of A/D converter count

11111 = 0.96875

•

00001 = 0.03125 00000 = 0.00000

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MCP19114/5

9.9 Calibration Word 9

Calibration Word 9 is at memory location 208Ah. The value stored at this memory location represents the offset voltage (in units of mV) of the analog test buffer. This is an 8-bit, 2's complement word that can be used to compensate any signal sent through the Analog test multiplexer. See section 8.0 for test signal details.

U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

BUFF7 BUFF6 BUFF5 BUFF4 BUFF3 BUFF2 BUFF1 BUFF0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-8 Unimplemented: Read as ‘0’ bit 7-0 BUFF<7:0>: Analog Buffer Offset calibration bits

11111111 = Mid scale (-1 mV)

•

10000000 = Largest negative offset (-128 mV) 01111111 = Largest positive offset (127 mV)

•

• 00000000 = Mid scale (0 mV)

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MCP19114/5

9.10 Calibration Word 10

The A2CAL<7:0> bits at memory location 208Bh contain the calibration bits for Current Sense Amplifier (A2) Gain Error. For best regulation accuracy using this amplifier, firmware can read this value and use it to

adjust the VREF command. Section 6.8 “Output

Regulation Reference Voltage Configuration” for

details.

U-0 U-0 U-0 U-0 U-0 U-0

— — — — — —

bit 13 bit 8

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

A2CAL7 A2CAL6 A2CAL5 A2CAL4 A2CAL3 A2CAL2 A2CAL1 A2CAL0

bit 7 bit 0

Legend:

R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 13-8 Unimplemented: Read as ‘0’ bit 7-0 A2CAL<7:0>: Current Sense Amplifier (A2) Gain Error Calibration bits

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MCP19114/5

PC<12:0>

0000h

0004h

0005h

0FFFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-Chip Program

Memory

CALL, RETURN RETFIE, RETLW

1000h

2000h

2005h

2006h

2007h

200Ah

207Fh

20FFh

2003h

2004h

Note 1: Not code protected.

Shadows 000-FFFh

2008h

2080h

200Bh

208Fh

2090h

2100h

3FFFh

User IDs

(1)

ICD Instruction

(1)

Manufacturing Codes

(1)

Device ID (hardcoded)

(1)

Config Word

(1)

Reserved

Reserved for

Manufacturing & Test

(1)

Calibration Words

(1)

Unimplemented

Shadows 2000-20FFh

10.0 MEMORY ORGANIZATION

There are two types of memory in the MCP19114/5:

• Program Memory

• Data Memory

10.1 Program Memory Organization

The MCP19114/5 have a 13-bit program counter capable of addressing an 8000 x 14 program memory space. Only the first 4000 x 14 (0000h-0FFFh) is physically implemented. Addressing a location above this boundary will cause a wrap-around within the first 4000 x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (refer to Figure 10-1). The width of the program memory bus (instruction word) is 14 bits. Since all instructions are a single word, the MCP19114/5 have space for 4000 instructions.

FIGURE 10-1: PROGRAM MEMORY MAP

AND STACK FOR MCP19114

- Special Function Registers (SFRs)

- General-Purpose RAM

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MCP19114/5

constants

BRW ;Add Index in W to

;program counter to

;select data RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3

my_function

;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W

10.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set a Files Select Register (FSR) to point to the program memory.

10.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access to the tables of constants. The recommended way to create such tables is shown in Example 10-1.

EXAMPLE 10-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available, so the older table-read method must be used.

10.2 Data Memory Organization

The data memory (refer to Figure 10-1) is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0, A0h-EFh in Bank 1 and 120h-16Fh in Bank 2 are General Purpose Registers, implemented as static RAM. All other RAM is unimplemented and returns ‘0’ when read. The RP<1:0> bits in the STATUS register are the bank select bits.

EXAMPLE 10-2: BANK SE LECT

RP1 RP0

00 -> Bank 0 is selected 01 -> Bank 1 is selected 10 -> Bank 2 is selected 11 -> Bank 3 is selected

To move values from one register to another register, the value must pass through the W register. This means that for all register-to-register moves, two instruction cycles are required.

The entire data memory can be accessed either directly or indirectly. Direct addressing may require the use of the RP<1:0> bits. Indirect addressing requires the use of the FSR. Indirect addressing uses the Indirect Register Pointer (IRP) bit in the STATUS register for access to the Bank0/Bank1 or the Bank2/Bank3 areas of data memory.

10.2.1 GENERAL PURPOSE REGISTER FILE

The register file is organized as 64 x 8 in the MCP19114/5. Each register is accessed, either directly

or indirectly, through the FSR (refer to Section 10.5

“Indirect Addressing, INDF and FSR Registers”).

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MCP19114/5

10.2.2 CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers can be addressed from any bank. These registers are listed below in Tab le 1 0- 1. For detailed information, refer to

Table 10-2.

TABLE 10-1: CORE REGISTERS

Addresses BANKx

x00h, x80h, x100h, or x180h x02h, x82h, x102h, or x182h x03h, x83h, x103h, or x183h x04h, x84h, x104h, or x184h x0Ah, x8Ah, x10Ah, or x18Ah x0Bh, x8Bh, x10Bh, or x18Bh

INDF

PCL

STATUS

FSR

PCLATH

INTCON

10.2.2.1 STATUS Register

The STATUS register contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (RAM)

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits.

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in subtraction.

and PD bits are not

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR x = Bit is unknown ‘0’ = Bit is cleared

‘1’ = Bit is set

bit 7 IRP: Register Bank Select bit (used for Indirect addressing)

1 = Bank 2 & 3 (100h - 1FFh) 0 = Bank 0 & 1 (00h - FFh)

bit 6-5 RP<1:0>: Register Bank Select bits (used for Direct addressing)

00 =Bank 0 (00h - 7Fh) 01 =Bank 1 (80h - FFh) 10 =Bank 2 (100h - 17Fh) 11 =Bank 3 (180h - 1FFh)

bit 4 TO

Note 1: For Borrow

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit in the source register.

: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

PD ZDC

(1)

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MCP19114/5

bit 3 PD

bit 2 Z: Zero bit

bit 1 DC: Digit Carry/Digit Borrow bit

bit 0 C: Carry/Borrow bit

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit in the source register.

: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

(1)

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4

(1)

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

low-order bit of the result

(ADDWF, ADDLW, SUBLW, SUBWF instructions)

(1)

10.2.3 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (refer to Figure 10-2). These registers are static RAM.

The special registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the microcontroller core are described in this section. Those related to the operation of the peripheral features are described in the associated section for that peripheral feature.

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10.3 DATA MEMORY

Indirect addr.

(1)

00h Indirect addr.

(1)

80h Indirect addr.

(1)

100h Indirect addr.

(1)

180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h

STATUS 03h STATUS 83h STATUS 103h STATUS 183h

FSR 04h FSR 84h FSR 104h FSR 184h PORTGPA 05h TRISGPA 85h WPUGPA 105h IOCA 185h PORTGPB 06h TRISGPB 86h WPUGPB 106h IOCB 186h

PIR1 07h PIE1 87h PE1 107h ANSELA 187h PIR2 08h PIE2 88h MODECON 108h ANSELB 188h

PCON 09h

89h ABECON 109h 189h PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh

TMR1L 0Ch

8Ch 10Ch PORTICD

(2)

18Ch

TMR1H 0Dh 8Dh 10Dh TRISICD

(2)

18Dh

T1CON 0Eh 8Eh 10Eh ICKBUG

(2)

18Eh

TMR2 0Fh

8Fh 10Fh BIGBUG

(2)

18Fh

T2CON 10h VINUVLO 90h SSPADD 110h PMCON1 190h

PR2 11h VINOVLO 91h SSPBUF 111h PMCON2 191h

12h VINCON 92h SSPCON1 112h PMADRL 192h

PWMPHL 13h CC1RL 93h SSPCON2 113h PMADRH 193h

PWMPHH 14h CC1RH 94h SSPCON3 114h PMDATL 194h

PWMRL 15h CC2RL 95h SSPMSK1 115h

PMDATH 195h

PWMRH 16h CC2RH 96h SSPSTAT 116h DSTCAL 196h

17h CCDCON 97h SSPADD2 117h RFBTCAL 197h 18h DESATCON 98h SSPMSK2 118h OSCCAL 198h

VREFCON 19h OVCON 99h 119h DCSCAL 199h

VREF2CON 1Ah OVREFCON 9Ah 11Ah TTACAL 19Ah

OSCTUNE 1Bh DEADCON 9Bh

11Bh BGRCAL 19Bh

ADRESL 1Ch SLPCRCON 9Ch 11Ch VROCAL 19Ch ADRESH 1Dh ICOACON 9Dh 11 Dh 19Dh ADCON0 1Eh ICLEBCON 9Eh

11Eh 19Eh

ADCON1 1Fh 9Fh 11F h Reserved 19Fh

General Purpose Register

96 Bytes

20h General

Purpose Register 80 Bytes

A0h General

Purpose Register

80 bytes

120h

1A0h

EFh 16F

1EF

7Fh

Accesses

Bank 0

F0h

FFh

Accesses

Bank 0

170h

17Fh

Accesses

Bank 0

1F0h

1FFh

Bank 0 Bank 1 Bank2 Bank3

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2: Only accessible when DBGEN

= 0 and ICKBUG<INBUG> = 1.

File

Address

File

Address

File

Address

File

Address

FIGURE 10-2: MCP19114/5 DATA MEMORY MAP

MCP19114/5

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MCP19114/5

TABLE 10-2: MCP19114/5 SPECIAL REGISTERS SUMMARY BANK 0

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000

03h STATUS IRP RP1 RP0 TO 04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTGPA GPA7 GPA6 GPA5

06h PORTGPB GPB7 GPB6 GPB5 GPB4

07h PIR1

08h PIR2 CDSIF

09h PCON

0Ah PCLATH

0Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 0Ch TMR1L Holding register for the Least Significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Dh TMR1H Holding register for the Most Significant byte of the 16-bit TMR1 xxxx xxxx

0Eh T1CON 0Fh TMR2 Timer2 Module Register 0000 0000 uuuu uuuu

10h T2CON

11h PR2 Timer2 Module Period Register 1111 1111 1111 1111 12h — Unimplemented — — 13h PWMPHL SLAVE Phase Shift Register xxxx xxxx uuuu uuuu 14h PWMPHH SLAVE Phase Shift Register xxxx xxxx uuuu uuuu 15h PWMRL PWM Register Low Byte xxxx xxxx uuuu uuuu 16h PWMRH PWM Register High Byte xxxx xxxx uuuu uuuu 17h — Unimplemented — — 18h — Unimplemented — — 19h VREFCON VREF7 VREF6 VREF5 VREF4 VREF3 VREF2 VREF1 VREF0 0000 0000 0000 0000

1Ah VREF2CON VREF27 VREF26 VREF25 VREF24 VREF23 VREF22 VREF21 VREF20

1Bh OSCTUNE 1Ch ADRESL Least significant 8 bits of the A/D result xxxx xxxx uuuu uuuu 1Dh ADRESH Most significant 2 bits of the A/D result 0000 00xx 0000 00uu

1Eh ADCON0

1Fh ADCON1

— ADIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF -000 0000 -000 0000

— — OTIF OVIF DRUVIF OVLOIF UVLOIF 0--0 0000 0--0 0000

— — — — — —PORBOR ---- --qq ---- --uu — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

— — T1CKPS1 T1CKPS0 — — TMR1CS TMR1ON --00 --00 --uu --uu

— — — — — TMR2ON T2CKPS1 T2CKPS0 ---- -000 ---- -000

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---0 0000

— CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000 -000 0000 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----

— G PA3 GPA2 GPA 1 GPA 0 xxx- xxxx uuu- uuuu

PD ZDCC0001 1xxx 000q quuu

— — GPB1 GPB0 xxxx --xx uuuu --uu

(2)

0000 000x 0000 000u

uuuu uuuu

0000 0000 0000 0000

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists.

(1)

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TABLE 10-3: MCP19114/5 SPECIAL REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

81h OPTION_REG RAPU

82h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000

83h STATUS IRP RP1 RP0 TO

84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISGPA TRISA7 TRISA6 TRISA5

86h TRISGPB TRISB7 TRISB6 TRISB5 TRISB4

87h PIE1

88h PIE2 CDSIE

89h

8Ah PCLATH

8Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF

8Ch — Unimplemented — —

8Dh — Unimplemented — —

8Eh — Unimplemented — —

8Fh — Unimplemented — —

90h VINUVLO

91h VINOVLO

92h VINCON UVLOEN UVLOOUT UVLOINTP UVLOINTN OVLOEN OVLOOUT OVLOINTP OVLOINTN 0x00 0x00 0u00 0u00

93h CC1RL

94h CC1RH

95h CC2RL

96h CC2RH

97h CCDCON CC2M<3:0> CC1M<3:0> xxxx xxxx uuuu uuuu

98h DESATCON CDSMUX CDSWDE Reserved CDSPOL CDSOE CDSOUT CDSINTP CDSINTN 0000 0x00 0000 0u00

99h OVCON 9Ah OVREFCON OOV7 OOV6 OOV5 OOV4 OOV3 OOV2 OOV1 OOV0 xxxx xxxx uuuu uuuu 9Bh DEADCON PDRVDT3 PDRVDT2 PDRVDT1 PDRVDT0 SDRVDT3 SDRVDT2 SDRVDT1 SDRVDT0 xxxx xxxx uuuu uuuu

9Ch SLPCRCON

9Dh ICOACON

9Eh ICLEBCON

9Fh — Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR

— Unimplemented — —

2: MCLR

and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists.

— ADIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE -000 0000 -000 0000

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

— — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0 --xx xxxx --uu uuuu — — OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0 --xx xxxx --uu uuuu

— — — — OVEN OVOUT OVINTP OVINTN ---- 0x00 ---- 0u00

— SLPBY SLPS5 SLPS4 SLPS3 SLPS2 SLPS1 SLPS0 -xxx xxxx -uuu uuuu — — — — ICOAC3 ICOAC2 ICOAC1 ICOAC0 ---- xxxx ---- uuuu — — — — — — ICLEBC1 ICLEBC0 ---- --xx ---- --uu

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC 0001 1xxx 000q quuu

— TRISA3 TRISA2 TRISA1 TRISA0 1110 1111 1110 1111

— — TRISB1 TRISB0 1111 0011 1111 0011

— — OTIE OVIE DRUVIE OVLOIE UVLOIE 0--0 0000 0--0 0000

(2)

Capture1/Compare1 Register1 x Low Byte (LSB) xxxx xxxx uuuu uuuu

Capture1/Compare1 Register2 x High Byte (MSB) xxxx xxxx uuuu uuuu

Capture2/Compare2 Register1 x Low Byte (LSB) xxxx xxxx uuuu uuuu

Capture2/Compare2 Register2 x High Byte (MSB) xxxx xxxx uuuu uuuu

Reset and Watchdog Timer Reset during normal operation.

0000 000x 0000 000u

(1)

MCP19114/5

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MCP19114/5

TABLE 10-4: MCP19114/5 SPECIAL REGISTERS SUMMARY BANK 2

Adr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000

103h STATUS IRP RP1 RP0 TO 104h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

105h WPUGPA

106h WPUGPB WPUB7 WPUB6 WPUB5 WPUB4

107h PE1 PDRVEN SDRVEN PDRVBY SDRVBY

108h MODECON MSC1 MSC0 RFB

109h ABECON DIGOEN DSEL2 DSEL1 DSEL0 DRUVSEL

10Ah PCLATH

10Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF

10Ch — Unimplemented — — 10Dh — Unimplemented — —

10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h SSPADD ADD<7:0> 0000 0000 0000 0000

111h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 112h SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 0000 0000 0000 0000 113h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 114h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 115h SSPMSK1 MSK<7:0> 1111 1111 1111 1111

116h SSPSTAT SMP CKE D/A 117h SSPADD2 ADD2<7:0> 0000 0000 0000 0000 118h SSPMSK2 MSK2<7:0> 1111 1111 1111 1111 119 h — Unimplemented — — 11A h — Unimplemented — — 11B h — Unimplemented — — 11C h — Unimplemented — — 11D h — Unimplemented — — 11E h — Unimplemented — — 11F h — Unimplemented — —

— — WPUA5 — WPUA3 WPUA2 WPUA1 WPUA0 --1- 1111 --u- uuuu

— — — — — 001- ---- 001- ----

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

PSR/WUA BF ——

PD ZDC C 0001 1xxx 000q quuu

— — WPUB1 — 1111 --1- uuuu --u- — ISPUEN PWMSTR_PEN PWMSTR_SEN 0000 -100 0000 -100

— EADIS ANAOEN 0000 0-00 0000 0-00

(2)

0000 000x 0000 000u

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR

2: MCLR

and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists.

Reset and Watchdog Timer Reset during normal operation.

(1)

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TABLE 10-5: MCP19114/5 SPECIAL REGISTERS SUMMARY BANK 3

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets

Bank 3

180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu

181h OPTION_REG RAPU

182h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000

183h STATUS IRP RP1 RP0 TO

184h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

185h IOCA IOCA7 IOCA6 IOCA5

186h IOCB IOCB7 IOCB6 IOCB5 IOCB4

187h ANSELA

188h ANSELB

189h — Unimplemented — —

18Ah PCLATH

18Bh INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF

18Ch PORTICD

18Dh TRISICD

18Eh ICKBUG

18Fh BIGBUG

190h PMCON1

191h PMCON2 Program Memory Control Register 2 (not a physical register) ---- ---- ---- ----

192h PMADRL PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000

193h PMADRH

194h PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 0000 0000

195h PMDATH

196h DSTCAL

197h RFBTCAL

198h OSCCAL

199h DCSCAL

19Ah TTACAL

19Bh BGRCAL

19Ch VROCAL

19Dh — Unimplemented — —

19Eh — Unimplemented — —

19Fh — Reserved — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR

2: MCLR 3: Only accessible when DBGEN

(3)

and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists.

— — — — ANSA3 ANSA2 ANSA1 ANSA0 ---- 1111 ---- 1111 — — ANSB5 ANSB4 — ANSB2 ANSB1 — --11 -11- --11 -11-

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

— CALSEL — — —WRENWR RD -0-- -000 -0-- -000

— — — — PMADRH3 PMADRH2 PMADRH1 PMADRH0 ---- -000 ---- -000

— — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 --00 0000 --00 0000 — — — DSTCAL4 DSTCAL3 DSTCAL2 DSTCAL1 DSTCAL0 ---x xxxx ---u uuuu — — RFBCAL5 RFBCAL4 RFBCAL3 RFBCAL2 RFBCAL1 RFBCAL0 --xx xxxx --uu uuuu — F CALT 6 FCA LT5 F CALT 4 F CALT 3 FC ALT 2 FC ALT1 F CALT 1 -xxx xxxx -uuu uuuu — — DCSCAL5 DCSCAL4 DCSCAL3 DCSCAL2 DCSCAL1 DCSCAL0 --xx xxxx --uu uuuu — — — — T TA3 T TA2 T TA1 TTA 0 ---- xxxx ---- uuuu — — — — BGRT3 BGRT2 BGRT1 BGRT0 ---- xxxx ---- uuuu — — — VROT4 VROT3 VROT2 VROT1 VROT0 ---x xxxx ---u uuuu

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— IOCA3 IOCA2 IOCA1 IOCA0 000- 0000 0000 0000

— — IOCB1 IOCB0 0000 -000 0000 -000

(2)

In-Circuit Debug Port Register xxx --xx uuuu --uu

In-Circuit Debug TRIS Register 1111 0011 1111 0011

In-Circuit Debug Register 0000 0000 000u uuuu

In-Circuit Debug Breakpoint Register 0000 0000 uuuu uuuu

Reset and Watchdog Timer Reset during normal operation.

= 0 and ICKBUG<INBUG> = 1.

0000 000x 0000 000u

(1)

MCP19114/5

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Bit Value

TMR0

Rate

WDT Rate

000 1: 2 1: 1 001 1: 4 1: 2 010 1: 8 1: 4 011 1: 16 1: 8 100 1: 32 1: 16 101 1: 64 1: 32 110 1: 128 1: 64 111 1: 256 1: 128

10.3.1 OPTION_REG REGISTER

The OPTION_REG register is a readable and writable register, which contains various control bits to configure:

• Timer0/WDT prescaler

• External GPA2/INT interrupt

•Timer0

• Weak pull-ups on PORTGPA and PORTGPB

Note: To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ in the OPTION_REG register. Refer to

Section 22.1.3 “Software Programmable Prescaler”.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RAPU

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR x = Bit is unknown ‘0’ = Bit is cleared

‘1’ = Bit is set

bit 7 RAPU

bit 6 INTEDG: Interrupt Edge Select bit

bit 5 T0CS: TMR0 Clock Source Select bit

bit 4 T0SE: TMR0 Source Edge Select bit

bit 3 PSA: Prescaler Assignment bit

bit 2-0 PS<2:0>: Prescaler Rate Select bits

INTEDG T0CS T0SE PSA PS2 PS1 PS0

: Port GPx Pull-up Enable bit

1 = Port GPx pull-ups are disabled 0 = Port GPx pull-ups are enabled

0 = Interrupt on rising edge of INT pin 1 = Interrupt on falling edge of INT pin

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

1 = Prescaler is assigned to WDT 0 = Prescaler is assigned to the Timer0 module

(1)

Note 1: Individual WPUx bit must also be enabled.

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12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO, CALL

OPCODE <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

Destination

10.4 PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 10-3 shows the two situations for loading the PC: the upper example shows how the PC is loaded on a write to PCL (PCLATH <4:0>  PCH), while the lower example in Figure 10-3 shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3>  PCH).

FIGURE 10-3: PROGRAM COUNTER

(PC) LOADING IN DIFFERENT SITUATIONS

10.4.3 COMPUTED FUNCTION CALLS

A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

10.4.4 STACK

The MCP19114/5 have an 8-level x 13-bit wide hardware stack (refer to Figure 10-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the 9 push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

10.4.1 MODIFYING PCL REGISTER

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<12:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 5 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

10.4.2 COMPUTED GOTO

A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address roll over from 0xFFh to 0X00h in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the table location within the table.

For more information, refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

 2014 Microchip Technology Inc. DS20005281A-page 77

Note 1: There are no Status bits to indicate Stack

Overflow or Stack Underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address.

10.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register directly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit in the STATUS register, as shown in Figure 10-4.

A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 10-3.

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MCP19114/5

MOVLW 0x40 ;initialize pointer MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer BTFSS FSR,7 ;all done? GOTO NEXT ;no clear next

CONTINUE ;yes continue

Data Memory

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1 RP0 6

From Opcode

IRP File Select Register

Bank Select

Location Select

00 01 10 11

180h

1FFh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail, refer to Figure 10-2.

EXAMPLE 10-3: INDIR ECT ADDRESSI NG

FIGURE 10-4: DIRECT/INDIRECT ADDRESSING

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11.0 DEVICE CONFIGURATION

Device Configuration consists of Configuration Word, Code Protection and Device ID.

Note: The DBGEN bit in Configuration Word is

managed automatically by device development tools, including debuggers and programmers. For normal device

11.1 Configuration Word

There are several Configuration Word bits that allow

operation, this bit should be maintained as a '1'. Debug is available only on the MCP19115.

different timers to be enabled and memory protection options. These are implemented as Configuration Word at 2007h

R/P-1 U-1 R/P-1 R/P-1 U-1 R/P-1

DBGEN

bit 13 bit 8

U-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 U-1 U-1

—CPMCLRE PWRTE WDTE — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

—WRT1WRT0 —BOREN

bit 13 DBGEN: ICD Debug bit

1 = ICD debug mode disabled 0 = ICD debug mode enabled

bit 12 Unimplemented: Read as ‘0’ bit 11-10 WRT<1:0>: Flash Program Memory Self Write Enable bit

11 = Write protection off 10 = 000h to 3FFh write protected, 400h to FFFh may be modified by PMCON1 control 01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON1 control 00 = 000h to FFFh write protected, entire program memory is write protected.

bit 9 Unimplemented: Read as ‘0’ bit 8 BOREN: Brown-out Reset Enable bit

1 = BOR disabled during Sleep and Enabled during operation 0 = BOR disabled

bit 7 Unimplemented: Read as ‘0’ bit 6 CP

bit 5 MCLRE: MCLR

bit 4

bit 3 WDTE: Watchdog Timer Enable bit

bit 2-0 Unimplemented: Read as ‘0’

: Code Protection

1 = Program memory is not code protected 0 = Program memory is external read and write protected

Pin Function Select

1 =MCLR 0 =MCLR

PWRTE

1 = PWRT disabled 0 = PWRT enabled

1 = WDT enabled 0 = WDT disabled

pin is MCLR function and weak internal pull-up is enabled pin is alternate function, MCLR function is internally disabled

: Power-up Timer Enable bit

(1)

Note 1: Bit is reserved and not controlled by user.

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MCP19114/5

11. 2 Code Protection

Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting.

11.2.1 PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP Configuration Word. When CP writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the

write protection setting. Refer to Section 11.3 “Write

Protection” for more information.

= 0, external reads and

11.3 Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in the Configuration Word define the size of the program memory block that is protected.

bit in the

11.4 ID Locations

Four memory locations (2000h – 2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB Integrated Development Environment (IDE).

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12.0 OSCILLATOR MODES

The MCP19114/5 have one oscillator configuration which is an 8 MHz internal oscillator.

12.1 Internal Oscillator (INTOSC)

The Internal Oscillator module provides a system clock source of 8 MHz. The frequency of the internal oscillator can be trimmed with a calibration value in the OSCTUNE register.

12.2 Oscillator Calibration

The 8 MHz internal oscillator is factory-calibrated. The factory calibration values reside in the read-only CALWD6 register. These values must be read from the CALWD6 register and stored in the OSCCAL register.

Refer to Section 17.0 “Flash Program Memory

Control” for the procedure on reading the program

memory.

Note: The FCAL<6:0> bits in the CALWD6

12.3 Frequency Tuning in User Mode

In addition to the factory calibration, the base frequency can be tuned in the user's application. This frequency tuning capability allows the user to deviate from the factory-calibrated frequency. The user can tune the frequency by writing to the OSCTUNE register (refer to Register 12-1).

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN<4:0>: Frequency Tuning bits

01111 = Maximum frequency 01110 =

•

00001 = 00000 = Center frequency. Oscillator Module is running at the calibrated frequency. 11111 =

•

• 10000 = Minimum frequency

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12.3.1 OSCILLATOR DELAY UPON POWER-UP, WAKE-UP AND BASE FREQUENCY CHANGE

In applications where the OSCTUNE register is used to shift the frequency of the internal oscillator, the application should not expect the frequency of the internal oscillator to stabilize immediately. In this case, the frequency may shift gradually toward the new value. The time for this frequency shift is less than eight cycles of the base frequency.

On power-up, the device is held in reset by the power-up time if the power-up timer is enabled.

Following a wake-up from Sleep mode or POR, an internal delay of ~10 µs is invoked to allow the memory bias to stabilize before program execution can begin.

TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCTUNE

Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by clock sources.

— — — TUN4 TUN3 TUN2 TUN1 TUN0 81

TABLE 12-2: SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG6

Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by clock sources.

13:8

7:0

— — — — — — — —

— FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0

on Page

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MCP19114/5

WDT

Module

VDDRise

Detect

Brown-out

Reset

Sleep

BOREN

MCLR/TEST_EN

External

Reset

On-Chip

RC OSC

11-bit Ripple Counter

PWRT

Enable PWRT

Chip_Reset

Power-on Reset

Time-out

Reset

Brown-out

Reset

13.0 RESETS

Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any

The reset logic is used to place the MCP19114/5 into a known state. The source of the reset can be determined by using the device status bits.

There are multiple ways to reset these devices:

• Power-on Reset (POR)

• Overtemperature Reset (OT)

•MCLR

Reset

•WDT Reset

• Brown-out Reset (BOR)

To a llo w V

to stabilize, an optional power-up timer

can be enabled to extend the Reset time after a POR event.

other Reset. Most other registers are reset to a “Reset state” on:

• Power-on Reset

•MCLR

Reset Reset during Sleep

• WDT Reset

• Brown-out Reset

WDT (Watchdog Timer) wake-up does not cause register resets in the same manner as a WDT Reset, since wake-up is viewed as the resumption of normal operation. TO

and PD bits are set or cleared differently in different Reset situations, as indicated in Tab le 1 3- 1. The software can use these bits to determine the nature of the Reset. Refer to Tab le 1 3- 2 for a full description of Reset states of all registers.

A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 13-1.

The MCLR

Reset path has a noise filter to detect and

ignore small pulses. Refer to Section 5.0 “Digital

Electrical Characteristics” for pulse-width

specifications.

FIGURE 13-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

T ABLE 13-1: TIME-OUT IN VARIOUS

PWRTE

 2014 Microchip Technology Inc. DS20005281A-page 83

SITUATIONS

Power-up

= 0 PWRTE = 1

PWRT

Wake-up from

Sleep

——

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MCP19114/5

MCLR

1k (or greater)

0.1 µF (optional, not critical)

100

(needed with

(optional)

MCP19114/5

capacitor)

TABLE 13-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR BOR TO PD Condition

0x11Power-on Reset u011Brown-out Reset uu0uWDT Reset uu00WDT Wake-up

uuuuMCLR uu10MCLR

Legend: u = unchanged, x = unknown

Reset during normal operation

Reset during Sleep

13.1 Power-on Reset (POR)

The on-chip POR circuit holds the chip in Reset until

has reached a high enough level for proper

operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset.

Note: The POR circuit does not produce an

internal Reset when V re-enable the POR, V (A

) for a minimum of 100 µs.

GND

When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.

declines. To

must reach V

13.2 MCLR

MCP19114/5 have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive

pin low.

MCLR

Voltages applied to the MCLR specification can result in both MCLR excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR directly to V

. The use of a Resistor-Capacitor (RC)

network, as shown in Figure 13-2, is suggested.

An internal MCLR option is enabled by clearing the MCLRE bit in the CONFIG register. When MCLRE = 0, the Reset signal to the chip is generated internally. When MCLRE = 1, the MCLR Reset input. In this mode, the MCLR pull-up to V

FIGURE 13-2: RECOMMENDED MCLR

CIRCUIT

pin that exceed its

Resets and

pin no longer be tied

pin becomes an external

pin has a weak

DS20005281A-page 84  2014 Microchip Technology Inc.

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MCP19114/5

Internal Reset

BOR

64 ms

(1)

64 ms

(1)

64 ms

(1)

<64ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

13.3 Brown-out Reset (BOR)

The BOREN bit <8> in the CONFIG register enables or disables the BOR mode, as defined in the CONFIG register. A brown-out occurs when V V

for greater than 100 µs minimum. On any Reset

BOR

(Power-on, Brown-out, Watchdog Timer, etc.), the chip will remain in Reset until V

rises above V

to Figure 13-3). If enabled, the Power-up Timer will be invoked by the Reset and will keep the chip in Reset an additional 64 ms.

FIGURE 13-3: BROWN-OUT SITUATIONS

falls below

BOR

(refer

Note: The Power-up Timer is enabled by the

PWRTE drops below V

bit in the CONFIG register. If V

while the Power-up

BOR

Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once the V rises above V

, the Power-up Timer will

BOR

execute a 64 ms reset.

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MCP19114/5

PWRT

IOSCST

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

13.4 Power-up Timer (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR Reset. The Power-up Timer operates from an internal RC oscillator. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the V acceptable level. A bit (P register can disable (if set) or enable (if cleared or programmed) the Power-up Timer.

The Power-up Timer delay will vary from chip to chip due to:

variation

•V

• Temperature variation

• Process variation

Note: Voltage spikes below V

pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR rather than pulling this pin directly to V

The Power-up Timer optionally delays device execution after a POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE the CONFIG register.

WRTE) in the CONFIG

to rise to an

at the MCLR

pin,

bit in

13.5 Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO changed to indicate the WDT Reset. Refer to

Section 16.0 “Watchdog Timer (WDT)” for more

information.

and PD bits in the STATUS register are

13.6 Start-up Sequence

Upon the release of a POR, the following must occur before the device begins executing:

• Power-up Timer runs to completion (if enabled)

• Oscillator start-up timer runs to completion

•MCLR

The total time-out will vary based on PWRTE For example, with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figures 13-4, 13-5 and 13-6 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR (refer to Figure 13-5). This is useful for testing purposes or to synchronize more than one MCP19114/5 device operating in parallel.

13.6.1 POWER CONTROL (PCON)

The Power Control (PCON) register (address 8Eh) has two Status bits to indicate what type of Reset occurred last.

must be released (if enabled)

bit status.

high will begin execution immediately

FIGURE 13-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

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MCP19114/5

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

PWRT

IOSCST

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal Reset

PWRT

IOSCST

FIGURE 13-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

FIGURE 13-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR

13.7 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Tables 13-3 and 13-4 show the Reset conditions of these registers.

 2014 Microchip Technology Inc. DS20005281A-page 87

TABLE 13-3: RESET STATUS BITS AND

POR BOR TO PD Condition

0x11Power-on Reset u011Brown-out Reset uu0uWDT Reset uu00WDT Wake-up from Sleep uu10Interrupt Wake-up from

uuuuMCLR

uu10MCLR 0u0xNot allowed. TO

0ux0Not allowed. PD is set on

WITH VDD)

THEIR SIGNIFICANCE

Sleep

Reset during normal

operation

Reset during Sleep

is set on

POR.

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MCP19114/5

TABLE 13-4: RESET CONDITION FOR SPECIAL REGISTERS (Note 2)

Condition

Power-on Reset 0000h 0001 1xxx ---- --0u Brown-out Reset 0000 0001 1xxx ---- --u0

MCLR Reset during normal operation 0000h 000u uuuu ---- --uu

MCLR

Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu WDT Wake-up from Sleep PC + 1 uuu0 0uuu ---- --uu

Interrupt Wake-up from Sleep PC + 1

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed

on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

2: If a Status bit is not implemented, that bit will be read as ‘0’.

Program

Counter

(1)

STATUS

uuu1 0uuu ---- --uu

PCON

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13.8 Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR

• Brown-out Reset (BOR)

The PCON register bits are shown in Register 13-1.

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — —PORBOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as '0' bit 1 POR

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 Unimplemented: Read as '0'

)

: Power-on Reset Status bit

TABLE 13-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PCON

STATUS IPR RP1 RP0 TO

Legend: — = unimplemented bit, read as ‘0’. Shaded cells are not used by Resets. Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

— — — — — —PORBOR 89

PD ZDCC69

on Page

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MCP19114/5

NOTES:

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14.0 INTERRUPTS

The MCP19114/5 have multiple sources of interrupt:

• External Interrupt (INT pin)

• Interrupt-On-Change (IOC) Interrupts

• Timer0 Overflow Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• ADC Interrupt

• System Input Undervoltage Error

• System Input Overvoltage Error

• SSP

•BCL

• Desaturation Detection

• Gate Drive UVLO

• Capture/Compare 1

• Capture/Compare 2

• Overtemperature

The Interrupt Control (INTCON) register and the Peripheral Interrupt Request (PIRx) registers record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits.

The Global Interrupt Enable bit, GIE, in the INTCON register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIEx registers. GIE is cleared on Reset.

When an interrupt is serviced, the following actions occur automatically:

• The GIE is cleared to disable any further interrupt

• The return address is pushed onto the stack

• The PC is loaded with 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

14.1 Interrupt Latency

For external interrupt events, such as the INT pin or PORTGPx change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (refer to

Figure 14-2). The latency is the same for one- or

two-cycle instructions.

14.2 GPA2/INT Interrupt

The external interrupt on the GPA2/INT pin is edge-triggered, either on the rising edge, if the INTEDG bit in the OPTION_REG register is set, or the falling edge, if the INTEDG bit is clear. When a valid edge appears on the GPA2/INT pin, the INTF bit in the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit in the INTCON register. The INTF bit must be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The GPA2/INT interrupt can wake up the processor from Sleep, if the INTE bit was set prior to

going into Sleep. Refer to Section 15.0 “Power-Down

Mode (Sleep)” for details on Sleep and Section 15.1 “Wake-up from Sleep” for timing of wake-up from

Sleep through GPA2/INT interrupt.

Note: The ANSEL register must be initialized to

configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.

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MCP19114/5

TMR1IF TMR1IE

SSPIF SSPIE

IOCF

IOCE

INTF INTE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

PEIF

ADIF ADIE

CDSIF CDSIE

OTIF

OTIE

OVIF

OVIE

DRUVIF

DRUVIE

BCLIF

BCLIE

TMR2F

TMR2E

T0IF T0IE

Plx2

UVLOIF

UVLOIE

OVLOIF OVLOIE

Plx1

CC2IF CC2IE

CC1IF CC1IE

INTCON

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

CLKIN

INT pin

INTF flag (INTCON reg.)

GIE bit (INTCON reg.)

INSTRUCTION FLOW

Instruction Fetched

Instruction Executed

PC PC + 1

PC + 1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC + 1)

Inst (PC – 1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 T

. Synchronous latency = 3 TCY, where TCY= instruction cycle time.

Latency is the same whether Inst (PC) is a single-cycle or a two-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in

Section 5.0 “Digital Electrical Characteristics”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

CLKOUT

(3)

(4)

(1)

(5)

(1)

Interrupt Latency

(2)

FIGURE 14-1: INTERRUPT LOGIC

FIGURE 14-2: INT PIN INTERRUPT TIMING

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14.3 Interrupt Control Registers

14.3.1 INTCON REGISTER

The INTCON register is a readable and writable register, that contains the various enable and flag bits for the TMR0 register overflow, interrupt-on-change and external INT pin interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, in the INTCON register. The user’s software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE IOCE T0IF INTF IOCF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts 0 = Disables all interrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt 0 = Disables the INT external interrupt

bit 3 IOCE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: External Interrupt Flag bit

1 = The external interrupt occurred (must be cleared in software) 0 = The external interrupt did not occur

bit 0 IOCF: Interrupt-on-Change Interrupt Flag bit

1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state

(1)

(2)

Note 1: IOCx registers must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

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MCP19114/5

14.3.1.1 PIE1 Register

The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 14-2.

Note 1: Bit PEIE in the INTCON register must be

set to enable any peripheral interrupt.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: ADC Interrupt Enable bit

1 = Enables the ADC interrupt 0 = Disables the ADC interrupt

bit 5 BCLIE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt

bit 4 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt

bit 3 CC2IE: Capture2/Compare2 Interrupt Enable bit

1 = Enables the Capture2/Compare2 interrupt 0 = Disables the Capture2/Compare2 interrupt

bit 2 CC1IE: Capture1/Compare1 Interrupt Enable bit

1 = Enables the Capture1/Compare1 interrupt 0 = Disables the Capture1/Compare1 interrupt

bit 1 TMR2IE: Timer2 Interrupt Enable

1 = Enables the Timer2 interrupt 0 = Disables the Timer2 interrupt

bit 0 TMR1IE: Timer1 Interrupt Enable

1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt

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14.3.1.2 PIE2 Register

The PIE2 register contains the Peripheral Interrupt Enable bits, as shown in Register 14-3.

Note 1: Bit PEIE in the INTCON register must be

set to enable any peripheral interrupt.

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CDSIE — — OTIE OVIE DRUVIE OVLOIE UVLOIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CDSIE: Desaturation Detection Interrupt Enable bit

1 = Enables the DESAT Detect interrupt 0 = Disables the DESAT Detect interrupt

bit 6-5 Unimplemented: Read as ‘0’ bit 4 OTIE: Overtemperature Interrupt Enable bit

1 = Enables overtemperature interrupt 0 = Disables overtemperature interrupt

bit 3 OVIE: V

1 = Enables the OV interrupt 0 = Disables the OV interrupt

bit 2 DRUVIE: Gate Drive Undervoltage Lockout Interrupt Enable bit

1 = Enables Gate Drive UVLO interrupt 0 = Disables Gate Drive UVLO interrupt

bit 1 OVLOIE: V

1 = Enables OVLO interrupt 0 = Disables OVLO interrupt

bit 0 UVLOIE: V

1 = Enables UVLO interrupt 0 = Disables UVLO interrupt

Overvoltage Interrupt Enable bit

OUT

Overvoltage Lockout Interrupt Enable bit

Undervoltage Lockout Interrupt Enable bit

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14.3.1.3 PIR1 Register

The PIR1 register contains the Peripheral Interrupt Flag bits, as shown in Register 14-4.

Note 1: Interrupt flag bits are set when an

interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, in the INTCON register. The user’s software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: ADC Interrupt Flag bit

1 = ADC conversion complete 0 = ADC conversion has not completed or has not been started

bit 5 BCLIF: MSSP Bus Collision Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 4 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit

1 = Interrupt is pending 0 = Interrupt is not pending

bit 3 CC2IF: Capture2/Compare2 Interrupt Flag bit

1 = Capture or Compare has occurred 0 = Capture or Compare has not occurred

bit 2 CC1IF: Capture1/Compare1 Interrupt Flag bit

1 = Capture or Compare has occurred 0 = Capture or Compare has not occurred

bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag

1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match did not occur

bit 0 TMR1IF: Timer1 Interrupt Flag

1 = Timer1 rolled over (must be cleared in software) 0 = Timer1 has not rolled over

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14.3.1.4 PIR2 Register

The PIR2 register contains the Peripheral Interrupt Flag bits, as shown in Register 14-3.

Note 1: Interrupt flag bits are set when an

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CDSIF — — OTIF OVIF DRUVIF OVLOIF UVLOIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CDSIF: DESAT Detect Interrupt Flag bit

1 = Normal Operation (CDSPOL = 0, CDSINTP = 0, CDSINTN = 1) 0 = Desaturation Detection has occurred

bit 6-5 Unimplemented: Read as ‘0’ bit 4 OTIF: Overtemperature Interrupt Flag bit

1 = Overtemperature event has occurred 0 = Overtemperature event has not occurred

bit 3 OVIF: Overvoltage Interrupt Flag bit

1 =V 0 =V

bit 2 DRUVIF: Gate Drive Undervoltage Lockout Interrupt Flag bit

1 = Gate Drive Undervoltage Lockout has occurred 0 = Gate Drive Undervoltage Lockout has not occurred

bit 1 OVLOIF: V

1 =VIN has exceeded the level defined by OVLO_DAC 0 =V

bit 0 UVLOIF: V

1 =VIN is below level defined by UVLO_DAC 0 =V

has exceeded the level defined by OV_REF

OUT

is below level defined by OV_REF

OUT

Overvoltage Lockout Interrupt Flag bit

is below level defined by OVLO_DAC

Undervoltage Lockout Interrupt Flag bit

is above level defined by UVLO_DAC

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MOVWF W_TEMP ;Copy W to TEMP register SWAPF STATUS,W ;Swap status to be saved into W

;Swaps are used because they do not affect the status bits MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) ;Insert user code here : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

TABLE 14-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 93

OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 76

PIE1 — ADIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 94

PIE2 CDSIE — — OTIE OVIE DRUVIE OVLOIE UVLOIE 95

PIR1

PIR2 CDSIF — — OTIF OVIF DRUVIF OVLOIF UVLOIF 97

Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Interrupts.

— ADIF BCLIF SSPIF — — TMR2IF TMR1IF 96

14.4 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software.

Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR (refer to Figure 10-3). These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example 14-1 can be used to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit) register

• Restore the W register

on Page

Note: The MCP19114/5 do not require saving

the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR.

EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM

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MCP19114/5

15.0 POW ER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a SLEEP instruction.

Upon entering Sleep mode, the following conditions exist:

1. WDT will be cleared but keeps running, if enabled for operation during Sleep.

2. PD

3. TO bit in the STATUS register is set.

4. CPU clock is disabled.

5. The ADC is inoperable due to the absence of the

6. I/O ports maintain the status they had before

7. Resets other than WDT are not affected by

8. Analog Circuit power (AV

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating.

• External circuitry sinking current from I/O pins.

• Internal circuitry sourcing current from I/O pins.

• Current draw from pins with internal weak

• Modules using Timer1 oscillator.

I/O pins that are high-impedance inputs should be pulled to V currents caused by floating inputs.

The SLEEP instruction removes power from the analog circuitry. AV Sleep mode and to maintain a shutdown current of 50 µA typical. The 5V LDO (V

2.5V – 3V in Sleep mode. The enable state of the

analog circuitry does not change with the execution of the SLEEP instruction.

bit in the STATUS register is cleared.

4V LDO power (AVDD).

SLEEP was executed (driving high, low or high-impedance).

Sleep mode.

) is removed during

Sleep mode.

pull-ups.

or GND externally to avoid switching

is shut down to minimize current draw in

) voltage drops to

15.1 Wake-up from Sleep

The device can wake up from Sleep through one of the following events:

1. External Reset input on MCLR

2. POR Reset

3. Watchdog Timer, if enabled

4. Any external interrupt

5. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)

The first two events will cause a device reset. The last three events are considered a continuation of program execution. To determine whether a device reset or

wake-up event occurred, refer to Section 13.7

“Determining the Cause of a Reset”.

The following peripheral interrupts can wake the device from Sleep:

1. Interrupt-on-change

2. External Interrupt from INT pin

When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction and will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up.

pin, if enabled

 2014 Microchip Technology Inc. DS20005281A-page 99

Page 100

MCP19114/5

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC

Interrupt flag

GIE bit

(INTCON reg.)

Instruction Flow

Instruction Fetched

Instruction Executed

PC PC + 1 PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2 0004h 0005h

Dummy Cycle

OST

PC + 2

Note 1: GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

Interrupt Latency

(1)

15.1.1 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP instruction

- SLEEP instruction will execute as an NOP

- WDT and WDT prescaler will not be cleared bit in the STATUS register will not be set

-TO

-PD

bit in the STATUS register will not be

cleared

• If the interrupt occurs during or after the

execution of a SLEEP instruction

- SLEEP instruction will be completely

executed

- Device will immediately wake up from Sleep

- WDT and WDT prescaler will be cleared

-TO

bit in the STATUS register will be set

-PD bit in the STATUS register will be cleared

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test

bit. If the PD bit is set, the SLEEP instruction

the PD was executed as an NOP.

FIGURE 15-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 93

IOCA IOCA7 IOCA6 IOCA5

IOCB IOCB7 IOCB6 IOCB5 IOCB4

— IOCA3 IOCA2 IOCA1 IOCA0 120

— —IOCB1IOCB0 120

PIE1 — ADIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 94

PIE2 CDSIE — — OTIE OVIE DRUVIE OVLOIE UVLOIE 95

PIR1

— ADIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF 96

PIR2 CDSIF — — OTIF OVIF DRUVIF OVLOIF UVLOIF 97

STATUS

IRP RP1 RP0 TO PD ZDCC 69

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.

DS20005281A-page 100  2014 Microchip Technology Inc.

Page

Datasheet MCP19114, MCP19115 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features:

Microcontroller Features:

Pin Diagram – 24-Pin QFN (MCP19114)

Pin Diagram – 28-Pin QFN (MCP19115)

Table of Contents

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Errata

Customer Notification System

1.0 DEVICE OVERVIEW

FIGURE 1-1: MCP19114/5 FLYBACK SYNCHRONOUS QUASI-RESONANT BLOCK DIAGRAM

FIGURE 1-2: MCP19114 CUK’ SYNCHRONOUS POSITIVE OUTPUT APPLICATION DIAGRAM

FIGURE 1-3: MCP19114 BOOST QUASI-RESONANT APPLICATION DIAGRAM

FIGURE 1-4: MICROCONTROLLER CORE BLOCK DIAGRAM

2.0 PIN DESCRIPTION

2.1 Detailed Pin Functional Description

3.0 FUNCTIONAL DESCRIPTION

3.1 Linear Regulators

3.2 Output Drive Circuitry

3.3 Current Sense

3.4 Peak Current Mode

3.5 Magnetic Desaturation Detection

3.6 Start-up

3.7 Driver Control Circuitry

3.8 Fixed PWM Frequency

3.10 OV REF

3.11 Independent Gate Drive with Programmable Delay

3.12 Temperature Management

4.0 ELECTRICAL CHARACTERISTICS

4.2 Electrical Characteristics

4.3 Thermal Specifications

5.0 DIGITAL ELECTRICAL CHARACTERISTICS

5.1 Timing Parameter Symbology

FIGURE 5-1: LOAD CONDITIONS

5.2 AC Characteristics: MCP19114 (Industrial, Extended)

FIGURE 5-2: EXTERNAL CLOCK TIMING

FIGURE 5-3: I/O TIMING

FIGURE 5-5: BROWN-OUT RESET TIMING AND CHARACTERISTICS

FIGURE 5-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMING

FIGURE 5-7: PWM TIMINGS

FIGURE 5-8: A/D CONVERSION TIMING

6.0 CONFIGURING THE MCP19114/5

6.1 Input Undervoltage and Overvoltage Lockout (UVLO and OVLO)

6.2 Output Overvoltage Protection

EXAMPLE 6-1: EXAMPLE OVREF CORRECTION ROUTINE

6.3 Desaturation Detection for Quasi-Resonant Operation

6.4 Primary Input Current Offset Adjust

6.5 Leading Edge Blanking

6.6 Slope Compensation

6.7 MOSFET Driver Programmable Dead Time

6.8 Output Regulation Reference Voltage Configuration

EXAMPLE 6-2: EX AMP LE A2 GAIN CORRECTION

EXAMPLE 6-3: VREF2 CORRECTION ROUTINE

6.10 Analog Peripheral Control

6.11 Analog Blocks Enable Control

6.12 Mode and RFB MUX Control

7.0 TYPICAL PERFORMANCE CURVES

FIGURE 7-1: IQ vs. Temperature.

FIGURE 7-4: Load Regulation.

FIGURE 7-2: IQ vs. Temperature in Sleep Mode.

FIGURE 7-3: Line Regulation.

FIGURE 7-7: Output Driver Dead Ti me vs. Code and Temperature.

FIGURE 7-12: Oscillator Frequency vs. Temperature.

FIGURE 7-13: Normalized Output Demand vs. Temperature.

8.0 SYSTEM BENCH TESTING

9.0 DEVICE CALIBRATION

9.1 Calibration Word 1

9.2 Calibration Word 2

9.3 Calibration Word 3

9.4 Calibration Word 4

9.5 Calibration Word 5

9.6 Calibration Word 6

9.7 Calibration Word 7

9.8 Calibration Word 8

9.9 Calibration Word 9

9.10 Calibration Word 10