Datasheet MCP19114, MCP19115 Datasheet

MCP19114/5

Digitally Enhanced Po wer An alog Syn chr onous Low-Si de PWM Controller

Features:

• Input Voltage: 4.5V to 42V

• Can be configured with Multiple Topologies
including but not limited to:

-Flyback

- Ćuk

-Boost

- SEPIC (Single-Ended Primary-Inductor

Converter)

• Capable of Quasi-Resonant or Fixed-Frequency
Operation

• Low Quiescent Current: 5 mA Typical

• Low Sleep Current: 30 µA Typical

• Low-Side Gate Drivers:

- +5V Gate Drive

- 0.5A Sink/Source Current

-+10V Gate Drive

- 1A Sink/Source Current

• Peak Current Mode Control

• Differential Remote Output Sense

• Multiple Output Systems:

- Master or Slave

• Configurable Parameters:

-V

, Precision I

REF

- Input Undervoltage Lockout (UVLO)

- Input Overvoltage Lockout (OVLO)

- Detection and Protection

- Primary Current Leading Edge Blanking (0,

50 ns, 100 ns and 200 ns)

- Gate Drive Dead Time (16 ns to 256 ns)

- Fixed Switching Frequency Range:

31.25 kHz to 2.0 MHz

- Slope Compensation

- Quasi-Resonant Configuration with Built-in

Comparator and Programmable Offset
Voltage Adjustment

- Primary Current Offset Adjustment

- Configurable GPIO Pin Options

• Integrated Low-Side Differential Current Sense
Amplifier

• ±5% Current Regulation

• Thermal Shutdown

OUT/VOUT

Set Point (DAC)

Microcontroller Features:

• Precision 8 MHz Internal Oscillator Block:

- Factory-calibrated to ±1%, typical

• Interrupt Capable

-Firmware

- Interrupt-on-Change Pins

• Only 35 Instructions to Learn

• 4096 Words On-Chip Program Memory

• High Endurance Flash:

- 100,000 write Flash Endurance

- Flash Retention: >40 years

• Watchdog Timer (WDT) with Independent
Oscillator for Reliable Operation

• Programmable Code Protection

• In-Circuit Serial Programming™ (ICSP™) via Two
Pins

• Eight I/O Pins and One Input-Only Pin

- Two Open Drain Pins

• Analog-to-Digital Converter (ADC):

- 10-bit Resolution

- Five External Channels

• Timer0: 8-bit Timer/Counter with 8-bit Prescaler

• Enhanced Timer1:

- 16-bit Timer with Prescaler

- Two Selectable Clock Sources

• Timer2: 8-Bit Timer with Prescaler

- 8-bit Period Register

2

• I

CTM Communication:

- 7-bit Address Masking

- Two Dedicated Address Registers

 2014 Microchip Technology Inc. DS20005281A-page 1

MCP19114/5

MCP19114

1

2

3

4

5

6

13

7

8

9

10

11

12

14

15

16

17

18

23

22

21

20

19

24

EXP-25

GPA0/AN0/TEST_OUT

GPA1/AN1/CLKPIN

GPA2/AN2/T0CKI/INT

GPA3/AN3

GPA7/SCL/ICSPCLK

GPA6/CCD/ICSPDAT

GPA5/MCLR/TEST_EN

GPB0/SDA

DESAT

N

DESAT

P

/I

SOUT

I

SP

I

SN

I

P

A

GND

P

GND

SDRV

PDRV

V

DR

GPB1/AN4/VREF2

I

COMP

I

FB

V

S

V

IN

V

DD

Pin Diagram – 24-Pin QFN (MCP19114)

DS20005281A-page 2  2014 Microchip Technology Inc.

TABLE 1: 24-PIN SUMMARY

MCP19114/5

I/O

ANSEL

A/D

Timers

24-Pin QFN

MSSP

Interrupt

Basic Additional

Pull-up

GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output

GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out

GPA2 3 Y AN2 T0CKI — IOC

Y — —

(2)

INT

GPA3 4 Y AN3 — — IOC Y — —

GPA5 7 N — — — IOC

(4)

(5)

Y

MCLR Test Enable Input

GPA6 6 N — — — IOC Y ICSPDAT Dual Capture/Compare Input

GPA7 5 N — — SCL IOC N ICSPCLK —

GPB0 8 N — — SDA IOC N — —

GPB1 24 Y AN4 — — IOC Y — V

DESAT

DESATP/

I

SOUT

I

SP

9 N — — — — — — DESAT Negative Input

N

10 N — — — — — — DESATP Input or I

11 N — — — — Y — Current Sense Amplifier Positive

REF2

Output

(3)

(6)

SOUT

Input

I

SN

12 N — — — — — — Current Sense Amplifier

Negative Input

A

P

I

P

GND

GND

13 N — — — — — — Primary Input Current Sense

14 N — — — — — A

15 N — — — — — P

GND

GND

Small Signal Ground

Large Signal Ground

SDRV 16 N — — — — — — Secondary LS Gate Drive

Output

PDRV 17 N — — — — — — Primary LS Gate Drive

Output

V

DR

V

DD

V

V

I

FB

I

COMP

IN

S

18 N — — — — — V

19 N — — — — — V

20 N — — — — — V

DR

DD

IN

Gate Drive Supply Voltage

VDD Output

Input Supply Voltage

21 N — — — — — — Output Voltage Sense

22 N — — — — — — Error Amplifier Feedback Input

23 N — — — — — — Error Amplifier Output

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the

MODECON register.

3: V

output selected when configured as master by proper configuration of the MSC<1:0> bits in the

REF2

MODECON register.

4: The IOC is disabled when MCLR
5: Weak pull-up always enabled when MCLR
6: When RFB of MODECON<5> = 0, internal feedback resistor and DESAT

RFB = 1, I

SOUT

is enabled.

is enabled.

is enabled, otherwise the pull-up is under user control.

input are enabled. When

P

(1)

 2014 Microchip Technology Inc. DS20005281A-page 3

MCP19114/5

MCP19115

1

2

3

4

5

6

715

8

9

10

11

12

13

14

16

17

18

19

20

21

26

25

24

23

22

28

27

EXP-29

GPA1/AN1/CLKPIN

GPA2/AN2/T0CKI/INT

GPB4/AN5/ICSPDAT

GPA3/AN3

GPA7/SCL

GPA6/CCD

GPA0/AN0/TEST_OUT

GPB6/AN7

GPB5/AN6/ICSPCLK

GPB1/AN4/VREF2

I

COMP

I

FB

V

S

V

IN

V

DD

V

DR

PDRV

SDRV

P

GND

A

GND

I

P

GPA5/MCLR/TEST_EN

GPB7_CCD

GPB0/SDA

DESAT

N

DESAT

P

/I

SOUT

I

SP

I

SN

Pin Diagram – 28-Pin QFN (MCP19115)

DS20005281A-page 4  2014 Microchip Technology Inc.

TABLE 2: 28-PIN SUMMARY

MCP19114/5

I/O

ANSEL

A/D

Timers

28-Pin QFN

MSSP

Interrupt

Pull-up

Basic Additional

GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output

GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out

GPA2 3 Y AN2 T0CKI — IOC

Y — —

(2)

INT

GPA3 5 Y AN3 — — IOC Y — —

GPA5 8 N — — — IOC

(4)

(5)

Y

MCLR Test Enable Input

GPA6 7 N — — — IOC Y — Dual Capture/Single

Compare1 Input

GPA7 6 N — — SCL IOC N — —

GPB0 10 N — — SDA IOC N — —

GPB1 26 Y AN4 — — IOC Y — V

REF2

(3)

GPB4 4 Y AN5 — — IOC Y ICSPDAT —

GPB5 27 Y AN6 — — IOC Y ICSPCLK —

GPB6 28 Y AN7 — — IOC Y — —

GPB7 9 Y — — — IOC Y — Single Compare2 Input

DESATP/

I

SOUT

12 N — — — — — — DESATP input or I

Output

(6)

SOUT

DESATN11 N — — — — — — DESAT Negative Input

I

SP

13 N — — — — Y — Current Sense Amplifier

Non-Inverting Input

I

SN

14 N — — — — — — Current Sense Amplifier

Inverting Input

A

P

I

P

GND

GND

15 N — — — — — — Primary Input Current Sense

16 N — — — — — A

17 N — — — — — P

GND

GND

Small Signal Ground

Large Signal Ground

SDRV 18 N — — — — — — Secondary LS Gate Drive

Output

PDRV 19 N — — — — — — Primary LS Gate Drive Output

V

DR

V

DD

V

V

I

FB

I

COMP

IN

S

20 N — — — — — V

21 N — — — — — V

22 N — — — — — V

DR

DD

IN

Gate Drive Supply Voltage

VDD Output

Input Supply Voltage

23 N — — — — — — Output Voltage Sense

24 N — — — — — — Error Amplifier Feedback input

25 N — — — — — — Error Amplifier Output

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the

MODECON register.

3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the

MODECON register.

4: The IOC is disabled when MCLR
5: Weak pull-up always enabled when MCLR
6: When RFB of MODECON<6> =0 Internal feedback resistor is enabled allow with DESAT

RFB=1, I

SOUT

is enabled.

is enabled.

is enabled, otherwise the pull-up is under user control.

input. When

P

(1)

 2014 Microchip Technology Inc. DS20005281A-page 5

MCP19114/5

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Pin Description ........................................................................................................................................................................... 13

3.0 Functional Description ................................................................................................................................................................ 19

4.0 Electrical Characteristics............................................................................................................................................................ 22

5.0 Digital Electrical Characteristics................................................................................................................................................. 29

6.0 Configuring the MCP19114/5 ..................................................................................................................................................... 37

7.0 Typical Performance Curves ...................................................................................................................................................... 53

8.0 System Bench Testing................................................................................................................................................................ 57

9.0 Device Calibration ...................................................................................................................................................................... 59

10.0 Memory Organization ................................................................................................................................................................. 67

11.0 Device Configuration.................................................................................................................................................................. 79

12.0 Oscillator Modes......................................................................................................................................................................... 81

13.0 Resets ........................................................................................................................................................................................ 83

14.0 Interrupts .................................................................................................................................................................................... 91

15.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 99

16.0 Watchdog Timer (WDT)............................................................................................................................................................ 101

17.0 Flash Program Memory Control ............................................................................................................................................... 103

18.0 I/O Ports ................................................................................................................................................................................... 109

19.0 Interrupt-On-Change .................................................................................................................................................................119

20.0 Internal Temperature Indicator Module..................................................................................................................................... 123

21.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 125

22.0 Timer0 Module.......................................................................................................................................................................... 135

23.0 Timer1 Module with Gate Control ............................................................................................................................................. 137

24.0 Timer2 Module.......................................................................................................................................................................... 141

25.0 Enhanced PWM Module........................................................................................................................................................... 143

26.0 Dual Capture/Compare (CCD) Module..................................................................................................................................... 147

27.0 PWM Control Logic .................................................................................................................................................................. 151

28.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 153

29.0 Instruction Set Summary .......................................................................................................................................................... 195

30.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 205

31.0 Development Support............................................................................................................................................................... 207

32.0 Packaging Information...............................................................................................................................................................211

Appendix A: Revision History............................................................................................................................................................. 217

Index .................................................................................................................................................................................................. 219

The Microchip Web Site..................................................................................................................................................................... 225

Customer Change Notification Service .............................................................................................................................................. 225

Customer Support .............................................................................................................................................................................. 225

Product Identification System............................................................................................................................................................. 227

DS20005281A-page 6  2014 Microchip Technology Inc.

MCP19114/5

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at [e-mail]. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2014 Microchip Technology Inc. DS20005281A-page 7

MCP19114/5

NOTES:

DS20005281A-page 8  2014 Microchip Technology Inc.

MCP19114/5

1.0 DEVICE OVERVIEW

The MCP19114/5 are highly integrated, mixed signal
low-side synchronous controllers that operate from

4.5V to 42V. The family features an analog PWM
controller with an integrated microcontroller core used
for LED lighting systems, battery chargers and other
low-side switch PWM applications. The devices feature
an analog internal PWM controller similar to the
MCP1631, and a standard PIC
to the PIC12F617.

Complete customization of device operating
parameters, start-up or shutdown profiles, protection
levels and fault handling procedures are accomplished
by setting digital registers using Microchip’s MPLAB
Integrated Development Environment software and
one of Microchip’s many in-circuit debugger and device
programmers.

The MCP19114/5 mixed signal low-side synchronous
controllers feature integrated programmable input
UVLO/OVLO, programmable output overvoltage (OV),
two low-side gate drive outputs with independent
programmable dead time, programmable leading edge
blanking (four steps), programmable 6-bit slope
compensation and an integrated internal
programmable oscillator for fixed-frequency
applications. An integrated 8-bit reference voltage

) is used for setting output voltage or current. An

(V

REF

internal comparator supports quasi-resonant
applications. Additional Capture and Compare
modules are integrated for additional control, including
enhanced dimming capability. The MCP19114/5
devices contain two internal LDOs. A 5V LDO is used
to power the internal processor and provide 5V
externally. This 5V external output can be used to
supply the gate drive. An analog filter between the V
output and the VDR input is recommended when
implementing a 5V gate drive supplied from V

4.7 µF capacitors are recommended with one placed
as close as possible to V
possible to V

, separated by a 10 isolation resistor.

DR

DO NOT exceed 10 µF on the V
is required to implement higher gate drive voltages. By
utilizing Microchip’s TC1240A voltage doubler supplied
from V

to provide VDR, a 10V gate drive can be

DD

achieved. A 4V LDO is used to power the internal
analog circuitry. The two low-side drivers can be used
to operate the power converter in bidirectional mode,
enabling the “shaping” of LED dimming current in LED
applications or developing bidirectional power
converters for battery-powered applications.

The MCP19114 is packaged in a 24-lead 4 mm x 4 mm
QFN. The MCP19115 is packaged in a 28-lead
5 mm x 5 mm QFN.

®

microcontroller similar

DD

and one as close as

DD

. An external supply

DD

®

X

DD

. Two

The ability for system designers to configure
application-specific features allows the MCP19114/5 to
be offered in smaller packages than currently available
in integrated devices today. The General Purpose
Input/Output (GPIO) of the MCP19114/5 can be
configured to offer a status output, a device enable, to
control an external switch, a switching frequency
synchronization output or input or even a device status
or "heartbeat" indicator. This flexibility allows the
MCP19114/5 packages and complete solutions to be
smaller, thereby saving size and cost of the system
printed circuit boards.

With integrated features like output current adjust and
dynamic output voltage positioning, the MCP19114/5
family has the best in class performance and highest
integration level currently available.

Power trains supported by this architecture include but
are not limited to boost, flyback, quasi-resonant
flyback, SEPIC, Ćuk, etc. Two low-side gate drivers are
capable of sinking and sourcing 1A at 10V V

. With a

DR

5V gate drive, the driver is capable of 0.5A sink and
source. The user has the option to allow the V

UVLO

IN

to shut down the drivers by setting the UVLOEN bit.
When this bit is not set, the device drivers will ride
through the UVLO condition and continue to operate
until VDR reaches the gate drive UVLO value. This
value is selectable at 2.7V or 5.4V and is always
enabled. An internal reset for the microcontroller core
is set to 2.0V. An internal comparator module is used to
sense the desaturation of the flyback transformer to
synchronize switching for quasi-resonant applications.
The operating input voltage for normal device operation
ranges from 4.5V to 42V with an absolute maximum of
44V. The maximum transient voltage is 48V for 500 ms.

2

C serial bus is used for device communications

An I
from the PWM controller to the system.

 2014 Microchip Technology Inc. DS20005281A-page 9

VDD(5V)

BGAP

UVLO

V

REF

OV REF

8

8

OV

BGAP

PIC CORE

OSC

OV

UVLO

PDRV

I

SN

A=10

I

P

LEB

2

EA_SC

PWM Comp

PWM Logic

DESAT

N

QRS

V

DR

A

GND

MCLR

DIMI

SDA

TEMP

V

S

BIN

I/O x 3

(x7 MCP19115)

OV

OC

Clamp

6

ccd

4

4

EN1

EN2

OVLO

4

I

FB

P

GND

P

GND

P

GND

V

VDD

V

REF2

MUX to

GPB1

I/O

LDO1
LDO2

Bias Gen

AVDD(4V)

V

AVDD

V

DD

V

REF2

8

DESAT

MUX

4V to 20V

8.8V to 44V

EN

BGAP

DESAT

P

/I

SOUT

I

SP

V

DD_OK

RFB
MUX

BG

5k:

Gate

Drive

Timing

Gate
Drive

Timing

I

P_COMP

A2

A1

OV_REF

V

REF2

V

REF

A2

OVLO_REF

UVLO_REF

L

IN

Interrupt and Logic to

PWM & PIC

L

IN

L

IN

R

FB_INT

AMUX

5V to 10V

4msb

VIN_UVLO

Log

Lin

Slope

Comp

ADJ

Offset

VIN_OVLO

+

-

-

+

OVLO

DMUX

PWM

VZC

VZC

VZC

VZC

V

DR

UVLO

BGAP

2.7V or 5.4V

ADC

4msb

2lsb

2lsb

BGAP

BGAP

CHS1

CHS2

CHS3

CHS4

CHS5

CHS6

CHS8

CHS9

CHS10

See Electrical Characteristics

For Clamp Voltages

V

IN

PDRV

I

P

SDRV

DESAT

N

DESAT

P

I

SN

I

SP

GPIO

GPIO

A

GNDPGND

V

VDD

V

VDD

V

VDD

V

DR

I

COMP

4.5V to 42V

4.7 µF

4.7 µF

10Ω

Place recommended V

VDD

and VDR4.7 µF

Capacitors as close to respective pins as possible

CHS0

V

IN/n

DS20005281A-page 10  2014 Microchip Technology Inc.

FIGURE 1-1: MCP19114/5 FLYBACK SYNCHRONOUS QUASI-RESONANT BLOCK DIAGRAM

MCP19114/5

MCP19114/5

V

IN

V

DR

I

SP

P

GND

V

S

I

P

V

IN

PDRV

BIN

DIMI

DESAT

N

MCLR

CCD

MCP19114

I

COMP

I/O

TEMP SNS

EN

2

SDRV

A

GND

V

DD

I

FB

4x424LdQFN

V

DD

I/O

I/O

I/O

2

V

DD

5V

DESAT

P

I

SN

I/O

TC1240
VOLTAGE
DOUBLER

10V

V

IN

V

DR

I

SP

P

GND

V

S

I

P

V

IN

PDRV

BIN

DIMI

DESAT

N

MCLR

CCD

MCP19114

I

SN

I

COMP

I/O

TEMP SNS

EN

A

GND

V

DD

I

SOUT

I

FB

4x424LdQFN

V

DD

I/O

V

DD

5V

2

SW1

SW2

DESAT

N

DESAT

N

DESAT

P

DESAT

P

DESAT

P

SDRV

SW1

SW2

I/O

I/O

2

FIGURE 1-2: MCP19114 CUK’ SYNCHRONOUS POSITIVE OUTPUT APPLICATION DIAGRAM

FIGURE 1-3: MCP19114 BOOST QUASI-RESONANT APPLICATION DIAGRAM

 2014 Microchip Technology Inc. DS20005281A-page 11

MCP19114/5

Flash

Program
Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr

7

RAM Addr

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

TESTCLKIN

PORTGPA

8

8

8

3

8 Level Stack

256

4K x 14

bytes

(13-bit)

Power-up

Timer

Power-on

Reset

Watchdog

Timer

MCLR

VIN V

SS

Timer0 Timer1

T0CKI

Configuration

8 MHz Internal

Oscillator

Timer2

I2C

GPA0

GPA1

GPA2
GPA3

GPA5

Analog Interface

SDA
SCL

PMDATL

EEADDR

Self read/
write flash
memory

Registers

PORTGPB

GPB0

GPB1

GPB6 (MCP19115)

GPB4 (MCP19115)

PWM

GPB5 (MCP19115)

GPA6
GPA7

GPB7 (MCP19115)

Enhanced

CCD

GPA6 GPB7 (MCP19115)

FIGURE 1-4: MICROCONTROLLER CORE BLOCK DIAGRAM

DS20005281A-page 12  2014 Microchip Technology Inc.

MCP19114/5

2.0 PIN DESCRIPTION

The 24-lead MCP19114 and 28-lead MCP19115
devices feature pins that have multiple functions
associated with each pin. Tab le 2 -1 provides a
description of the different functions. Refer to

Section 2.1 “Detailed Pin Functional Description”

for more detailed information.

TABLE 2-1: MCP19114/5 PINOUT DESCRIPTION

Name Function

Input

Type

GPA0/AN0/TEST_OUT GPA0 TTL CMOS General-purpose I/O

AN0 AN — A/D Channel 0 input

TEST_OUT — — Internal analog/digital signal multiplexer output

GPA1/AN1/CLKPIN GPA1 TTL CMOS General-purpose I/O

AN1 AN — A/D Channel 1 input

CLKPIN ST CMOS Switching frequency clock input or output

GPA2/AN2/T0CKI/INT GPA2 ST CMOS General-purpose I/O

AN2 AN — A/D Channel 2 input

T0CKI ST — Timer0 clock input

INT ST — External interrupt

GPA3/AN3 GPA3 TTL CMOS General-purpose I/O

AN3 AN — A/D Channel 3 input

GPA5/MCLR

GPA5 TTL — General-purpose input only

MCLR

GPA6/CCD/ICSPDAT GPA6 ST CMOS General-purpose I/O

ICSPDAT ST CMOS Serial Programming Data I/O

CCD ST CMOS Single Compare output. Dual Capture input

GPA7/SCL/ICSPCLK GPA7 ST OD General-purpose open drain I/O

SCL I

ICSPCLK ST — Serial Programming Clock

GPB0/SDA GPB0 TTL OD General-purpose I/O

SDA I

GPB1/AN4/VREF2 GPB1 TTL CMOS General-purpose I/O

AN4 AN — A/D Channel 4 input

VREF2 — AN VREF2 DAC Output

GPB4/AN5/ICSPDAT

(MCP19115 Only)

GPB4 TTL CMOS General-purpose I/O

AN5 AN — A/D Channel 5 input

ICSPDAT ST CMOS Primary Serial Programming Data I/O

GPB5/AN6/ICSPCLK

(MCP19115 Only)

GPB5 TTL CMOS General-purpose I/O

AN6 AN — A/D Channel 6 input

ISCPCLK ST — Primary Serial Programming Clock

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the MODECON register.
3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the MODECON

register.

Output

Type

Description

ST — Master Clear with internal pull-up

2

C™ OD I2C clock

2

C™ OD I2C data input/output

(3)

2

C = Schmitt Trigger input with I2C

(1)

(2)

 2014 Microchip Technology Inc. DS20005281A-page 13

MCP19114/5

TABLE 2-1: MCP19114/5 PINOUT DESCRIPTION (CONTINUED)

Name Function

GPB6/AN7

(MCP19115 Only)

GPB7/CCD

(MCP19115 Only)

V

IN

V

DD

V

DR

A

GND

P

GND

GPB6 TTL CMOS General-purpose I/O

AN7 AN — A/D Channel 7 input

GPB7 TTL CMOS General-purpose I/O

CCD ST CMOS Single Compare output. Dual Capture input.

V

IN

V

DD

V

DR

A

GND

P

GND

Input
Type

PDRV PDRV — — Primary Low-Side MOSFET gate drive

SDRV SDRV — — Secondary Low-Side MOSFET gate drive

I

P

I

SN

I

SP

V

S

I

FB

I

COMP

DESATP/I

DESAT

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

SOUT

N

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I

I

P

I

SN

I

SP

V

S

I

FB

I

COMP

DESATP/I

DESAT

SOUT

N

Note 1: The Analog/Digital Debug Output is selected through the control of the ABECON register.

2: Selected when functioning as master or slave by proper configuration of the MSC<1:0> bits in the MODECON register.
3: VREF2 output selected when configured as master by proper configuration of the MSC<1:0> bits in the MODECON

register.

Output

Type

Description

— — Device input supply voltage

— — Internal +5V LDO output pin

— — Gate drive supply voltage

— — Small signal quiet ground

— — Large signal power ground

— — Primary input current sense

— — Secondary current sense amplifier negative input

— — Secondary current sense amplifier positive input

— — Sense voltage compared to overvoltage DAC

— — Error amplifier feedback input

— — Error amplifier output

— — DESATP: DESAT detect comparator positive input

: Secondary current sense amplifier output

I

SOUT

— — DESATN: DESAT detect comparator negative

input

2

C = Schmitt Trigger input with I2C

DS20005281A-page 14  2014 Microchip Technology Inc.

MCP19114/5

2.1 Detailed Pin Functional Description

2.1.1 GPA0 PIN

GPA0 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.

AN0 is an input to the A/D. To configure this pin to be
read by the A/D on channel 0, bits TRISA0 and ANSA0
must be set.

The ABECON register can be configured to set this pin
to the TEST_OUT function. It is a buffered output of the
internal analog or digital signal multiplexers. Analog
signals present on this pin are controlled by the
ADCON0 register. Digital signals present on this pin
are controlled by the ABECON register.

2.1.2 GPA1 PIN

GPA1 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.

AN1 is an input to the A/D. To configure this pin to be
read by the A/D on channel 1, bits TRISA1 and ANSA1
must be set.

When the MCP19114/5 are configured as a MASTER
or SLAVE, this pin is configured to be the switching
frequency synchronization input or output (CLKPIN).

2.1.3 GPA2 PIN

GPA2 is a general-purpose ST input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.

AN2 is an input to the A/D. To configure this pin to be
read by the A/D on channel 2, bits TRISA2 and ANSA2
must be set.

When bit T0CS is set in the OPTION_REG register, the

T0CKI function is enabled. Refer to Section 22.0

“Timer0 Module” for more information.

GPA2 can also be configured as an external interrupt

by setting the INTE bit. Refer to Section 14.2

“GPA2/INT Interrupt” for more information.

2.1.5 GPA5 PIN

GPA5 is a general-purpose TTL input only pin. An
internal weak pull-up and interrupt-on-change are also
available.

For programming purposes, this pin is to be connected
to the MCLR

Section 30.0 “In-Circuit Serial Programming™
(ICSP™)” for more information.

This pin is MCLR
CONFIG register.

pin of the serial programmer. Refer to

when the MCLRE bit is set in the

2.1.6 GPA6 PIN

GPA6 is a general-purpose CMOS output ST input pin
whose data direction is controlled in TRISGPA.

ICSPDAT is a serial programming data I/O function.
This can be used in conjunction with ICSPCLK to serial
program the device.

GPA6 is part of the CCD Module. For more information,

refer to Section 26.0 “Dual Capture/Compare (CCD)

Module”.

2.1.7 GPA7 PIN

GPA7 is a true open drain general-purpose pin whose
data direction is controlled in TRISGPA. There is no
internal connection between this pin and device VDD.
This pin does not have a weak pull-up, but inter­rupt-on-change is available.

This pin is the primary ICSPCLK input. For MCP19115,
this pin is ALT1_ICSPCLK. This can be used in
conjunction with ICSPDAT to serial program the
device.

When the MCP19114/5 is configured for I

communication, Section 28.2 “I

GPA7 functions as the I
be configured as an input to allow proper operation.

2

2

C Mode Overview ”,

C clock (SCL). This pin must

2

C

2.1.4 GPA3 PIN

GPA3 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPA. An
internal weak pull-up and interrupt-on-change are also
available.

AN3 is an input to the A/D. To configure this pin to be
read by the A/D on channel 3, bits TRISA3 and ANSA3
must be set.

 2014 Microchip Technology Inc. DS20005281A-page 15

MCP19114/5

2.1.8 GPB0 PIN

GPB0 is a true open drain general-purpose pin whose
data direction is controlled in TRISGPB. There is no
internal connection between this pin and device V
This pin does not have a weak pull-up, but
interrupt-on-change is available. When the
MCP19114/5 are configured for I

Section 28.2 “I

2

as the I
an input to allow proper operation.

2

C Mode Overvi ew”, GPB0 functions

C clock (SDA). This pin must be configured as

2

C communication,

DD

2.1.9 GPB1 PIN

GPB1 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.

AN4 is an input to the A/D. To configure this pin to be
read by the A/D on channel 4, bits TRISB1 and ANSB1
must be set.

When the MCP19114/5 are configured as a MASTER,
this pin is configured to be the V

DAC output.

REF2

2.1.10 GPB4 PIN (MCP19115 ONLY)

GPB4 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.

AN5 is an input to the A/D. To configure this pin to be
read by the A/D on channel 5, bits TRISB4 and ANSB4
must be set.

ICSPDAT is the primary serial programming data I/O
function. This is used in conjunction with ICSPCLK to
serial program the device.

2.1.11 GPB5 PIN (MCP19115 ONLY)

GPB5 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.

AN6 is an input to the A/D. To configure this pin to be
read by the A/D on channel 6, bits TRISB5 and ANSB5
must be set.

ICSPCLK is the primary serial programming clock
function. This is used in conjunction with ICSPDAT to
serial program the device.

2.1.12 GPB6 PIN (MCP19115 ONLY)

GPB6 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An
internal weak pull-up and interrupt-on-change are also
available.

AN7 is an input to the A/D. To configure this pin to be
read by the A/D on channel 7, bits TRISB6 and ANSB6
must be set.

2.1.13 GPB7 PIN (MCP19115 ONLY)

GPB7 is a general-purpose TTL input or CMOS output
pin whose data direction is controlled in TRISGPB. An

.

internal weak pull-up and interrupt-on-change are also
available.

GPB7 is part of the CCD Module. For more information,

refer to Section 26.0 “Dual Capture/Compare (CCD)

Module”.

2.1.14 DESATN PIN

Internal comparator inverting input. Used during
quasi-resonant operation for desaturation detection.

2.1.15 DESATP/I

When using the internal comparator for desaturation
detection during quasi-resonant operation, this pin
connects to the comparator’s non-inverting input. The
output of the remote sense current sense amplifier gets
configured to utilize the 5 k internal feedback resistor.
When not utilizing the internal comparator and not
configured to use the 5 k internal feedback resistor,
the current sense amplifier gets connected to this pin

SOUT

.

and is I

SOUT

PIN

2.1.16 ISP PIN

The non-inverting input to internal current sense
amplifier, typically used to differentially remote sense
secondary current. This pin can be internally pulled-up

by setting the <ISPUEN> bit in the PE1 register.

to V

DD

2.1.17 ISN PIN

The inverting input to internal current sense amplifier,
typically used to differentially remote sense secondary
current.

2.1.18 IP PIN

Primary input current sense for current mode control
and peak current limit. For voltage mode control, this
pin can be connected to an artificial ramp.

2.1.19 A

A

is the small signal ground connection pin. This

GND

pin should be connected to the exposed pad on the
bottom of the package.

2.1.20 P

Connect all large signal level ground returns to P
These large-signal level ground traces should have a
small loop area and minimal length to prevent coupling
of switching noise to sensitive traces.

GND

GND

PIN

PIN

GND

.

DS20005281A-page 16  2014 Microchip Technology Inc.

2.1.21 SDRV PIN

The gate of the low-side secondary MOSFET is
connected to SDRV. The PCB trace connecting SDRV
to the gate must be of minimal length and appropriate
width to handle the high peak drive current and fast
voltage transitions.

2.1.22 PDRV PIN

The gate of the low-side primary MOSFET is
connected to PDRV. The PCB tracing connecting
PDRV to the gate must be of minimal length and
appropriate width to handle the high-peak drive
currents and fast voltage transitions.

2.1.23 VDR PIN

The supply for the low-side drivers is connected to this
pin and has an absolute maximum rating of +13.5V.
This pin can be connected by an RC filter to the V
pin.

DD

2.1.24 VDD PIN

The output of the internal +5.0V regulator is connected
to this pin. It is recommended that a 1.0 µF bypass
capacitor be connected between this pin and the GND
pin of the device. The bypass capacitor should be
physically placed close to the device.

MCP19114/5

2.1.25 VIN PIN

Input power connection pin of the device. It is
recommended that capacitance be placed between this
pin and the GND pin of the device.

2.1.26 VS PIN

Analog input connected to the non-inverting input of the
overvoltage comparator. Typically used as output
voltage overvoltage protection. The inverting input of
the overvoltage comparator is controlled by the OV
REF DAC.

2.1.27 IFB PIN

Error amplifier inverting feedback connection.

2.1.28 I

Error amplifier output signal.

COMP

PIN

2.1.29 EXPOSED PAD (EP)

It is recommended to connect the exposed pad to

.

A

GND

 2014 Microchip Technology Inc. DS20005281A-page 17

MCP19114/5

NOTES:

DS20005281A-page 18  2014 Microchip Technology Inc.

3.0 FUNCTIONAL DESCRIPTION

MCP19114/5

3.1 Linear Regulators

The operating input voltage for the MCP19114/5
ranges from 4.5V to 42V. There are two internal Low
Dropout (LDO) voltage regulators. A 5V LDO is used to
power the internal processor and provide a 5V output
for external usage. A second LDO (V
regulator and is used to power the remaining analog
internal circuitry. Using an LDO to power the
MCP19114/5, the input voltage is monitored using a
resistor divider. The MCP19114/5 also incorporate

brown-out protection. Refer to Section 13.3

“Brown-out Reset (BOR)” for details. The PIC core

will reset at 2.0V V

DD

.

AVD D

) is a 4V

3.2 Output Drive Circuitry

The MCP19114/5 integrate two low-side drivers used
to drive the external low-side N-Channel power
MOSFETs for synchronous applications, such as
synchronous flyback and synchronous Ćuk converters.
Both converter types can be configured for
non-synchronous control by replacing the synchronous
FET with a diode. The flyback is also capable of
quasi-resonant operation. The MCP19114/5 can also
be configured as a Boost or SEPIC switch-mode power
supply (SMPS). In Boost mode, non-synchronous
fixed-frequency or non-synchronous quasi-resonant
control can be utilized. This device can also be used as
a SEPIC SMPS in fixed-frequency non-synchronous
mode. The low-side drive is capable of switching the
MOSFET at high frequency in typical SMPS
applications. The gate drive (V
5V to 10V. The drive strength is capable of up to 1A
sink/source with 10V gate drive and down to 0.5A
sink/source with 5V gate drive. A programmable delay
is used to set the gate turn-on dead time. This prevents
overlap and shoot-through currents that can decrease
the converter efficiency. Each driver shall have its own
EN input controlled by the microcontroller core.

) can be supplied from

DR

3.3 Current Sense

The output current is differentially sensed by the
MCP19114/5. In low-current applications, this helps
maintain high system efficiency by minimizing power
dissipation in current sense resistors. Differential
current sensing also minimizes external ground shift
errors. The internal differential amplifier has a precision
gain of 10V/V.

3.4 Peak Current Mode

The MCP19114/5 is a peak current mode controlled
device with the current sensing element in series with
the primary side MOSFET. Programmable Leading
Edge Blanking can be implemented to blank current
spikes resulting from turn on. The blank time is
controlled from the ICLEBCON register.

Primary Input Current Offset Adjust is also available via
user programmability, thus limiting peak primary input
current. This offset adjustment is controlled by the
ICOACON register.

3.5 Magnetic Desaturation Detection

An internal comparator module is used to detect power
train magnetic desaturation for quasi-resonant
applications. The comparator output is used as a signal
to synchronize the start of the next switching cycle.
This operation differs from the traditional
fixed-frequency application. The DESAT comparator
output can be enabled and routed into the PWM
circuitry or disabled for fixed-frequency applications.
During Quasi-Resonant (QR) operation, the DESAT
comparator output is enabled and combined with a pair
of one-shot timers and a flip-flop to sustain PWM
operation. Timer2 (TMR2) must be initialized and set to
run at a frequency lower than the minimum QR
operating frequency. When the CDSWDE bit is set in
the DESATCON register, TMR2 serves as a watchdog.

An example of the order of events for a Flyback SMPS
in synchronous QR operation is as follows:

The primary gate drive (PDRV) goes high. The output
of the DESAT comparator is high. The primary current
increases until I
and causes PWM comparator output to go low. The
PDRV goes low and the secondary gate drive (SDRV)
goes high (after programmed dead time). This triggers
the first one-shot to send a 200 ns pulse that resets the
flip-flop and TMR2 (WDM_RESET). The 200 ns
one-shot pulse design is implemented to mask out any
spurious transitions at the DESAT comparator output
caused by switching noise. The SDRV stays high until
the secondary winding completely runs out of energy,
at which time the output capacitance begins to source
current back through the winding and secondary
MOSFET. The DESAT comparator detects this and its
output goes low. This sets the flip-flop and triggers the
second one-shot to send a 33 ns pulse to the control
logic, causing the SDRV to go low and the PDRV to go
high (after programmed dead time). The cycle then
repeats. If, for any reason, the reset one-shot does not
fire, the WDM_RESET signal stays low and TMR2 is
allowed to run until the PWM signal kicks off a new
cycle.

The desaturation comparator module is controlled by
the DESATCON register.

reaches the level of the Error Amp

P

 2014 Microchip Technology Inc. DS20005281A-page 19

MCP19114/5

3.6 Start-up

To control the output current during start-up, the
MCP19114/5 have the capability to monotonically
increase system current, at the user’s discretion. This
is accomplished through the control of the reference
voltage DAC (V
user control via software.

). The entire start-up profile is under

REF

3.7 Driver Control Circuitry

The internal driver control circuitry of the MCP19114/5
is comprised of an error amplifier (EA), a high-speed
comparator and a latch similar to the MCP1631.

The error amplifier generates the control voltage used
by the high-speed PWM comparator. There is an
internally generated reference voltage, V
difference or error between this internal reference
voltage and the actual feedback voltage is the control
voltage. Some applications will implement parked
times where the gate drives are not active. For
example, when changing between LED strings and
after voltage repositioning, the user can disable the
gate drives and park the error amplifier output low.
During the time when the EA is parked, its output will be
clamped low (1 * BG) such that it is in a known state
when reactivated. Before the output switches are
re-enabled, it may be necessary to re-enable the EA
some time prior to enabling the output drivers. This
prior-EA enable time will allow the EA to slew towards
the intended target and prevent the secondary switch
from turning on for an extensive period of time,
unintentionally discharging the output capacitance and
pulling the output voltage down. External
compensation is used to stabilize the control system.

Since the MCP19114/5 are peak current mode
controlled, the comparator compares the primary peak
current waveform (I
flowing in the primary side with the error amplifier
control output voltage. This error amplifier control
output voltage also has user-programmable slope
compensation subtracted from it. In fixed-frequency
applications, the slope compensation signal is
generated to be greater than 1/2 the down slope of the
inductor current waveform and is controlled by the
SLPCRCON register. Offset adjust ability is also
available to set the peak current limit of the primary
switch for overcurrent protection. The range of the
slope compensation ramp is specified. When the
current sense signal reaches the level of the control
voltage minus slope compensation, the on cycle is
terminated and the external switch is latched off until
the beginning of the next cycle which begins at the next
clock cycle.

To improve current regulation at low levels, a pedestal
voltage (VZC) set to the BG (1.23V) is implemented.
This virtual ground serves as the reference for the error
amplifier (A1), slope compensation, current sense
amplifier (A2) and the I

) that is based upon the current

P

offset adjustment.

P

REF

. The

An S-R latch (Set-Rest-Flip-Flop) is used to prevent the
PWM circuitry from turning the external switch on until
the beginning of the next clock cycle.

3.8 Fixed PWM Frequency

The switching frequency of the MCP19114/5 while not
controlled by the DESAT comparator output is
generated by using a single edge of the 8 MHz internal
clock. The user sets the MCP19114/5 switching
frequency by configuring the PR2 register. The
maximum allowable PDRV duty cycle is adjustable and
is controlled by the PWMRL register. The
programmable range of the switching frequency will be

31.25 kHz to 2 MHz. The available switching frequency
below 2 MHz is defined as F
a whole number between 4  N  256. Refer to

Section 25.0 “Enhanced PWM Module” for details.

3.9 V

This reference is used to generate the voltage
connected to the non-inverting input of the error
amplifier. The entire analog control loop is raised to a
virtual ground pedestal equal to the Band Gap voltage
(1.23V).

REF

= 8 MHz/N, where N is

SW

3.10 OV REF

This reference is used to set the output overvoltage set
point. It is compared to the V
typically proportional to the output voltage based on a
resistor divider. OV protection, when enabled, can be
set to a value for the protection of system circuitry or it
can be used to “ripple” regulate the converter output
voltage for repositioning purposes. For details, refer to

Register 6-4.

input pin, which is

S

3.11 Independent Gate Drive with Programmable Delay

Two independent low-side gate drives are integrated
for synchronous applications. Programmable delay has
been implemented to improve efficiency and prevent
shoot-through currents. Each gate drive has an
independent enable input controlled by the PE1
register and programmable dead time controlled by the
DEADCON register.

DS20005281A-page 20  2014 Microchip Technology Inc.

3.12 Temperature Management

3.12.1 THERMAL SHUTDOWN

To protect the MCP19114/5 from overtemperature
conditions, a 150°C junction temperature thermal
shutdown has been implemented. When the junction
temperature reaches this limit, the device disables the
output drivers. In Shutdown mode, both PDRV and
SDRV outputs are disabled and the overtemperature
flag (OTIF) is set in the PIR2 register. When the
junction temperature is reduced by 20°C to 130°C, the
MCP19114/5 can resume normal output drive
switching.

3.12.2 TEMPERATURE REPORTING

The MCP19114/5 have a second on-chip temperature
monitoring circuit that can be read by the ADC through

the analog test MUX. Refer to Section 20.0 “In ternal

Temperature Indicator Module” for details on this

internal temperature monitoring circuit.

MCP19114/5

 2014 Microchip Technology Inc. DS20005281A-page 21

MCP19114/5

4.0 ELECTRICAL CHARACTERISTICS

4.1 ABSOLUTE MAXIMUM RATINGS †

VIN-V

(transient < 500 ms)............................................................................................................................................+48V

V

IN

PDRV ..................................................................................................................................(GND - 0.3V) to (V

SDRV ....................................................................... ..........................................................(GND - 0.3V) to (V

V

DD

V

DR

Voltage on MCLR

Maximum voltage: any other pin .................................. ...................................................+(V

(operating) .................................................................................................................................................-0.3V to +44V

GND

+0.3V)

DR

+0.3V)

DR

Internally Generated ......................................... ...............................................................................................+6.5V

Externally Generated........................................ .............................................................................................+13.5V

with respect to GND.................... ...............................................................................-0.3V to +13.5V

- 0.3V) to (VDD+0.3V)

GND

Maximum output current sunk by any single I/O pin .... ..........................................................................................25 mA

Maximum output current sourced by any single I/O pin ..........................................................................................25 mA

Maximum current sunk by all GPIO.............................. ..........................................................................................90 mA

Maximum current sourced by all GPIO ........................ ..........................................................................................35 mA

Storage Temperature.................................................... ..........................................................................-65°C to +150°C

Maximum Junction Temperature .................................. ........................................................................................+150°C

Operating Junction Temperature.................................. ..........................................................................-40°C to +125°C

ESD protection on all pins (HBM)................................. ......................................................................................... 2.0 kV

ESD protection on all pins (MM)................................... ........................................................................................... 200V

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

4.2 Electrical Characteristics

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

Input

Input Voltage V

Input Quiescent

IN

I

Q

4.5 — 42 V
—510 mA Not Switching, +V

Current

Shutdown Current

Linear Regulator V

Internal Circuitry

DD

I

SHDN

V

DD

—30150 µA V

4.75 5.0 5.5 VV

Bias Voltage

Maximum External
V

Output Current

DD

Line Regulation V

Load Regulation V

Output Short Circuit

(V

DD-OUT

I

DD_OUT

DD-OUT

DD-OUT

V

DD-OUT

I

DD_SC

/

* VIN)

/

35 ——mAV

-0.1 0.002 0.1 %/V (V

-0.65 0.1 +0.65 %I

—50—mAV

Current

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

A

and VDD.

IN

=+25°C, Boldface specifications

=5V

SEN

= 12V

IN

Note 1

= 6.0V to 42V

IN

= 6.0V to 42V,

IN

Note 3

+1.0V) VIN 20V

DD

Note 3

DD_OUT

= 1 mA to 20 mA

Note 3

=(VDD+1.0V)

IN

Note 3

DS20005281A-page 22  2014 Microchip Technology Inc.

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

Dropout Voltage VIN-V

Power Supply

PSRR

DD

LDO

—0.30.5 VI

—60—dBf 1000 Hz,

Rejection Ratio

Linear Regulator V

Internal Analog

AVDD

V

AVD D

—4.0—V

Supply Voltage

Band Gap Voltage BG — 1.23 — V Trimmed at 1.0% tolerance

Band Gap

BG

TOL

-2.5 — +2.5 %

To le r a nc e

Input UVLO Voltage

UVLO Range UVLO

UVLO

ON

Trip

UVLO

ON

TOL

4.0 — 20 VV

-14 — 14 %V

To le r a nc e

UVLO Hysteresis UVLO

HYS

— 4 — % Hysteresis is based upon

Resolution nbits — 6 — Bits Logarithmic Steps

UVLO Comparator

Input-to-Output

TD — 5 — µs 100 ns rise time to 1V

Delay

Input OVLO Voltage

OVLO Range OVLO

OVLO

ON

Trip

OVLO

ON

TOL

8.8 — 44 VV

-14 — 14 %V

To le r a nc e

OVLO Hysteresis OVLO

HYS

— 5 — % Hysteresis is based upon the

Resolution nbits — 6 — Bits Logarithmic Steps

OVLO Comparator

Input-to-Output

TD — 5 — µs 100 ns rise time to 1V

Delay

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

A

and VDD.

IN

=+25°C, Boldface specifications

DD_OUT

=20mA,

Note 3, Note 4

I

DD_OUT

C

=25mA

=0µF, CDD=1µF

IN

Falling

IN

Falling

IN

UVLO trip set to 9V
VINUVLO = 0x21h

the UVLO

ON

setting
UVLO trip set to 9V
VINUVLO = 0x21h

overdrive on V

IN

VIN> UVLO to flag set

Rising

IN

Rising

IN

OVLO trip set to 18V
VINOVLO = 0x1Fh

OVLO

ON

setting
OVLO trip set to 18V
VINOVLO = 0x1Fh

overdrive on V

IN

VIN> OVLO to flag set

 2014 Microchip Technology Inc. DS20005281A-page 23

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

Output OV DAC

Resolution nbits — 8 — Bits Linear DAC

Full Scale Range FSR 0 — 2 * BG V

To le r a nc e O VR E F

TOL

-10 — +10 % Full Scale, Code = 0xFF

Output OV Comparator

OV Hysteresis OV

Input Bias Current I

Common-Mode

V

HYS

BIAS

CMR

—50—mV

—±1—µA

0—3.0VNote 2

Input Voltage Range

Input-to-Output

TD — 200 — ns Note 2

Delay

V oltage Reference DAC (V

REF

)

Resolution nbits — 8 — V/V Linear DAC

Full Scale Range FSR BG — 2 * BG V Pedestal set to BG

V oltage Reference DAC (V

REF2

)

Resolution nbits — 8 — Bits Linear DAC

Full Scale Range FSR 0 — BG V

Sink Current I

Source Current I

SINK

SOURCE

To le r a nc e VR E F2

TOL

-3 ——mAV

3 ——mAV

-10 — +10 % Full Scale, Code = 0xFF

Current Sense Amplifier (A2)

Amplifier PSRR PSRR — 65 — dB V

Closed Loop

A2

VCL

—10—V/VR

Voltage Gain

Low-Level Output V

Gain Bandwidth

GBWP — 10 — MHz V

OL

—500—mVR

Product

Input Impedance R

Sink Current I

Source Current I

SOURCE

IN

SINK

—10—k

-3 ——mAI

3 ——mAI

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

A

and VDD.

IN

=+25°C, Boldface specifications

100 ns rise time to 1V
overdrive on V

S

VS> OV to flag set

=0V,

REF2

=300to BG

R

L

=BG,

REF2

R

=300to GND

L

=2*BG

CM

=5k to 2.048V,

L

100 mV < A2 <

– 100 mV, VCM=BG

V

AVD D

=5k to 2.048V

L

=4V

AVD D

SP=ISN

R

L

SP=ISN

R

L

=GND

=300 to 2 * BG

=GND

=300 to GND

DS20005281A-page 24  2014 Microchip Technology Inc.

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

Common Mode

V

CMR

GND – 0.3 — VBG+0.3 V Note 2

Range

Common Mode

CMRR — 70 — dB

Rejection Ratio

Internal Feedback

R

FB_INT

—5—k

Resistor

Internal Feedback

R

FB_INT_TOL

—2—%Trimmed

Resistor Tol

Pedestal Voltage

Pedestal Voltage

VZC — BG — V

Level

Error Amplifier (EA)

Input Offset Voltage V

Common Mode

CMRR — 65 — dB V

OS

—2—mV

Rejection Ratio

Open-Loop Voltage

A

VOL

—70—dBNote 2

Gain

Low-level Clamp

V

OL

BG - 0.35 BG - 0.22 BG - 0.1 VRL=5k to 2.048V

value

Gain Bandwidth

GBWP — 3.5 — MHz

Product

Error Amplifier Sink

I

SINK

-3 ——mAV

Current

Error Amplifier

I

SOURCE

3 ——mAV

Source
Current

Maximum Error

V

EA_MAX

— 2 * BG — V EA Output clamped to
Amplifier
Output High-Level
Clamp

Peak Current Sense Input

Maximum Primary

V

IP_MAX

—BG1.5VNote 2
Current Sense
Signal Voltage

PWM Comparator

Input-to-Output

TD — 20 — ns Note 2

Delay

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

A

and VDD.

IN

=+25°C, Boldface specifications

= 0V to BG

CM

=BG, IFB=I

REF

RL=150 to 1.5 * BG

=2*BG, IFB=I

REF

RL=150 to 1.5 * BG

2*BG Voltage

COMP

COMP

 2014 Microchip Technology Inc. DS20005281A-page 25

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

Peak Current Leading Edge Blanking

Resolution LEB — 2 — Bits

Blanking Time

LEB

RANGE

0 — 256 ns 4-Step Programmable Range

Adjustable Range

Offset Adjustment (IP Sense)

Resolution OS

Offset Adjustment

OS

ADJ_RANGE

ADJ

—4—Bits

0—750mV

Range

Offset Adjustment

OS

ADJ_STEP

— 50 — mV Linear Steps

Step Size

Adjustable Slope Compens ation

Resolution SC

RES

— 6 — Bits Log Steps

Slope m 4.1 — 432.5 mV/µs

Slope Step Size SC

Ramp Set Point

m

STEP

TOL

— 8 — % Log Steps

—±1±30%

To le ra nc e

Desaturation Detection Compa r ator

Input Offset Voltage V

Input Bias Current I

Common-Mode

V

OS

BIAS

CMR

— ±1 — mV Trimmed, 5 bits adjustable

— ±1 — µA Internal Circuit Dependent

GND – 0.3V — 2.7 V Note 2

Input Voltage Range

Input-to-Output

TD — 20 — ns

Delay

VDR UVLO

UVLO

V

DR

(2.7V V

UVLO

V

DR

(2.7 V

V

UVLO

DR

DR

Rising)

DR

Falling)

V

DR_UVLO_2.7_F

V

DR_UVLO_2.7_R

V

DR_UVLO 2.7 HYS

2.45 — 2.9 V

2.68 — 3.23 V

190 — 415 mV

(2.7V) Hysteresis

V

UVLO

DR

(5.4V V

UVLO

V

DR

(5.4V V

V

UVLO

DR

Falling)

DR

Rising)

DR

V

DR_UVLO_5.4_F

V

DR_UVLO_5.4_R

V

DR_UVLO 5.4 HYS

4.7 — 5.96 V

5.15 — 6.56 V

380 — 830 mV

(5.4V) Hysteresis

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

A

and VDD.

IN

=+25°C, Boldface specifications

(0, 50,100, and 200 ns)

Note 2

DS20005281A-page 26  2014 Microchip Technology Inc.

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

Output Driver (PDRV and SDRV)

PDRV/SDRV Gate

R

DR-SRC

——13.5  V

Drive Source
Resistance

PDRV/SDRV Gate

R

DR-SINK

——12  V

Drive Sink
Resistance

PDRV/SDRV Gate
Drive Source

I

DR-SRC

—0.5—AV

—1.0—
Current

PDRV/SDRV Gate
Drive Sink Current

I

DR-SINK

—0.5—AV

—1.0—

Dead Time Adjustment

Resolution DT

Dead Time

DT

RES

RANGE

—4—Bits

16 — 256 ns
Adjustable Range

Dead Time Step

DT

STEP

— 16 — ns Linear Steps
Size

Dead Time

DT

TOL

—±8—ns
To le r a nc e

Oscillator/PWM

Internal Oscillator

F

OSC

7.60 8.00 8.40 MHz

Frequency

Switching

F

SW

—F
Frequency

Switching

N4—255—F
Frequency Range
Select

A/D Converter (ADC) Characteristics

Resolution N

Integral Error E

Differential Error E

Offset Error E

Gain Error E

Reference Voltage V

REF_ADC

Full-Scale Range FSR

R

IL

DL

OFF

GN

A/D

——10Bits

——±1LSbV

— — ±1 LSb No missing code in 10 bits,

— +3.0 +5.0 LSb V

—±2±5LSbV

—V

GND — V

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

/N — MHz

OSC

AVD D

—V

AVD D

A

—

and VDD.

IN

=+25°C, Boldface specifications

=4.5V

DR

Note 2

=4.5V

DR

Note 2

=5V

DR

=10V

V

DR

Note 2

=5V

DR

=10V

V

DR

Note 2

=2MHz

MAX

REF_ADC=VAVD D

V

REF_ADC=VAVD D

REF_ADC=VAVD D

REF_ADC=VAVD D

 2014 Microchip Technology Inc. DS20005281A-page 27

MCP19114/5

4.2 Electrical Characteristics (Continued)

Electrical Specifications: Unless otherwise noted, V

apply over the T

range of -40°C to +125°C

A

Parameters Sym. Min. Typ. Max. Units Conditions

GPIO Pins

Maximum GPIO

I

SINK_GPIO

——90mANote 5

Sink Current

Maximum GPIO

I

SOURCE_GPIO

——35mANote 5

Source Current

GPIO Weak Pull-up

I

PULL-UP_GPIO

50 250 400 µA

Current

GPIO Input Low

V

GPIO_IL

GND — 0.8 V I/O Port with TTL buffer,

Voltage

GND — 0.2V

GND —

GPIO Input High

V

GPIO_IH

2.0 — V

Voltage

0.8V

0.8V

GPIO Output Low

V

GPIO_OL

——0.12V

Voltage

GPIO Output High

V

GPIO_OH

VDD-0.7 — — V IOH=2.5mA, VDD=5V

Voltage

GPIO Input

GPIO_I

IL

—±0.1±1 µA Negative current is defined

Leakage Current

Thermal Shutdown

Thermal Shutdown T

Thermal Shutdown

T

SHD_HYS

SHD

—150—°C

—20—°C

Hysteresis

Note 1: Refer to Section 15.0 “Power-Down Mode (Sleep)”.

2: Ensured by design, not production tested.
3: V

is the voltage present at the VDD pin.

DD

4: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2%

below its nominal value measured at a 1V differential between V

5: The V

LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a

DD

maximum of 15 mA.

= 12V, FSW=150kHz, T

IN

DD

DD

— V

— V

0.2V

DD

DD

DD

DD

DD

DD

and VDD.

IN

=+25°C, Boldface specifications

A

=5V

V

DD

V I/O Port with Schmitt

Trigger buffer, V

VMCLR

V I/O Port with TTL buffer,

=5V

V

DD

V I/O Port with Schmitt

Trigger buffer, V

VMCLR

VIOL=7mA, VDD=5V

as current sourced by the
pin.

DD

DD

=5V

=5V

4.3 Thermal Specifications

Parameters Sym. Min. Typ. Max. Units

Temperature Ranges

Specified Temperature Range T

Operating Junction Temperature Range T

Maximum Junction Temperature T

Storage Temperature Range T

A

J

J

A

Thermal Package Resistances

Thermal Resistance, 24L-QFN 4x4 
Thermal Resistance, 28L-QFN 5x5 

DS20005281A-page 28  2014 Microchip Technology Inc.

JA

JA

-40 — +125 °C

-40 — +125 °C

——+150°C

-65 — +150 °C

—42—°C/W

— 35.3 — °C/W

5.0 DIGITAL ELECTRICAL CHARACTERISTICS

5.1 Timing Parameter Symbology

The timing parameter symbols have been created with
one of the following formats:

MCP19114/5

1. TppS2ppS

2. TppS

T

F Frequency T Time
Lowercase letters (pp) and their meanings:

pp

cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port wr WR
mc MCLR
Uppercase letters and their meanings:

S

FFall PPeriod
HHigh RRise
I Invalid (high-impedance) V Valid
L Low Z High-impedance

2

I

C only

AA output access High High
BUF Bus free Low Low

T

(I2C specifications only)

CC:ST

CC

HD Hold SU Setup

ST

DAT DATA input hold STO STOP condition
STA START condition

3. T

4. Ts (I

(I2C specifications only)

CC:ST

2

C specifications only)

 2014 Microchip Technology Inc. DS20005281A-page 29

MCP19114/5

VDD/2

C

L

R

L

Pin Pin

V

SS

V

SS

C

L

RL=464

C

L

= 50 pF for all GPIO pins

Load Condition 1 Load Condition 2

OSC

Q4 Q1 Q2 Q3 Q4 Q1

1

2

FIGURE 5-1: LOAD CONDITIONS

5.2 AC Characteristics: MCP19114 (Industrial, Extended)

FIGURE 5-2: EXTERNAL CLOCK TIMING

TABLE 5-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

No.

1T

2TCYInstruction Cycle Time

Note 1: Instruction cycle period (T

DS20005281A-page 30  2014 Microchip Technology Inc.

Sym. Characteristic Min. Typ.†Max. Units Conditions

F

OSC

OSC

Oscillator Frequency

Oscillator Period

(1)

(1)

(1)

—8 —MHz

— 250 — ns

—TCY ns TCY = 4*T

OSC

* These parameters are characterized but not tested.
† Data in “Typ.” column is at V

=12V (VDD= 5V), 25°C unless otherwise stated. These parameters are for

IN

design guidance only and are not tested.

) equals four times the input oscillator time base period. All specified values

CY

are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code.