Datasheet MCP19035 Datasheet

MCP19035

MCP19035

3x3 DFN*

COMP

FB

V

IN

PHASE

BOOT

1

2

3

4

10

9

8

7

LDRV

HDRVSHDN

* Includes Exposed Thermal Pad (EP); see Ta b l e 3 - 1.

EP

11

6

PWRGD

+V

CC

5

High-Speed Synchronous Buck Controller

Features:

• Input Voltage Range: from 4.5V to 30V

• Targeted for Low-Voltage Power Trains with
Output Current up to 20A

• High-Speed Voltage Mode, Analog Pulse-Width
Modulation Control

• Power Good Output

• Internal Oscillator, Reference Voltage and
Overcurrent Limit Threshold for Stand-Alone
Applications.

• Multiple Switching Frequency Options (F

- 300 kHz

-600kHz

• Integrated Synchronous MOSFET Drivers

• Multiple Dead-Time Options

• Internal Blocking Device for Bootstrap Circuit

• Integrated Current Sense Capability for Short
Circuit Protection

• Internal Overtemperature Protection

• Under Voltage Lockout (UVLO)

• Integrated Linear Voltage Regulator

• 10-LD 3X3mm DFN Package

SW

):

General Description

The MCP19035 is an application-optimized, high­speed synchronous buck controller that operates from
input voltage sources up to 30V. This controller
implements a voltage-mode control architecture with a
fixed switching frequency of 300 kHz or 600 kHz. The
high-switching frequency facilitates the use of smaller
passive components, including the inductor and
input/output capacitors, allowing a compact, high­performance power supply solution. The MCP19035
implements an adaptive anti-cross conduction scheme
to prevent shoot-through in the external power
MOSFETs. Furthermore, the MCP19035 offers multiple
dead-time options, enabling an additional degree of
optimization, allowing a higher efficiency power supply
design.

The MCP19035 controller is intended to be used for
applications providing up to 20A of output currents
across a wide input voltage range, up to 30V.

The SHDN
While turned off, the current consumption is minimized.

The MCP19035 offers a Power Good feature
(PWRGD), enabling fault detection and simplifying
sequencing.

input is used to turn the device on and off.

Applications:

• Point of Loads

• Set-Top Boxes

• DSL Cable Modems

• FPGA’s/DSP’s Power Supply

• PC’s Graphic/Audio Cards

 2012-2013 Microchip Technology Inc. DS22326B-page 1

Package Types

MCP19035

C

IN

C

OUT

L

Q

1

Q

2

MCP19035

HDRV

LDRV

PHASE

BOOT

+V

CC

C

BOOT

C

VCC

+V

OUT

V

IN

PWRGD

COMP

FB

R

1

R

3

C

1

R

2

C

3

R

4

C

2

ON

OFF

SHDN

GND

+

V

IN

Typical Application

DS22326B-page 2  2012-2013 Microchip Technology Inc.

MCP19035

1.0 ELECTRICAL

CHARACTERISTICS

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those

Absolute Maximum Ratings †

VIN - V

V

BOOT

VHDRV, HDRV Pin................. +V

VLDRV, LDRV Pin.....................+ (V

Max. Voltage on Any Pin........... + (V

Storage Temperature ....................................-65°C to +150°C

Maximum Junction Temperature................................. +150°C

ESD protection on all pins (HBM) ....................................2 kV

ESD protection on all pins (MM) .....................................200V

........................................................ -0.3V to +32V

GND

................................................................-0.3V to +37V

-0.3V to V

PHASE

-0.3V) to (VCC+0.3V)

GND

-0.3V) to (VCC+0.3V)

GND

BOOT

+0.3V

indicated in the operational sections of this
specification is not intended. Exposure to maximum
rating conditions for extended periods may affect
device reliability.

DC ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, V

values), T

= -40°C to +125°C (for minimum and maximum).

A

Parameters Symbol Min Typ Max Units Conditions

Inputs

Input Voltage Range V

UVLO (V

Rising) UVLO

IN

UVLO (VIN Falling) UVLO

UVLO Hysteresis UVLO

Input Quiescent Current I(V

Shutdown Current I

IN_SHDN

IN

ON

OFF

HYST

)—68 mA

IN

4.5 — 30 V

44.24.4 V

3.4 3.6 3.8 V

— 600 — mV

— 25 50 µA SHDN = GND.

Linear Regulator

Output Voltage V

Output Current I

Short-Circuit

VCC-OUT

I

VCC-OUT_SC

CC

4.875 5 5.125 V 6V  VIN < 30V
50 — mA 6.5V  VIN < 30V, Note 2

— — 100 mA VIN = 6V, R

Output Current

Load Regulation — 0.1 — % Note 1
Line Regulation — 0.05 — % Note 1

Dropout Voltage — 0.75 1.3 V I

Power Supply

PSRR — 70 — dB f  1000 Hz,

Rejection Ratio

Internal Oscillator

Switching Frequency F

SW

255 300 345 kHz 2 options, see Section 4.4,

510 600 690 kHz

Ramp Signal Amplitude V

RAMP

0.911.1V

Reference Voltage

Reference Voltage

V

REF

585 600 615 mV

Generator

Note 1: Ensured by design. Not production tested.

2: Limited by the maximum power dissipation of the case.
3: Possibility to be adjusted for high volumes.

= 12V, FSW = 300 kHz, CIN = 1.0 µF, TA = +25°C (for typical

IN

Internal Voltage Regulator is
also disabled

VCC_OUT

I

VCC_OUT

= 0 µF,

C

IN

C

VCC-OUT

Internal Oscillator
Note 1

PP

< 0.1

LOAD

= 50 mA

= 50 mA

= 4.7 µF, Note 1

 2012-2013 Microchip Technology Inc. DS22326B-page 3

MCP19035

DC ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted, V

values), T

= -40°C to +125°C (for minimum and maximum).

A

Parameters Symbol Min Typ Max Units Conditions

Error Amplifier

Gain Bandwidth Product GBP 6.5 10 — MHz Note 1

Open Loop Gain A

Input Offset Voltage V

Input Bias Current

I

OL

OS

BIAS

70 80 — dB Note 1

-5 0.1 5 mV Note 1

—— 5 nANote 1

(FB Pin)

Error Amplifier

I

SINK

—5— mANote 1

Sink Current

Error Amplifier

I

SOURCE

—5— mANote 1

Source Current

PWM Section

Maximum Duty Cycle DC

Minimum ON time t

ON(MIN)

MAX

85 — — % Note 1
50 — 100 ns 6V  VIN < 30V, Note 1

Soft Start

Soft Start Time t

SS

—8— ms

Shutdown

Logic Low-to-High

SHDN

HI

0.85 — — V 4.5V  VIN < 30V, VCC goes

Threshold

Logic High-to-Low

SHDN

LO

— — 0.4 V 4.5V  VIN < 30V, VCC goes

Threshold

Power Goo d

Power Good

PG

TH-H

—9396% of V

Threshold High

Power Good

PG

TH-LOW

88 90 — % of V

Threshold Low

Power Good

PG

TH-HYS

—3—% of V

Threshold Hysteresis

Power Good Delay t

Power Good Active

t

PG-DELAY

PG-TIME-OUT

— 150 — us VFB = (PG

— 120 — ms VFB = (PG

Time-O ut Period

MOSFET Drivers

High-Side Driver Pull-up

R

HI-SOURCE

—23.5  V

Resistance

High-Side Driver Pull-

R

HI-SINK

—23.5  V

Down Resistance

Low-Side Driver Pull-Up

R

LO-SOURCE

—23.5  VCC = 5V, Note 1

Resistance

Low-Side Driver Pull-

R

LO-SINK

—12.5  VCC = 5V, Note 1

Down Resistance

HDRV Rise Time t

HDRV Fall Time t

LDRV Rise Time t

RH

FH

RL

—1535 nsC

—1535 nsC

—1025 nsC

Note 1: Ensured by design. Not production tested.

2: Limited by the maximum power dissipation of the case.
3: Possibility to be adjusted for high volumes.

= 12V, FSW = 300 kHz, CIN = 1.0 µF, TA = +25°C (for typical

IN

from 0V to 5V

from 5V to 0V

REF

REF

REF

(PG

TH-LOW

(PG

TH-HI

BOOT–VPHASE

I

HDRV

BOOT–VPHASE

I

HDRV

LOAD

LOAD

LOAD

+ 100 mV) to

TH-HI

– 100 mV)

– 100 mV) to

TH-HI

+ 100 mV)

= 4.5V,

= 100 mA, Note 1

= 4.5V,

= 100 mA, Note 1

= 1.0 nF, Note 1
= 1.0 nF, No te 1
= 1.0 nF, No te 1

DS22326B-page 4  2012-2013 Microchip Technology Inc.

MCP19035

DC ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise noted, V

values), T

= -40°C to +125°C (for minimum and maximum).

A

Parameters Symbol Min Typ Max Units Conditions

LDRV Fall Time t

Dead Time t

FL

DT

—1025 nsC

20 — — ns Two Dead-Time options, see

—12—

Short Circuit Protection

High-Side Over Current

OC

TH-HI

430 480 530 mV Note 1, V

Threshold Voltage

Low-Side Over Current

OC

TH-LO

130 180 230 mV Note 1, Note 3

Threshold Voltage

Minimum Pulse Width

t

SS-MIN

— 800 — ns Note 1

During Short Circuit

Off-Time Between

t

SS-HT

30 60 — ms Note 1

Restart Attempts (Hick­Up Time)

Thermal Shutdown

Thermal Shutdown TSHD — 150 — °C Note 1

Thermal Shutdown

TSHD_HYS — 15 — °C Note 1

Hysteresis

Note 1: Ensured by design. Not production tested.

2: Limited by the maximum power dissipation of the case.
3: Possibility to be adjusted for high volumes.

= 12V, FSW = 300 kHz, CIN = 1.0 µF, TA = +25°C (for typical

IN

LOAD

Section 5.2.2, Dead Time
Selection, Note 1

= 1.0 nF, No te 1

= 5V

CBOOT

TEMPERATURE SPECIFICATIONS

Electrica l Character istics: Unless otherwise indicated, V

Parameters Sym Min Typ Max Units Conditions

Temperature Ranges

Specified Temperature Range T

Maximum Junction Temperature T

J-MAX

Operating Temperature Range T

Storage Temperature Range T

Thermal Package Resistances

Thermal Resistance, 10L-3x3 DFN 

-40 — +125 °C

A

——+150°C

-40 — +125 °C

A

-65 — +150 °C

A

JA

— 53.3 — °C/W Typical 4-Layer board with

= 6.0V to 30V, FSW = 300 kHz

IN

interconnecting vias

 2012-2013 Microchip Technology Inc. DS22326B-page 5

MCP19035

NOTES:

DS22326B-page 6  2012-2013 Microchip Technology Inc.

MCP19035

5.0

6.0

7.0

iescent Current (mA)

fSW= 300 kHz

fSW= 600 kHz

4.0

0 5 10 15 20 25 30 35

Input Qu

Input Voltage (V)

4.0

6.0

8.0

10.0

escent Current (mA)

0.0

2.0

-50 0 50 100 150

Input Qu

i

Junction Temperature (°C)

-4.0

-2.0

0.0

2.0

4.0

scillator Frequency

ariation (%)

f

S

W

= 300 kHz

fSW= 600 kHz

-10.0

-8.0

-6.0

-50 0 50 100 150

Relative

O

V

Junction Temperature (°C)

4.99

5.01

5.03

5.05

utput Voltage (V)

I

LOAD

= 20 mA

4.95

4.97

0 10203040

LDO

O

Input Voltage (V)

4.99

5.01

5.03

5.05

Output Voltage (V)

4.95

4.97

0 204060

LDO

Load Current (mA)

0.75

1

1.25

1.5

opout Voltage (V)

I

LOAD

= 50 mA

0

0.25

0.5

-50 0 50 100 150

LDO D

r

Junction Temperature (°C)

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T

=+25°C, VIN = 12V, V

A

FIGURE 2-1: Input Quiescent Current vs. Input Voltage.

= 1.8V, fSW = 300 kHz, C

OUT

FIGURE 2-4: +V
Input Voltage.

= 4.7 uF.

VCC

CC-OUT

Regulation vs.

FIGURE 2-2: Input Quiescent Current vs. Temperature.

FIGURE 2-3: Relative Oscillator Frequency Variation vs. Temperature.

 2012-2013 Microchip Technology Inc. DS22326B-page 7

FIGURE 2-5: +V

CC-OUT

Regulation vs.

Load Current.

FIGURE 2-6: LDO Regulator Dropout Voltage vs. Temperature.

MCP19035

-50.0

-30.0

-10.0

DO PSRR (dB)

-90.0

-70.0

10 1000 100000

L

Frequency (Hz)

0

0.1

0.2

e Reference Voltage

Variation (%)

-0.2

-0.1

-50 0 50 100 150

Relati

v

Junction Temperature (°C)

4

5

Volatge Lockout

resholds (V)

VINRising

VINFalling

2

3

-50 0 50 100 150

Under

T

h

Junction Temperature (°C)

8.0

9.0

10.0

11.0

12.0

Start Time (ms)

I

OUT

= 1 A

fSW= 600 kHz

=

5.0

6.0

7.0

-50 0 50 100 150

Sof

t

Junction Temperature (°C)

fSW300 kHz

500

600

Side Overcurrent

reshold (mV)

V

CBOOT

= 5V

300

400

-50 0 50 100 150

High-

T

h

Junction Temperature (°C)

-100

0

Side Overcurrent

hreshold (mV)

-200

-50 0 50 100 150

Low

-

T

Junction Temperature (°C)

Note: Unless otherwise indicated, T

FIGURE 2-7: +V

CC-OUT

LDO PSRR vs.

Frequency.

=+25°C, VIN = 12V, V

A

= 1.8V, fSW = 300 kHz, C

OUT

VCC

= 4.7 uF.

FIGURE 2-10: Soft Start Time vs. Temperature.

FIGURE 2-8: Relative Reference Voltage Variation vs. Temperature.

FIGURE 2-9: UVLO Thresholds vs. Temperature.

DS22326B-page 8  2012-2013 Microchip Technology Inc.

FIGURE 2-11: High-Side Overcurrent Threshold vs. Temperature.

FIGURE 2-12: Low-Side Overcurrent Threshold vs. Temperature.

MCP19035

-10

0

10

20

30

40

50

e Driver PMOS R

DSon

ive Variation (%)

-50

-40

-30

-

20

-50 0 50 100 150

High-Si

d

Rela

t

Junction Temperature (°C)

-10

0

10

20

30

40

50

Driver NMOS R

DSon

ive Variation (%)

-50

-40

-30

-20

-50 0 50 100 150

High-Sid

e

Rela

t

Junction Temperature (°C)

-10

0

10

20

30

40

50

Driver PMOS R

DSon

ive Variation (%)

-50

-40

-30

-20

-50 0 50 100 150

Low-Sid

e

Relea

t

Junction Temperature (°C)

-10

0

10

20

30

40

50

Driver NMOS R

DSon

ive Variation (%)

-50

-40

-30

-20

-50 0 50 100 150

Low-Sid

e

Rela

t

Junction Temperature (°C)

120

130

140

150

ood Active Timeout

(ms)

100

110

-50 0 50 100 150

Power

G

Junction Temperature (°C)

90

100

Good Thresholds

eference Voltage)

PWRGD = Low

PWRGD = High

80

-50 0 50 100 150

Powe

(% of

R

Junction Temperature (°C)

Note: Unless otherwise indicated, T

A

FIGURE 2-13: HDRV P-Ch R
Variation vs. Temperature.

=+25°C, VIN = 12V, V

Relative

DSon

= 1.8V, fSW = 300 kHz, C

OUT

VCC

FIGURE 2-16: LDRV N-Ch R
Variation vs. Temperature

= 4.7 uF.

DSon

Relative

FIGURE 2-14: HDRV N-Ch R
Variation vs. Temperature.

FIGURE 2-15: LDRV P-Ch R
Variation vs. Temperature.

 2012-2013 Microchip Technology Inc. DS22326B-page 9

DSon

DSon

Relative

Relative

FIGURE 2-17: PG Active Time Out Period vs. Temperature.

FIGURE 2-18: PG Thresholds Voltage vs. Temperature.

MCP19035

NOTES:

DS22326B-page 10  2012-2013 Microchip Technology Inc.

3.0 PIN DESCRIPTION

Description of the pins are listed in Ta bl e 3- 1.

TABLE 3-1: PIN DESCRIPTION TABLE

MCP19035

3x3 DFN

Symbol Description

MCP19035

1 SHDN

2 FB Feedback voltage input pin

3 COMP Internal error amplifier output pin

4V

5 PWRGD Power good pin

6+V

7 LDRV Lower gate drive output pin

8 BOOT Floating bootstrap supply pin

9 PHASE Switching node pin

10 HDRV Upper gate drive output pin

11 EP Exposed Thermal Pad, must be connected to GND

IN

CC

Device shutdown input pin

Input voltage pin

+5.0V output voltage pin

3.1 Shutdown Input Pin (SHDN)

This pin enables or disables the MCP19035 device.
When logic “High” is applied to this pin, the device is
enabled. A logic “Low” will disable the device. When
the device is disabled, both the LDRV and HDRV pins
are held low. The internal LDO regulator is also dis­abled when the SHDN
pin float. If not used, connect to V
resistor.

pin is pulled low. Do not let this

using a 100 k

IN

3.2 Feedback Voltage Input Pin (FB)

This is the internal error amplifier’s negative input, and
is used to sense the output voltage. The positive input
to the amplifier is connected to the internal reference
voltage.

3.5 Power Good Pin (PWRGD)

The power good pin is an open drain output. This pin is
pulled low when the output is 90% less than the typical
value. Connect this pin to +VCC pin through a pull-up
resistor. The recommended value for the pull-up resis­tor is 100 k.

3.6 LDO Output Voltage Pin (+VCC)

This pin is the output of the internal voltage regulator
(LDO). The internal circuitry of the controller is powered
from this pin (+5.0V). External low noise loads can be
powered from this pin, but the sum of the external load
current and the internal circuitry current should not
exceed 50 mA. A 4.7 F ceramic capacitor must be
connected between this pin and GND.

3.3 Internal Error Amplifier Pin (COMP)

This is the output of the internal error amplifier. The
compensation network is connected between this pin
and the FB pin.

3.7 Lower Gate Pin (LDRV)

This pin is the drive output for the low-side N-Channel
MOSFET (synchronous rectifier). The LDRV drive is
capable of sourcing 1A and sinking 1.5A.

3.8 Bootstrap Supply Pin (BOOT)

3.4 Input Voltage Pin (VIN)

This pin is the input power for the controller. A bypass
capacitor must be connected between this pin and the
GND pin. The input of an internal voltage regulator
(LDO) is connected to this pin to generate the +5V V
used for internal circuitry bias.

 2012-2013 Microchip Technology Inc. DS22326B-page 11

CC

The BOOT pin is the floating bootstrap power supply
pin for the high-side MOSFET gate driver. A capacitor
connected between this pin and the PHASE pin pro­vides the necessary charge to turn on the external
high-side MOSFET.

MCP19035

3.9 Switching Node Pin (PHASE)

This pin provides a return path for the high-side gate
driver. It also provides a path for the charging of the
BOOT capacitor, used while turning on the high-side
MOSFET. This pin also senses the switching transition
to eliminate cross conduction (shoot-through).

3.10 Upper Gate Drive Pin (HDRV)

This pin is the high-side N-channel MOSFET (control
transistor) gate drive output. The HDRV drive is
capable of sourcing and sinking 1A.

3.11 Exposed Thermal Pad (EP)

Analog ground and power ground are both connected
to this pin.

DS22326B-page 12  2012-2013 Microchip Technology Inc.

MCP19035

HDRV

LDRV

Oscillator

BOOT

Control

Logic

SHDN

V

IN

PWRGD

COMP

FB

PHASE

Cross

Conduction

Protection

HD

LD

Voltage

Regulator

Comp

Dead
Time

Generator

+

-

V

CC

Power-Good

Circuit

Shut-Down

Circuit

+

-

SD

EA

SD

UVLO

Circuit

Over-Current

Detection Circuit

Reference

Voltage

Generator

Soft Start

Circuit

FB

SD

GND

V

REF

PWM

Over-Temperature

Detection Circuit

OT

OT

V

IN

V

CC

V

CC

V

CC

V

CC

4.0 DETAILED DESCRIPTION

4.1 Device Overview

The MCP19035 family of devices are high­performance controllers providing all the necessary
functions to construct a high-performance DC/DC
converter, while keeping costs and design effort to a
minimum:

• Support for pre-biased outputs eliminates con-

cerns about damaging sensitive loads during
startup.

• Strong gate drivers for the high-side and rectifier

N-Channel MOSFETs decrease switching losses,
yielding increases in efficiency.

• Adaptive gate drive timing prevents shoot-through

and minimizes body diode conduction in the syn­chronous rectifier MOSFET, which also increases
the efficiency.

• Dead-Time optimization options of the MCP19035
assist in improving the power conversion effi­ciency, when used with high-speed, low Figure of
Merit MOSFETs.

• Overcurrent protection circuits in both high and
low-side switches, and a short circuit hiccup­recovery mode increase design flexibility and min­imize power dissipation in the event of prolonged
output faults.

• The dedicated SHDN
be placed in a low quiescent current state.

• Internal fixed converter switching frequency and
soft-start reduce the external component count,
simplifying design and layout, as well as reducing
footprint and size.

• The 3 mm × 3 mm DFN package size also mini­mizes the overall converter footprint.

pin allows the converter to

FIGURE 4-1: Internal Block Diagram.

 2012-2013 Microchip Technology Inc. DS22326B-page 13

MCP19035

PG

TH-LOW

t

PG-TIMEOUT

PG

V

FB

t

PG-DELAY

PG

TH-HI

PG

V-LOW

4.2 PWM Circuitry

The MCP19035 controller implements a fixed
frequency, voltage-mode control scheme. The internal
PWM generator is comprised of an oscillator, error
amplifier, high-speed comparator and a latch. The error
amplifier generates the control voltage by amplifying
the difference between voltage reference (600 mV,
internally generated) and the voltage of the FB pin
(feedback voltage). This control voltage is compared by
the high-speed comparator to an artificially generated
ramp signal; the result is a PWM signal. An SR latch
(Set-Reset flip-flop) is used to prevent the PWM
circuitry from turning on the external switch until the
beginning of the next clock cycle.

An external Compensation Network (Type-II or
Type-III) must be used to stabilize the control system.

4.3 Internal Reference Voltage V

REF

An integrated, precision voltage reference is provided
by the MCP19035. An external resistor divider is used
to program the converter’s output voltage. The nominal
value of this internal reference voltage is 600 mV.

4.4 Internal Oscillator

The MCP19035 device provides two switching
frequency options: 300 kHz and 600 kHz.

4.5 Under Voltage Lockout Circuit (UVLO)

A 100 k pull-up resistor is recommended between the
SHDN pin and VIN pin. Note that the SHDN input is a
high-impedance pin. Noise generated by the circuits
located near this pin may inadvertently shut down the
controller. To improve the noise immunity of this input
pin, we recommend placing a small capacitor between
GND and SHDN

, or decrease the value of the pull-up
resistor. The Shutdown input pin should not be left
floating.

4.7 Power Good Output (PWRGD)

This open drain output provides an indication that the
output voltage is 92% (typical) of its regulated value.
This output is also low for other existing conditions that
signal the possibility that the output of the power supply
is out of regulation. The conditions are:

• Feedback pin (FB) voltage differs more than ±8%

from its nominal value (600 mV)

• Soft-start period is active

• Undervoltage condition detected

• Overcurrent condition detected, on either the High

Side or Low Side

• Die temperature is above the thermal shutdown

threshold (+150°C)

The active high power good signal has a fixed time
delay of approximately 120 ms (t
typically a 150 s delay (t

PG-DELAY

signal high-to-low transition.

PG-TIMEOUT

) on the power good

). There is

An integrated Under Voltage Lockout Circuit (UVLO)
prevents the converter from starting until the input volt­age is high enough for normal operation. The converter
will typically start at 4.2V and operate down to 3.6V.
Hysteresis is added to prevent starting and stopping
during startup, as a result of loading the input voltage
source.

4.6 Shutdown Input

The Shutdown input pin (SHDN) is used to enable and
disable the controller. When the SHDN
low, the MCP19035 is placed in Shutdown mode.
During Shutdown, most of the internal circuits
(including the LDO) are disabled, to minimize current
consumption.

pin is pulled

FIGURE 4-2: Power Good Signal.

DS22326B-page 14  2012-2013 Microchip Technology Inc.

MCP19035

I

External Load

= 50 mA - f

SW

x(Q

G(High Side)

+ Q

G(Low Side)

) - 5 mA

Where:

I

External Load

= Current Available for powering the

External Load

f

SW

= Switching Frequency (300 kHz or

600 kHz)

Q

G(High Side)

= Total Gate Charge of the High-Side

MOSFET at 4.5V V

GS

Q

G(Low Side)

= Total Gate Charge of the Low-Side

MOSFET at 4.5V V

GS

4.8 Internal Voltage Regulator (LDO)

The MCP19035 controller offers an internal 5V Low
Dropout Voltage Regulator. This regulator provides the
bias voltage for all internal circuits. A ceramic capacitor
(4.7 F minimum) must be connected between the
output of this LDO (V
stable operation.

An external low noise load may be powered from this
regulator, but the total current consumed from the LDO
output (internal circuitry of MCP19035 + external load)
should not exceed 50 mA. The internal circuitry of the
MCP19035 consume approximately 5 mA. The total
amount of current available to power the external load
can be estimated from Equation 4-1:

EQUATION 4-1:

This LDO dissipates power within the MCP19035. To
avoid tripping the Overtemperature Protection Circuit,
the designer must ensure that the maximum die
temperature is below +125°C under worst case
conditions (i.e. high input voltage). For further
information regarding the maximum dissipated power
for LDOs, see Microchip’s AN761 and AN792
application notes.

The LDO is protected against overload and short-circuit
conditions. Consistent performance of the internal
MOS drivers is ensured by monitoring the LDO output
voltage; if the voltage is lower than 3.3V typical, the
chip will enter in Shut-Down mode to prevent damage
to the external MOSFETs.

pin) and ground (GND pin) for

CC

4.9 Internal MOSFET Drivers

Internal MOSFET drivers are capable of driving
external, “Logic Level” (+5V) MOSFETs.

The Low-Side Driver (LDRV) is referenced to the GND
pin and is capable of sourcing 1A and sinking 1.5A.

The High-Side Driver (HDRV) is floating and capable of
sourcing and sinking 1A. This driver is powered from an
external bootstrap capacitor.

The drivers have non-overlapping timing that is
governed by an adaptive delay circuit to minimize body
diode conduction in the synchronous rectifier.

For the optimized Dead Time version of the
MCP19035, the adaptive delay circuit is disabled and
the Dead Time has a fixed value.

4.10 Overcurrent Protection

Overcurrent protection is accomplished by monitoring
the voltage across the external MOSFETs when they
are ON (conducting).

For the high-side overcurrent protection, when the
sensed voltage drop across the high-side MOSFET is
greater than the high-side overcurrent threshold
voltage, the high-side MOSFET is immediately turned
off and the high-side overcurrent counter is
incremented by one. On the next cycle, if the high-side
overcurrent threshold voltage is not exceeded, the
high-side overcurrent counter is decreased by one
count. If the high-side overcurrent counter reaches a
count of 7, a fault condition exists and the MCP19035
turns off both external MOSFETs.

After a 60 ms delay, the MCP19035 will attempt to
restart. If during the next cycle, a high-side overcurrent
threshold voltage is measured across the high-side
MOSFET, a fault is again declared and both external
MOSFETs are turned off for another 60 ms. However, if
after the attempted restart a high-side overcurrent
threshold voltage is not measured across the high-side
MOSFET, the high-side overcurrent counter is
decreased by one and the MCP19035 continues to
operate until the high-side overcurrent counter reaches
a count of 7.

The low-side overcurrent protection behaves much the
same way as the high-side overcurrent protection. The
difference is that the low-side MOSFET is not
immediately turned off when a low-side overcurrent
threshold voltage is measured. It remains on until the
next cycle begins.

 2012-2013 Microchip Technology Inc. DS22326B-page 15

MCP19035

I

HS MOS

V

OC HS

R

DSON

-----------------=

Where:

IHS

MOS

= Current that passes through the

High-Side MOSFET

V

OC HS

= Threshold Voltage for High-Side

Overcurrent Protection Circuit
(480 mV)

R

DSON

= ON Resistance of the High-Side

MOSFET

I

LS MOS

V

OC LS

R

DSON

---------------- -=

Where:

I

LS MOS

= Current that passes through the

Low-Side MOSFET

V

OC LS

= Threshold Voltage for Low-Side

Overcurrent Protection Circuit
(180 mV)

R

DSON

= ON Resistance of the Low-Side

MOSFET

For the low-side overcurrent protection, when the
sensed voltage drop across the low-side MOSFET is
greater than the low-side overcurrent threshold voltage
specified, a low-side overcurrent counter is
incremented by one count. On the next cycle, if the low­side over current threshold voltage is not exceeded, the
low-side overcurrent counter is decreased by one. If
the low-side overcurrent counter reaches a count of 7,
a fault condition exists and the MCP19035 turns off
both external MOSFETs. After a 60 ms delay, the
MCP19035 device will attempt to restart. If during the
next cycle, a low-side overcurrent threshold voltage is
measured across the low-side MOSFET, a fault is
again declared and both external MOSFETs are turned
off for another 60 ms. However, if after the attempted
restart a low-side overcurrent threshold voltage is not
measured across the low-side MOSFET, the low-side
overcurrent counter is decreased by one and the
MCP19035 continues to operate until the low-side
overcurrent counter reaches a count of 7.

The voltage threshold for high-side overcurrent
protection circuit is fixed, 480 mV typical. The high-side
voltage threshold will also depend on the value of the
voltage across the bootstrap circuit capacitor, and will
decrease when this voltage decreases. This will ensure
that the high-side protection will avoid a failure of the
MOSFET when the bootstrap voltage is low and the
switching losses are high. This threshold will provide a
cycle-by-cycle protection in case of short circuit, but it
should not be used to provide a precise current limit for
the converter. An estimation of the current that flows in
the high-side MOSFET during short circuit can be
found using Equation 4-2. Note that, due to the leading
edge blanking time, this current also depends on the
inductor's ripple current. To avoid false triggering of the
high-side overcurrent protection circuit during
transients, it is highly recommended to choose a
MOSFET that will provide a threshold at least four
times higher than the maximum output current of the
converter.

EQUATION 4-2: PEAK CURRENT FOR

HIGH-SIDE MOSFET

The voltage threshold for the low-side overcurrent
protection circuit is fixed, 180 mV typical. Different
values for this threshold (from 100 mV to 300 mV) are
available on request. An estimation of the current that
flows on the low-side MOSFET during short circuit is
realized using Equation 4-3. Note that, due to the
leading edge blanking time, this current also depends
on the inductor's ripple current. To avoid false triggering
of the low-side over current protection circuit during
transients, it is highly recommended to choose a
MOSFET that will provide a threshold at least two times
higher than the maximum output current of the
converter.

EQUATION 4-3:

To avoid a false trigger of the overcurrent circuit, a
leading edge blanking circuit is present on both the
high and low-side measurements. Due to this blanking
time, the accuracy of the overcurrent circuit may be
impacted if the converter operates at higher duty cycles
(more than 85%), or if the inductor's current ripple is

DS22326B-page 16  2012-2013 Microchip Technology Inc.

very high (i.e. the inductor is saturated by the excessive
current).

4.11 Soft Start

SHDN

V

OUT

Soft Start Time

(T

SS

= 8 ms)

To control the output voltage during start-up, the
MCP19035 uses a soft-start circuit that allows the
output voltage of the system to monotonically increase.
The soft start circuitry allows the output voltage to rise
up to the desired regulation limit, typically within 8 ms.
The soft start circuit is enabled each time the
MCP19035 starts. This includes initial start-up, start-up
from toggling the SHDN
shutdown, or start-up after an overcurrent condition.

pin, start-up after thermal

MCP19035

FIGURE 4-3: Soft Start-up Diagram.

4.12 Pre-Bias Load Start-up

A special start-up sequence will prevent any current to
be sourced from the output in case of a pre-biased
load. This is accomplished by monitoring the FB pin
and internal reference voltages. If the positive input to
the Error Amplifier (internal reference voltage) is
greater than the feedback voltage (voltage present at
FB pin), the controller will drive the low-side MOSFET
(synchronous rectifier) with a reduced duty cycle. This
sequence ensures a smooth output voltage transition
without sinking any current from the pre-biased
external load.

Note: Do not use a low impedance source to

back-drive the output voltage during the
pre-bias state. There is no protection
mechanism for positive current flow in the
synchronous rectifier MOSFET. The
converter can reverse the energy flow
(becoming a Boost converter) if the input
voltage is accidentally disconnected.

 2012-2013 Microchip Technology Inc. DS22326B-page 17

MCP19035

NOTES:

DS22326B-page 18  2012-2013 Microchip Technology Inc.

MCP19035

LV

IN

MAX

V

OUT

–





V

OUT

V

IN

MAX

-----------------------



1

f

SW

----------

1

0.3 I

OUT

MAX



------------------------------------------



=

I

L

PEAK

I

OUT

MAX

0.3 I

OUT

MAX



2

------------------------------------------+=

I

L

RMS

I

2

OUT

I

Ripple

2

3

------------------- -+=

5.0 APPLICATION INFORMATION

5.1 Typical Applications

The MCP19035 synchronous buck controller operates
over an input voltage range up to a maximum of 30V.
The output current capability depends only on the
external MOSFET’s selection and can also be very
high, typically up to 20A.

Typical applications include POL modules for powering
DSPs, FPGAs and ASICs, and, in general, any step­down voltage conversion (from maximum 30V input
voltage) for medium-to-high output current loads.

5.2 Design Procedure

To simplify this design process, an Excel®-based
design tool is available to support typical applications.
This tool is available on the MCP19035 product web

site. Refer to AN1452 – “Using the MCP19035
Synchronous Buck Converter Design Tool” for further

details.

5.2.1 SWITCHING FREQUENCY AND THE
MAXIMUM CONVERSION RATIO

The MCP19035 controller provides two options for the
switching frequency: 300 kHz and 600 kHz. In general,
choosing a higher switching frequency allows the use
of smaller size components (i.e. inductor and filtering
capacitors), but increases the switching losses. The
300 kHz switching frequency is recommended for
applications requiring output currents up to 20A. For
applications requiring output currents up to 10A, the
recommended switching frequency is 600 kHz.

Due to the minimum “On Time” for the high-side
MOSFET driver (70 ns typical), the maximum
conversion ratio must be limited to 20:1.

5.2.2 DEAD TIME SELECTION

Dead Time will affect the maximum obtainable
efficiency of the converter. Selecting the Dead Time
depends on the external MOSFETs’ parameters. Lower
Figure of Merit (FOM) transistors will permit the use of
shorter Dead Times. This may increase the converter
efficiency by up to 2%.

Low Figure of Merit transistors allow the user to select
a low value for Dead Time (typical 12 ns) without
causing a shoot-through phenomenon. For low-FOM
transistors, the MCP19035 version with fixed 12 ns
Dead Time is recommended.

For typical medium Figure of Merit transistors, the
MCP19035 version with the adaptive Dead-Time
generator is recommended.

5.2.3 INDUCTOR SELECTION

The output inductor is responsible for smoothing the
square wave created by the switching action and for
controlling the output current ripple (I

). There is a

OUT

trade off between efficiency and load transient
response time when the value of the inductor is
chosen. The smaller the inductance, the quicker the
converter can respond to transients in the load current.
However, a smaller inductor requires a higher switching
frequency to maintain the same level of output current
ripple. Remember that increasing the switching
frequency will also increase the switching losses in the
MOSFETs.

A good compromise for the inductor current ripple is
30% of the output current. The value of the inductor is
calculated in Equation 5-1:

EQUATION 5-1: INDUCTOR VALUE

The peak current in the inductor is determined in

Equation 5-2:

EQUATION 5-2: INDUCTOR PEAK

CURRENT

EQUATION 5-3: INDUCTOR RMS

CURRENT

Additional care must be taken when selecting an induc­tor:

• Choose an inductor that has a saturation current
larger than the calculated peak current. The
tolerance of the inductor must also be considered
(typically 20%).

• To minimize the conduction losses, choose an
inductor with the lowest possible DC resistance.
The maximum DC resistance specified in the data
sheet will ensure the worst-case component spec­ification.

• There are many magnetic materials available for
inductor core: ferrite, iron powder and composite
materials. The ferrite offers the lowest core
losses, but the saturation characteristic is “hard”
(i.e. the inductance drops rapidly after the current
reaches the saturation level). The losses of iron
powder or composite material cores are higher
than ferrite, but the saturation characteristic is
“soft”, making it more suitable for voltage mode
control converter, including the MCP19035.

 2012-2013 Microchip Technology Inc. DS22326B-page 19

MCP19035

C

IN_MIN

I

OUT

D1D–



f

SWVRipple

DI

OUT

ESR



–



-----------------------------------------------------------------------------------=

Where:

C

IN_MIN

= Minimum Capacitance of the Input

Capacitor (in Farad)

I

OUT

= Output Current (A)

D = Duty Cycle (for worst case this is 0.5)

fSW= Switching Frequency (Hz)

V

Ripple

= Input Voltage Ripple (usually between

0.1V and 0.5V)

ESR = Equivalent Series Resistance of the

Capacitor (in Ohm)

I

RMS CINIOUT

I

Ripple

12

--------------- -+





D

V

OUTIOUT



V

IN

--------------------------------





–=

V

RippleIRipple

ESR

1

8C

OUTfSW



--------------------------------------+







=

Where:

I

Ripple

= Inductor Current Ripple (A)

V

Ripple

= Output Voltage Ripple (V)

C

OUT

= Output Capacitor (F)

ESR = Equivalent Series Resistance of the

Output Capacitor (Ohm)

C

OUT

LI

OH

2

I

OL

2

–



V

f

2

V

OUT

2

–

------------------------------------=

Where:

I

OH

= Final Value of the Output Current

IOL= Initial Value of the Output Current

V

OUT

= Initial Output Voltage

V

f

= Final Output Voltage

5.2.4 INPUT CAPACITOR SELECTION

The input capacitor is responsible for providing a low
impedance voltage source for the step-down converter.
This capacitor must be able to sustain high ripple
current, a consequence of the discontinuous input
current of the buck converter. A low equivalent series
resistance capacitor (ESR), preferably ceramic, is
recommended. For wide temperature range
applications, a multi-layer X7R dielectric is
recommended, while for applications with limited
temperature range, a multi-layer X5R dielectric is
acceptable. A higher ESR will produce a higher voltage
ripple and higher power losses. The capacitor voltage
rating must be higher than the maximum operating
input voltage of the converter.

The minimum capacitance is determined in

Equation 5-4:

EQUATION 5-4: MINIMUM CAPACITANCE

FOR INPUT CAPACITOR

5.2.5 OUTPUT CAPACITOR SELECTION

The output capacitor is responsible for smoothing the
output voltage. It also plays an important role in the
stability of the control system. The voltage ripple across
the output capacitor is the sum of ripple voltages due to
the Equivalent Series Resistance (ESR) and the
voltage sag due to the load current that must be
supplied by the capacitor as the inductor is discharged.
A low ESR capacitor, preferably ceramic, is
recommended. For wide temperature range
applications, a multi-layer X7R dielectric is
recommended, while for applications with limited
temperature range, a multi-layer X5R dielectric is
acceptable.

The output voltage ripple is estimated in Equation 5-6:

EQUATION 5-6: OUTPUT VOLTAGE

RIPPLE

The maximum ripple current in the input capacitor
occurs when the duty cycle is 50%. This must be
considered worst case for calculating the input
capacitor.

The RMS current in the input capacitor is estimated
with Equation 5-5:

EQUATION 5-5: RMS CURRENT IN THE

INPUT CAPACITOR

The input capacitor must be rated to sustain this RMS
current without considerable losses.

DS22326B-page 20  2012-2013 Microchip Technology Inc.

Minimum capacitance value is calculated according to
the demand of the load transient response. During a
transient load current, the excessive energy stored by
the inductor must be absorbed by the output capacitor
until the control loop sets the proper duty cycle.

Equation 5-7 calculates the minimum value for the

output capacitor value:

EQUATION 5-7: OUTPUT CAPACITOR

MINIMUM VALUE

For applications that require low output voltage
overshoot during a step load, the value of the output
capacitor can become very large. In this case, it is
recommended to mix ceramic capacitors with
aluminum or polymer electrolytic capacitors to reach
the recommended value.

MCP19035

FOM Q

GTotRDS

ON

=

I

RMS High-Side

DI

OUT

2

I

Ripple

2

12

--------------- -+









=

Where:

D = Duty Cycle

I

OUT

= Output Current (A)

I

Ripple

= Current Ripple in the Inductor

(typically 30% of the maximum output
current) (A)

P

COND High-SideIRMS High-Si de

2

R

DS onHS max



=

P

SW High-Sid e

VINI

OUT



2

---------------------------





t

sHLtsLH

+



f

SW



=

Where:

V

IN

= Input Voltage (V)

I

OUT

= Output Current (A)

fSW= Switching Frequency (Hz)

t

s(HL)

= MOSFET Switching Time

(High-to-Low transition) (s)

t

s(LH)

= MOSFET Switching Time

(Low-to-High transition) (s)

t

sHL

Q

G Total

I

DRV

Sink

--------------------- -=

t

sLH

Q

G Total

I

DRV

Source

--------------------- -=

Where:

Q

G(Total)

= High-side MOSFET Total Gate

Charge

I

DRVSink

= Sink Peak Current for High-Side

Driver (typical 1A)

I

DRVSource

= Source Peak Current for High-Side

Driver (typical 1A)

P

Lo s s Hi g h -Side

P

COND High-Si dePSW High-Side

+=

5.2.6 MOSFETS SELECTION

Choosing the right MOSFET is a critical part of the
design for a switching regulator. Their performance will
directly impact the efficiency and reliability of the
regulator.

The MCP19035 synchronous buck controller offers an
integrated, logic-level MOSFET driver, and is capable
of supplying 5V to drive the MOSFET gates. As a
result, logic-level MOSFETs must be used. Suitable
MOSFETs should meet the requirement of voltage and
current rating.

A key parameter for evaluating the MOS transistor
performance is the Figure of Merit. For a given
MOSFET, this is defined as the product between the
Total Gate Charge (Q

) and R

G

(see Equation 5-

DS(ON)

8).

EQUATION 5-8: FIGURE OF MERIT

A lower FOM value means a higher-performance MOS
transistor.

For the high-side MOSFET, power losses consist of
both switching and conduction losses. Conduction
losses are high when the duty cycle of the converter is
high. The conduction loss of the high-side MOSFET
can be estimated by multiplying the R
RMS value of the current that passes through the tran­sistor (see Equation 5-9).

DS(ON)

with the

The switching losses are more difficult to calculate,
since they depend on many parameters. Equation 5-11
shows an estimation of these losses:

EQUA TION 5-11: SWITCHING LOSSES FOR

HIGH-SIDE MOSFET

The t
following equations:

s(HL)

and t

times can be estimated using the

s(LH)

EQUATION 5-12:

EQUATION 5-9: RMS VALUE FOR

The conduction losses for high-side MOS transistor are
estimated in Equation 5-10:

EQUATION 5-10: CONDUCTION LOSSES

 2012-2013 Microchip Technology Inc. DS22326B-page 21

HIGH-SIDE CURRENT

FOR HIGH-SIDE MOSFET

The total power losses for the high-side MOSFET can
be calculated with Equation 5-13:

EQUATION 5-13: TOTAL POWER LOSSES

FOR HIGH-SIDE MOSFET

For applications that operate with low duty cycle (lower
than 30%) or high input voltage, the power losses for
the high-side transistor are mainly switching losses.
For these applications, it is recommended to choose a
MOSFET that offers a low Total Gate Charge.

For applications that operate with duty cycles higher
than 50%, the power losses for the high-side transistor
are mainly conduction losses. For these applications,
choose a MOSFET that has a low R

DS(on).

MCP19035

I

RMS Low-Side

1D–I

OUT

2

I

Ripple

2

12

--------------- -+









=

Where:

D = Duty Cycle

I

OUT

= Output Current (A)

I

Ripple

= Current Ripple in the Inductor

(typically 30% of the maximum output
current) (A)

P

CO N D Lo w -SideIRMS Low-Si de

2

R

DS onLS max



=

P

LOSS BDIOUTVF

 tBDfSW=

Where:

V

F

= Forward Voltage of the Body Diode (V)

t

BD

= Total Conduction Time for Body Diode (s)

P

RR

QRRVINf

SW



2

----------------------------------------=

Where:

QRR= Reverse Recovery Charge of the Body Diode (C)

P

Loss Low-Side

P

COND Low-SidePLOSS BDPRR

++=

C

BOOT

Q

G Total



V

DROOP

----------------------- -=

Where:

Q

G(Total)

= High-side MOSFET Total Gate Charge (C)

V

DROOP

= Allowable Gate Drive Voltage Droop (V)

The low-side MOSFET (synchronous rectifier) is “soft­commutated” by the energy stored in the inductor , thus
reducing the switching losses. For the low-side transis­tor, the power losses mainly consist of conduction
losses, body diode conduction losses and body diode
reverse recovery losses.

Similarly to the high-side, the RMS current that pass
through the low-side MOSFET is calculated using

Equation 5-14:

EQUATION 5-14: RMS CURRENT FOR

LOW-SIDE MOSFET

The conduction losses for low-side MOS transistor are
estimated in Equation 5-15:

EQUATION 5-15: CONDUCTION LOSSES

FOR LOW-SIDE
TRANSISTOR

The body diode conduction loss is calculated in

Equation 5-16:

EQUATION 5-16: BODY DIODE

CONDUCTION LOSSES

The body diode recovery time losses will be calculated
using Equation 5-17:

EQUATION 5-17: BODY DIODE REVERSE

RECOVERY LOSSES

The total power loss for the low-side MOSFET can now
be estimated by summing the power losses in

Equation 5-18:

EQUA TION 5-18: T OTAL POWER LOSS FOR

LOW-SIDE MOSFET (SR)

The conduction losses are the dominant part of the total
losses for the low-side transistor; choose a MOSFET
with a low R

DS(on)

.

The body diode conduction and reverse recovery
losses can be greatly minimized by reducing the Dead
Times necessary to prevent the shoot-through. This
can be achieved by choosing transistors that have a
very low Figure of Merit (FOM) MOSFET for both sides.

5.2.7 BOOTSTRAP CAPACITOR
SELECTION

The selection of the bootstrap capacitor is based upon
the total gate charge of the high-side power MOSFET
and the allowable droop in gate drive voltage while the
high-side power MOSFET is conducting (see

Equation 5-19).

EQUATION 5-19: BOOTSTRAP CAPACITOR

DS22326B-page 22  2012-2013 Microchip Technology Inc.

It is recommended that the voltage droop does not
exceed 50 mV. A low ESR, ceramic capacitor, rated at
least 16 V

, is recommended.

DC

MCP19035

Magnitude

(dB)

Frequency

(log scale)

A

MOD

0dB

-40 dB/decade

-20 db/decade

f

LC

f

ESR

Phase

(deg)

0°

-90°

-180°

Frequency
(log scale)

f

LC

1

2



LC

OUT



-------------------------------------=

f

ESR

1

2



ESR C

OUT



-----------------------------------------------=

A

MOD

20

V

IN

V

RAMP



-------------------- -log



20 VINlog



==

Gs

R1R3+

R1R3C

1



---------------------------------

s

1

R4C

2



--------------------+





s

1

R1R

3



C

1



--------------------------------------+







ss

C2C3+

R4C2C

3



---------------------------------+







s

1

R3C

1



--------------------+







---------------------------------------------------------------------------------------------------



=

Where:

C

1

R

3

C

3

R

1

R

2

C

2

V

REF

R

4

+

-

EA

V

IN

COMP

5.2.8 FEEDBACK LOOP COMPENSATION

Since the MCP19035 implements a Voltage-Mode
PWM control, a Type-III compensation network is
recommended. Correct placing of poles and zeros
require analysis of the Bode plots for the buck
converter power train.

The frequencies for pole and zero are determined
using Equation 5-20:

EQUATION 5-20: POLE AND ZERO

FREQUENCIES

EQUATION 5-21: PWM MODULATOR GAIN

The Type-III compensation network is represented in

Figure 5-2:

FIGURE 5-1: Bode Plots for Buck Converter Power Train (Representation Using Asymptotes).

The power train of a buck converter that uses voltage
mode control is a second order system. At the LC
resonance frequency, a double pole occurs; this pole
will “push” the gain down with a slope of -40db/decade.
This double pole also introduces a phase lag of -180°.
The compensation network must counteract the effects
of this double pole in order to achieve the stability of the
system.

The Equivalent Series Resistance (ESR) of the output
capacitor introduces a zero that “pushes” the gain and
phase up again. This zero helps the stability of the
system if it occurs before the phase reaches the critical
point of -180°. However, due to the performance criteria
(output voltage ripple, efficiency), the application
requires the use of low ESR capacitors. For capacitors
that have very low ESR (ceramic capacitors), this zero
occurs at high frequency, where the phase reaches the
critical point.

 2012-2013 Microchip Technology Inc. DS22326B-page 23

FIGURE 5-2: Type-III Compensation Network.

MCP19035

Magnitude

(dB)

Frequency
(log scale)

A

OL

0dB

f

Z1

f

Z2

Phase

(deg)

0°

90°

-90°

Frequency

(log scale)

f

P1

f

P2

A

POLE

A

ZERO

f

Z1

1

2



R1R3+C

1



--------------------------------------------------

1

2



R1C

1



------------------------------- -



=

f

Z2

1

2



R4C

2



------------------------------- -=

f

P1

1

2



R

4

C2C

3



C2C3+

------------------- -







---------------------------------------------------

1

2



R4C

3



------------------------------- -



=

f

P2

1

2



R3C

1



------------------------------- -=

A

ZERO

20

R

4

R

1

----- -log



=

A

POLE

20

R

4R1R3

+



R1R

3



------------------------------------log



=

R

2

V

REFR1



V

OUTVREF

–

-------------------------------- -

0.6 R

1



V

OUT

0.6–

---------------------------==

A

PT

CO

A

MOD

40–

f

CO

f

LC

--------





log



=

The Type-III compensation network provides two zeros
and three poles (including origin pole), pushing the
cross-over frequency as high as possible, and boosts
the phase margin of the system to greater than 45°. A
higher bandwidth yields a faster load transient
response. The faster transient response results in a
smaller output voltage overshoot.

The procedure for placing the poles and zeros to
achieve the optimum phase margin are presented
below:

1. Determine the frequency of the double pole

(LC pole) and ESR zero using Equation 5-20.

2. Choose resistor R

(usually between 10 k and

1

100 k). This value is a compromise between
high values for additional capacitors (higher
cost) and possible noise induced problems.

3. Resistor R2 is calculated using Equation 5-25:

EQUATION 5-25: FEEDBACK RESISTOR

DIVIDER

FIGURE 5-3: Bode Plots for Type III Compensation Network (Representation Using Asymptotes).

Assuming C3«C2 and R3«R1, the pole and zero
frequencies can be calculated using Equation 5-22:

EQUATION 5-22: POLE AND ZERO

FREQUENCIES OF THE
COMPENSATION
NETWORK

4. Choose the crossover frequency of the

compensated system. This frequency is
recommended to be between 1/10
the switching frequency (f

th

and 1/5th of

). A higher

SW

crossover frequency will improve the transient
response, but will decrease the phase margin.
For most of the applications, the crossover
frequency is set around 1/10

th

of switching
frequency. This is a reasonable compromise
between simplifying the design of the
compensation loop and achieving a fast
transient response. Since the frequency of the
ESR zero is much higher than LC resonant
frequency, the gain of the power train can be
typically approximated at the crossover
frequency, using Equation 5-26:

EQUATION 5-26: POWER TRAIN GAIN AT

CROSSOVER
FREQUENCY

EQUATION 5-23: ZERO GAIN

The compensated error amplifier must have a
gain equal to A

). Typically, this crossover frequency occurs

(f

EQUATION 5-24: POLE GAIN

CO

between F

and FP1 (see Figure 5-3).

Z2

DS22326B-page 24  2012-2013 Microchip Technology Inc.

at crossover frequency

PTco

MCP19035

C

1

LC

OUT



R

1

--------------------------- -=

R

4

f

CO

f

LC

------- -

1

V

IN

-------- R

1



=

Where:

f

CO

= cross-over frequency for the compensated

system (usually 1/10

th

of fSW)

C22

LC

OUT



R

4

--------------------------- -



=

C

3

1

2



R4f

SW



----------------------------------------- -=

R

3

1



C1f

SW



-------------------------------- -=

5. The first zero of the compensation network must
be placed at the f

frequency. The capacitor C

LC

is calculated using Equation 5-27:

EQUATION 5-27: CAPACITOR C

1

6. The value of the resistor R4 is estimated using

Equation 5-28:

EQUATION 5-28: RESISTOR R

4

7. The second zero of the compensation network
must be placed at half of the f
value of the capacitor C

frequency. The

LC

is calculated in

2

Equation 5-29:

EQUATION 5-29: CAPACITOR C

2

The compensation circuit can be simulated with any

1

available simulator. The values of the components can
be adjusted to meet the initial design parameters
(crossover frequency and phase margin). It is also nec­essary to ensure that the gain of the compensation cir­cuit does not exceed the gain of the error amplifier. Due
to the interactions between poles and zeros, it is highly
recommended to use the design tool provided by
Microchip Technology Inc. to design and analyze the
compensation network.

8. The first pole of the compensation network must
be placed at f

The value of C3 is calculated in

SW.

Equation 5-30:

EQUATION 5-30: CAPACITOR C

3

9. The second pole of the compensation network
must be placed at half of the f
resistor R

is calculated in Equation 5-31:

3

EQUATION 5-31: RESISTOR R

.The value for

SW

3

 2012-2013 Microchip Technology Inc. DS22326B-page 25

MCP19035

C

IN

C

OUT

L

Q

1

Q

2

MCP19035

HDRV

LDRV

PHASE

BOOT

+V

CC

C

BOOT

C

VCC

+V

OUT

SHDN

V

IN

PWRGD

COMP

FB

R

1

R

3

C

1

R

2

C

3

R4

C

2

+V

IN

ON

OFF

R

IN

GND

5.3 Operation with Low Input Voltages

If the application requires an input voltage below 5.5V,
it is recommended to use the alternative schematic
depicted in Figure 5-4.

FIGURE 5-4: Typical Application for Low VIN.

This connection avoids the voltage drop on the internal
voltage regulator, ensuring the correct driving of the
MOSFETs at low input voltage.

Additional care must be exercised when this alternative
schematic is used to minimize the input voltage
ripple/noise. The internal circuitry of the MCP19035
may be affected by the ripple/noise present on the V
pin. The RIN resistor together with C
a low-pass filter for the bias voltage (V
recommended value range for this resistor is between

capacitor form

VCC

voltage). The

CC

CC

2.2 and 10.

DS22326B-page 26  2012-2013 Microchip Technology Inc.

MCP19035

6.0 DESIGN EXAMPLE

This example illustrates the step-by-step design proce­dure for a 12V to 1.8V synchronous buck converter
using the MCP19035 controller. To minimize the design
effort, Microchip provides a design tool that is used to

calculate the component values. See AN1452 - “Using

the MCP19035 Synchronous Buck Converter Design
Tool” for further details (DS01452).

The electrical parameters are detailed in Ta bl e 6 - 1.

TABLE 6-1: DESIGN EXAMPLE ELECTRICAL SPECIFICATION

Parameter Test Conditions Min Nominal Max Unit

Input Voltage (VIN) 8 12 14 V

Output Voltage (V

)0  I

OUT

Line Regulation 8.0V  V
Load Regulation 0A  I

Output ripple (V

Input ripple (V

OUT_RIPPLE

IN_RIPPLE

)I

)I

Output overshoot Step from 3.75A to 11.25A — — 100 mV

Output undershoot Step from 11.25A to 3.75A — — 100 mV

Output current (I

Efficiency V

)0—15A

OUT

=12V, I

IN

 15A — 1.8 — V

OUT

 14V — — 0.5 %

IN

 15A — — 0.5 %

OUT

= 15A — — 30 mV

OUT

=15A — — 0.3 V

OUT

= 10A 90 — — %

OUT

6.0.1 INDUCTOR SELECTION

The inductor must be sized for a typical ripple current
that is around 30% of maximum output current. The
inductor value calculated with Equation 5-1 is 1.16 µH.
To compensate against component tolerance, choose
the next higher standard value 1.5 µH (typically 20% for
high current inductors).

The peak current in the inductor can be calculated with

Equation 5-2, its value being 17.25A. The inductor

must sustain, without saturating, this peak current. To
maintain low-conduction losses, the DC resistance of
the inductor must be as low as possible. Table 6-2
shows some suitable inductors for this application.

TABLE 6-2: SUITABLE INDUCTORS FROM VARIOUS VENDORS

Vendor Part Number

Coilcraft

®

Wurth Elektronik

TDK - EPC

Bourns

®

®

XAL1010-152MEB 1.5 1.76 36.6

®

7443320150 1.5 2.1 27

B82559A0142A013 1.4 1.5 22

SRP1270-1R5M 1.5 2.1 48

Inductance

(µH)

DCR

(m)

I

SAT

(A)

 2012-2013 Microchip Technology Inc. DS22326B-page 27

MCP19035

P

IN

U

OUTIOUTmax



Eff

----------------------------------------- -=

P

LOSS

P

INPOUT

–=

R

DS on

P

LOSS High Side–

I

RMS High Side–

2

----------------------------------------- 0 .3



=

Q

GTotal

P

LOSS High Side–

V

IN MaxIOUTfSW



-------------------------------------------------------0.7



=

6.0.2 INPUT CAPACITOR SELECTION

The converter operates with a maximum duty cycle of

22.5%. A ceramic capacitor (X7R dielectric) with a
10 m ESR (typical) will be used. The minimum
capacitance for input capacitor, calculated in

Equation 5-4, is 32.7 µF. Use two standard 22 µF

capacitors (X7R) rated at 25V

in parallel.

DC

6.0.3 OUTPUT CAPACITOR SELECTION

Based on a step load from 25% to 75% of the maximum
output current, the minimum value for the output capac­itor can be determined with Equation 5-7. The mini­mum value is 456 µF. Choose the next higher standard
value (500 µF). The ESR of the output capacitor will
strongly affect the output voltage ripple. Use five
100 µF standard ceramic capacitors (X7R or X5R
dielectric) rated at 6.3V
final value of the ESR is lower than 5 m. The output
voltage ripple is now estimated with Equation 5-6.

in parallel. The estimated

DC

6.0.4 MOSFETS SELECTION

Before the MOSFET selection, the total losses of the
converter should be estimated. For this application, the
input power can be estimated using Equation 6-1:

EQUATION 6-1: INPUT POWER

TABLE 6-3: ESTIMATION OF THE POWER

LOSSES DISTRIBUTION

Component Losses (%)

High-Side MOSFET 36

Low-Side MOSFET 40

Inductor 10

Input Capacitor 2

Output Capacitor 1

PWM Controller 10

Traces DC Resistance 1

An important part of the total power losses (over 75%)
are dissipated by the MOSFETs.

For the high-side MOSFET, the total amount of losses
(conduction and switching losses) should not exceed

0.72W. This design has a higher conversion ratio
(greater than 7:1), thus most of the losses of the high­side MOSFET will be switching losses. As a rule of
thumb, the switching losses will be considered to be
70% of the total losses.

The conduction losses for the high-side MOSFET are
estimated in Equation 5-10. High-side MOSFET
conduction losses are high at low input voltages. The
maximum R

for the high-side MOSFET is:

DS(on)

The total power losses are estimated in Equation 6-2:

EQUATION 6-2: TOTAL CONVERTER

LOSSES

To achieve the efficiency goal (90%), the total power
losses must be lower than 2W at 10A output current.

Table 6-3 shows how these losses are distributed over

the converter components. The power losses distribu­tion varies with the design parameters. As a rule of
thumb, for designs that have higher conversion ratio
(low duty cycles), the losses for the high-side MOSFET
are mainly switching losses. For the low side, most of
the losses will be the conduction losses.

EQUATION 6-3: MAXIMUM

HIGH-SIDE R

For this design, where I
input voltage and 10A output current, the high-side
MOSFET should have a R

For the high-side MOSFET, most of the losses are
switching losses (70%). The maximum total gate
charge for the high-side MOSFET is:

RMS High-Side

DS(On)

DS(ON)

=3.9A at 12V

lower than 14 m.

EQUATION 6-4: MAXIMUM TOTAL

GATE CHARGE FOR
THE HIGH-SIDE MOSFET

The maximum Total Gate Charge (Q

should be lower than 12 nC (calculated for 10A

V

GS

output current).

G(Total)

) at 4.5V

DS22326B-page 28  2012-2013 Microchip Technology Inc.

MCP19035

R

DS on

P

LOSS Low S ide–

I

RMS Low Side–

2

--------------------------------------- -0.85



=

I

MAX

HS

0.48

R

DS onHS

-------------------------=

I

MAX

LS

0.18

R

DS onLS

------------------------=

For the low-side MOSFET, losses are mainly
conduction losses. As a rule of thumb, the conduction
losses are considered to be 85% of the total losses. For
this design, the maximum power losses (estimated at
12V input voltage and 10A output current) for low-side
should be lower than 0.9W. Estimate the maximum
R

EQUATION 6-5: MAXIMUM RD

for the low-side MOSFET using Equation 6-5:

DS(On)

(ON)

OF

LOW-SIDE MOSFET

In this design, I

RMS Low-Side

voltage, 10A output current and the maximum R
for low-side MOSFET = 7.8 m.

For this design, Microchip's MCP87050 and
MCP87022 high-performance MOSFETs can be used.
Calculate the total losses introduced by these transis­tors using the provided equations. For the high-side
MOSFET (MCP87050), the total loss is 0.66W. The
low-side MOSFET (MCP87022) will dissipate a 0.3W
loss.

= 9.3A at 12V input

DS(On)

6.0.5 BOOTSTRAP CAPACITOR

SELECTION

From Equation 5-19, the value of the Bootstrap
Capacitor should be higher than 276 nF. Choose the
standard value 330 nF ceramic capacitor (X7R) rated

DC

.

at 16 V

6.0.6 DEAD TIME (DT) SELECTION

The MOSFET used in this design has a low Figure of
Merit parameter. The overall efficiency of the converter
can be improved by choosing the MCP19035 with
optimized Dead Time.

The peak current for the low-side MOSFET is:

EQUATION 6-7: MAXIMUM PEAK

CURRENT FOR A
LOW-SIDE MOSFET

For this design, the maximum peak current that flows
into the low-side MOSFET is 81A.

6.0.8 FEEDBACK LOOP COMPENSATION

For this design, the crossover frequency is 30 kHz,
while the resonant frequency of LC tank is 5.88 kHz.
With these parameters, and following the design

procedure described in Section 5.2, Design

Procedure, the value for compensation network

components can be calculated.

TABLE 6-4: COMPENSATION NETWORK

COMPONENTS

Component Value Standard Value

R

1

R

2

R

3

R

4

C

1

C

2

C

3

The components used for the compensation network
must be of good quality and tolerance. The
recommended dielectric for capacitors is C0G and the
tolerance 5%. The recommended tolerance for
resistors is 1%.

20 k 20 k
10 k 10 k

0.774 k 0.75 k

8.6 k 8.2 k

1.37 nF 1.2 nF

6.36 nF 6.8 nF

61 pF 68 pF

6.0.7 OVERCURRENT PROTECTION

THRESHOLDS

The MCP19035 controller provides two fixed threshold
for high and low-side overcurrent protection circuits.
These thresholds are 480 mV (typical) for high-side
and 180 mV (typical) for the low-side. The peak current
for the high-side is:

EQUATION 6-6: MAXIMUM PEAK

CURRENT FOR A
HIGH-SIDE MOSFET

6.0.9 LAYOUT RECOMMENDATIONS

Good printed circuit board layout techniques are
important to any switching circuitry, and switching
power supplies are no different. Here are the guidelines
for the PCB layout:

• The exposed pad of MCP19035 DFN case is the
only connection to the internal device ground.
Connect this pad directly to the board ground
plane.

• Place at least four vias in the exposed pad land to
help remove heat from the device.

• Use separate grounds for power and signal paths.
Keep high current paths away from sensitive
components and nodes (ex. feedback and

For this design, the maximum peak current that flows
into the high-side MOSFET is 87A.

compensation network components).

• Four layer PCBs are highly recommended to
obtain optimum results regarding noise/EMI. Use
an internal layer as ground plane.

 2012-2013 Microchip Technology Inc. DS22326B-page 29

MCP19035

C

IN

C

OUT

L1

Q

1

Q

2

R

L

MCP19035

HDRV

LDRV

PHASE

I

IN

I

SR

I

HDRV

I

LDRV

I

RR

GND

Where:

I

IN

= Input Converter current

I

SR

= Current through the Synchronous Rectifier (SR) MOSFET

I

HDRV and ILDRV

= MOSFET drivers’ currents

IRR= Current produced by the Reverse Recovery of the SR MOSFET body diode

• For double layer boards, a single ground plane
(usually the bottom) is recommended.

• Use short, wide traces for the MOSFET’s gate
drive connection (LDRV and HDRV signals).

• Place the main MOSFET (control/high-side MOS­FET) as close as possible to the input capacitors.

• Minimize the connections between MOSFETs, the
inductor and the MCP19035 case (PHASE node).
Place this node over a ground plane to minimize
the radiated noise.

• Place the compensation network components

near the MCP19035 case and connect these
components to a low noise ground (signal
ground).

• Locate the V

decoupling capacitor close to the

IN

MCP19035 case.

• Locate the Bootstrap Circuit capacitor close to the
MCP19035 case.

• Minimize the area of high frequency current loops.

Figure 6-1 helps the PCB designer to identify the main

high frequency current paths for the Synchronous Buck
Converter.

FIGURE 6-1: High Frequency Current Paths.

All these currents contain high-frequency components
and can produce EMI. Minimizing the area of these
loops will reduce the radiated noise.

The Reverse Recovery of the SR MOSFET Body Diode
current is an important source of noise and EMI. This
current, although very short (less than 10 ns), can
easily reach a few hundred amps, especially when
using low ESR capacitors for input bypass and very fast
MOSFETs for switching transistors. If this current
passes through a path that has a high inductance, it will
produce an intense voltage ringing.

DS22326B-page 30  2012-2013 Microchip Technology Inc.

For noise sensitive applications (for example, RF
applications) the excessive voltage ringing in the
PHASE node produced by Reverse Recovery of SR
MOSFET Body Diode can be reduced by placing a low­value resistor in series with the bootstrap capacitor.
This resistor will slow down the high-side MOSFET
during low-to-high transition, reducing the slew rate of
the SW node signal. The recommended value for this
resistor is between 2.2 and 10, and should be
determined by lab measurements. The penalty of
including this resistor is an efficiency reduction. It
should, however, be no more than 0.5%.

Figures 6-2 and 6-3 show the difference between

PHASE node voltage with and without this resistor.

MCP19035

FIGURE 6-2: SW (PHASE) Node With Boot Capacitor Series Resistor.

FIGURE 6-3: SW (PHASE) Node Without Boot Capacitor Series Resistor.

 2012-2013 Microchip Technology Inc. DS22326B-page 31

SHDN

1

FB

2

COMP

3

VIN

4

PWRGD

5

VCC

6

LDRV

7

BOOT

8

PHASE

9

HDRV

10

GND

11

U1

MCP19035

Q1

MCP87050

Q2

MCP87022

PGND

PGND

PGND

SGND

PGND

PGND

SGND PGND

PGND

1.5PH

L1

10k

R2

1M

R5

6.8nF

C2

20k

R1

22PF

C10

22PF

C11

100PF

C7

100PF

C8

100PF

C9

4.7PF

C13

1PF

C12

12

J1

12

J2

1.2nF

C1

750

R3

8.2k

R4

68pF

C3

VIN

VOUT

100PF

C5

100PF

C6

100k

R6

0.33PF

C4

DS22326B-page 32  2012-2013 Microchip Technology Inc.

6.0.10 SCHEMATIC AND BILL OF MATERIALS

MCP19035

FIGURE 6-4: Schematic Diagram.

MCP19035

TABLE 6-5: BILL OF MATERIALS

Qty Reference Value Manufacturer

®

1 C1 1.2 nF KEMET

Electronic Corp.

1 C2 6.8 nF KEMET

Electronic Corp.

1 C3 68 pF KEMET

Electronic Corp.

1 C4 0.33 µF MURATA

Electronics

5 C5, C6,

C7, C8, C9

2 C10, C11 22 µF MURATA

1 C12 1 µF TDK Corporation CGA4J3X7R1V105K Cap. Ceramic 1 µF 35V 10% X7R 0805

1 C13 4.7 µF TDK Corporation C2012X5R1E475K Cap. Ceramic 4.7 µF 25V X5R 0805

2 J1, J2 On-Shore

1L1 1.5µHWurth

1 Q1 Microchip

1 Q2 Microchip

1R1 20 k Panasonic

1R2 10 k Panasonic - ECG ERJ-3GEYJ103V Res. 10k Ohm 1/10W 5% 0603 SMD

1R3 750 Vishay

1R4 8.2k Panasonic - ECG ERJ-3EKF8201V Res. 8.2k Ohm 1/10W 1% 0603 SMD

1R5 1M Panasonic - ECG ERJ-3EKF1004V Res. 1M Ohm 1/10W 1% 0603 SMD

1R6 100k Panasonic - ECG ERJ-3EKF1003V Res. 100k Ohm 1/10W 1% 0603 SMD

1 U1 Microchip

100 µF TDK

Electronics

Technology Inc.

Electronik Group

Technology Inc.

Technology Inc.

Intertechnology

Technology Inc.

®

®

Corporation C3225X5R0J107M Cap. Ceramic 100 µF 6.3V 20% X5R

®

- ECG ERJ-3EKF2002V Res. 20k Ohm 1/10W 1% 0603 SMD

®

/Dale

Manufacturer Part

Number

C0603C122J1GACTU Cap. Ceramic 1200 PF 100V 5% NP0

0603

C0603C682J5GACTU Cap. Ceramic 6800 PF 50V 5% NP0

0603

C0603C680J1GACTU Cap. Ceramic 68 PF 100V 5% NP0 0603

GRM188R71C334KA01D Cap. Ceramic 0.33 µF16V 10% X7R

0603

1210

GRM32ER71E226KE15L Cap. Ceramic 22 µF 25V 10% X7R 1210

ED120/2DS Terminal Block 5.08 mm Vert. 2 POS

7443320150 Inductor Power 1.5 µH 19.5A SMD

MCP87050T-U/MF High-Speed N-Channel Power MOSFET,

5x6 mm PDFN

MCP87022T-U/MF High-Speed N-Channel Power MOSFET,

5x6 mm PDFN

CRCW0603750RFKEA Res. 750 OHM 1/10W 1% 0603 SMD

MCP19035-AAABE/MF High Speed Synchronous

Buck Controller

Description

 2012-2013 Microchip Technology Inc. DS22326B-page 33

MCP19035

NOTES:

DS22326B-page 34  2012-2013 Microchip Technology Inc.

7.0 PACKAGING INFORMATION

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)

* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

3

e

Part Number Code

MCP19035-AAAAE/MF BAFG

MCP19035T-AAAAE/MF BAFG

MCP19035-AAABE/MF BAFP

MCP19035T-AAABE/MF BAFP

MCP19035-BAAAE/MF BAFH

MCP19035T-BAAAE/MF BAFH

MCP19035-BAABE/MF BAFQ

MCP19035T-BAABE/MF BAFQ

BAFG

1209

256

10-Lead DFN (3x3x0.9 mm)

Example:

7.1 Package Marking Information

MCP19035

3

e

 2012-2013 Microchip Technology Inc. DS22326B-page 35

MCP19035

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22326B-page 36  2012-2013 Microchip Technology Inc.

MCP19035

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2012-2013 Microchip Technology Inc. DS22326B-page 37

MCP19035

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22326B-page 38  2012-2013 Microchip Technology Inc.

APPENDIX A: REVISION HISTORY

Revision B (March 2013)

The following is the list of modifications:

1. Added the 600 kHz option Switching Frequency
parameter and related information throughout
the document.

2. Updated the DC Electrical Characteristics table
to reflect the 600 kHz option for the Switching
Frequency parameter.

3. Updated Figure 2-1, Figure 2-3, and

Figure 2-10.

4. Updated Section 4.4 “Internal Oscillator”.

5. Updated the Switching Frequency value in

Equation 4-1.

6. Updated Section 4.11 “Soft Start”.

7. Updated Figure 4-3.

8. Added a note to Section 4.12 “Pre-Bias Load

Start-up”.

9. Updated Section 5.2.1 “Switching Frequency

and the Maximum Conversion Ratio”.

10. Updated Section 7.1 “Package Marking Infor-

mation” with the 600 kHz Switching Frequency

option markings.

11. Updated the Product Identification System page
with the 600 kHz Switching Frequency option
marking information.

MCP19035

Revision A (November 2012)

• Original Release of this Document.

 2012-2013 Microchip Technology Inc. DS22326B-page 39

MCP19035

NOTES:

DS22326B-page 40  2012-2013 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

PART NO. X /XX-X

Switching PackageTemperature

Range

Device

Device: MCP19035: High-Speed Synchronous Buck Controller

MCP19035T: High-Speed Synchronous Buck Controller

(Tape and Reel)

Switching
Frequency:

A=300kHz
B=600kHz

Reference Voltage: A=600mV

LDRV OC
Threshold:

A=200mV

Dead Time: A =20 ns

B=12ns

Temperature Range: E= -40C to +125C (Extended)

Package: MF = Plastic Dual Flat, No Lead Package - 3x3x0.9

mm, 10-Lead

Examples:

a) MCP19035-AAAAE/MF: 300 kHz Switching Freq.,

600 mV V

REF

, 200 mV
LDRV OC Threshold,
20 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

b) MCP19035T-AAAAE/MF: Tape and Reel,

300 kHz Switching Freq.,
600 mV V

REF

, 200 mV

LDRV OC Threshold,
20 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

c) MCP19035-AAABE/MF: 300 kHz Switching Freq.,

600 mV V

REF

, 200 mV

LDRV OC Threshold,
12 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

d) MCP19035T-AAABE/MF: Tape and Reel,

300 kHz Switching Freq.,
600 mV V

REF

, 200 mV
LDRV OC Threshold,
12 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

e) MCP19035-BAAAE/MF: 600 kHz Switching Freq.,

600 mV V

REF

, 200 mV

LDRV OC Threshold,
20 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

f) MCP19035T-BAAAE/MF: Tape and Reel,

600 kHz Switching Freq.,
600 mV V

REF

, 200 mV

LDRV OC Threshold,
20 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

g) MCP19035-BAABE/MF: 600 kHz Switching Freq.,

600 mV V

REF

, 200 mV

LDRV OC Threshold,
12 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

h) MCP19035T-BAABE/MF: Tape and Reel,

600 kHz Switching Freq.,
600 mV V

REF

, 200 mV
LDRV OC Threshold,
12 ns Dead Time,
Extended Temperature,
10LD 3x3 DFN Package

Frequency

X

Reference
Voltage

X

LDRV OC
Threshold

X

Dead
Time

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

MCP19035

 2012-2013 Microchip Technology Inc. DS22326B-page 41

MCP19035

NOTES:

DS22326B-page 42  2012-2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, K
PICSTART, PIC
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their
respective companies.

© 2012-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-62077-089-4

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

32

logo, rfPIC, SST, SST Logo, SuperFlash

QUALITY MANAGEMENT S

 2012-2013 Microchip Technology Inc. DS22316B-page 43

Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

®

MCUs and dsPIC® DSCs, KEELOQ

®

code hopping

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11/29/12

DS22316B-page 44  2012-2013 Microchip Technology Inc.