Page 1
M48T59
M48T59Y/M48T59V
64 Kbit (8Kb x8) TIMEKEEPER® SRAM
PRELIMINARY DATA
■ INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
■ FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
■ AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■ WRITE PROTECT VOLTAGES
(V
= Power-fail Deselect Voltage):
PFD
– M48T59: 4.5V ≤ V
– M48T59Y: 4.2V ≤ V
– M48T59V: 2.7V ≤ V
■ SELF-CONTAINED BATTERY and CRYSTA L
PFD
PFD
PFD
≤ 4.75V
≤ 4.5V
≤ 3.0V
in the CAPHAT DIP PACKAGE
■ PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT
®
TOP
(to be Ordered Separately)
■ SOIC PACKAGE PROVIDES D IREC T
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
■ MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
■ PROGRAMM ABLE A L A R M O U TPUT ACTIVE
in the BATTERY BACK-UP MODE
■ BATTERY LOW FLAG
SNAPHAT (SH)
Battery/Crytstal
28
28
1
SOH28 (MH)
Figure 1. Logic Diagram
V
CC
13
A0-A12
1
PCDIP28 (PC)
Battery/Crystal
CAPHAT
8
DQ0-DQ7
Table 1. Signal Names
A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
IRQ
/FT
RST
E
G
W
V
CC
V
SS
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Interrupt / Frequency Test
Output (Open Drain)
Power Fail Reset Output
(Open Drain)
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
W
E
G
M48T59
M48T59Y
M48T59V
V
SS
IRQ/FT
RST
AI01380E
1/21
Page 2
M48T59, M48T59Y, M48T59V
Figure 2A. DIP Connections
RST V
1
A12
2
3
A7
4
A6
5
A5
6
A4
7
A3
A2
A1
A0
DQ0
8
9
10
11
M48T59
M48T59Y
12
13
DQ2
14
SS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AI01381D
CC
W
IRQ/FT
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
Table 2. Absolute Maximum Ratings
(1)
Figure 2B. SOIC Connections
RST V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ2
SS
1
2
3
4
5
6
7
M48T59Y
8
M48T59V
9
10
11
12
13
14
AI01382E
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
W
IRQ/FT
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V
Symbol Parameter Value Unit
T
A
T
STG
T
SLD
V
IO
V
CC
I
O
P
D
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowe d on any pin while i n the Batter y Back-up mod e.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
(2)
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V
Supply Voltage
Output Current 20 mA
Power Dissipation 1 W
rating only and functional opera tion of the devi ce at these or any other conditions above those i ndi cated in th e operational section
of this spec ification is not im plied. Exposure t o the abso lute max imum rat ing cond itions for extende d period s of tim e may affe ct
reliability.
Grade 1 0 to 70
Grade 6 –40 to 85
–40 to 85 °C
M48T59/M48T59Y –0.3 to 7
M48T59V –0.3 to 4.6
°C
V
V
PFD
≤ V
CC
or
or
SO
(1)
(min)
(2)
E G W DQ7-DQ0 Power
V
IH
V
IL
V
IL
V
IL
X X X High Z CMOS Standby
X X X High Z Battery Back-up Mode
Table 3. Operating Modes
Mode
Deselect
Write
Read
Read
Deselect
Deselect
Note: 1. X = VIH or VIL; VSO = Battery Back-up Swit ch ov er Volta ge.
2. See T able 7 for deta ils.
4.75V to 5.5V
4.5V to 5.5V
3.0V to 3.6V
V
to V
SO
2/21
X X High Z Standby
X
V
IL
V
IH
V
IL
V
IH
V
IH
D
D
OUT
IN
Active
Active
High Z Active
Page 3
Figure 3. Block Diagram
M48T59, M48T59Y, M48T59V
IRQ/FT
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
POWER
LITHIUM
CELL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
CC
RSTV
DESCRIPTION
®
The M48T59/59Y/59V TIMEKEEPER
RAM is an
8Kb x8 non-volatile static RAM and real time clock.
The monolithic chip is available in two special
packages to provide a highly integrated battery
backed-up memory and real time clock solution.
The M48T59/59Y/59V is a non-volatile pin and
function equivalent to any JEDEC standard 8Kb x8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
write timing or limitations on the number o f writes
that can be performed.
The 28 pin 600mil DIP CAPHAT™ houses the
M48T59/ 5 9Y /59V silic o n with a quartz c ry st al and
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing cont aining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and c rystal dam age due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
16 x 8 BiPORT
SRAM ARRAY
A0-A12
DQ0-DQ7
E
W
G
AI01383D
V
PFD
8176 x 8
SRAM ARRAY
V
SS
Table 4. AC Measurement Conditions
Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Figure 4. AC Testing Load Circuit
DEVICE
UNDER
TEST
CL includes JIG capacitance
Note: Excluding open-drain output pins.
645Ω
CL = 100pF
AI02325
1.75V
3/21
Page 4
M48T59, M48T59Y, M48T59V
Table 5. Capacitance
(T
= 25 °C)
A
(1, 2)
Symbol Parameter Test Condition Min Max Unit
C
C
IO
Note: 1. Effective capacitance measured with power suppl y at 5V.
2. Sampled only, not 100% tested.
3. Outputs desele ct ed.
Input Capacitance
IN
(3)
Input / Output Capacitance
V
V
OUT
IN
= 0V
= 0V
10 pF
10 pF
Table 6. DC Characteristics
(T
= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
Symbol Parameter Test Condition
(1)
I
LI
I
LO
I
I
I
V
V
Input Leakage Current
(1)
Output Leakage Current
Supply Current Outputs open 50 30 mA
CC
Supply Current (Standby)
CC1
TTL
Supply Current (Standby)
CC2
CMOS
(2)
Input Low Voltage –0.3 0.8 –0.3 0.8 V
IL
Input High Voltage 2.2
IH
Output Low Voltage
V
OL
Output Low Voltage (IRQ
(3)
and RST
V
Note: 1. Outputs deselected.
Output High Voltage
OH
2. Negativ e s p i k e s of –1V allo wed for up to 10ns onc e pe r cycle .
3. The I RQ
)
/FT and RS T pi ns are Open Drain.
/FT
0V ≤ V
IN
0V ≤ V
OUT
= V
E
= VCC – 0.2V
E
I
= 2.1mA
OL
IOL = 10mA
I
= –1mA
OH
≤ V
≤ V
IH
CC
CC
M48T59/Y M48T59V
Min Max Min Max
±1 ±1 µA
±1 ±1 µA
32mA
31mA
V
CC
+ 0.3
2
VCC + 0.3
0.4 0.4 V
0.4 0.4 V
2.4 2.4 V
Unit
V
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(TA = 0 to 70 °C or –40 to 85 °C)
Symbol Parameter Min Typ Max Unit
M48T59 4.5 4.6 4.75 V
V
PFD
V
SO
t
DR
Note: 1. All voltages referenced to VSS.
2. Usi ng larger M4T 32-BR12SH6 SNAPHA T top (recomm ended for I ndustrial Te m perature Range - grade 6 device).
4/21
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage
Expected Data Retention Time (at 25 °C)
M48T59Y 4.2 4.35 4.5 V
M48T59V 2.7 2.9 3.0 V
M48T59/Y 3.0 V
V
M48T59V
Grade 1
Grade 6
10
7
(2)
PFD
–100mV
V
YEARS
YEARS
Page 5
M48T59, M48T59Y, M48T59V
Table 8. Power Down/Up AC Characteristics
(T
= 0 to 70 °C or –40 to 85 °C)
A
Symbol Parameter Min Max Unit
t
PD
(1)
t
F
t
FB
t
R
t
RB
t
REC
Note: 1. V
2. V
3. t
E or W at VIH before Power Down
V
(max) to V
PFD
(2)
V
(min) to VSS VCC Fall Time
PFD
V
(min) to V
PFD
VSS to V
(3)
V
(max) to V
PFD
(min).
es V
PFD
(min) to VSS fall time of less than tFB may cause corruption of RAM data.
PFD
(min) = 20ms for industrial temperature grade 6 device.
REC
PFD
(max) to RST High
PFD
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC pass-
PFD
(min) VCC Fall Time
PFD
(max) VCC Rise Time
PFD
(min) VCC Rise Time
Figure 5. Power Down/Up Mode AC Waveforms
V
CC
V
(max)
PFD
V
(min)
PFD
VSO
tPD
tF
tFB
0 µs
300 µs
M48T59/Y 10 µs
M48T59V 150 µs
10 µs
1µs
40 200 ms
tR
tRB
tDR
tREC
RST
INPUTS
OUTPUTS
RECOGNIZED RECOGNIZED
VALID VALID
(PER CONTROL INPUT) (PER CONTROL INPUT)
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For t he 2 8 le ad S OIC , t he ba ttery/crystal package (i.e. SNAPHAT) part number
is "M4T28-BR12SH" or “M4T32-BR12SH”.
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lithium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T59/59Y/59V are integrated on one silicon
chip.
DON'T CARE
HIGH-Z
AI03258
The two circuits are interconnected at the upper
eight memory locations to provide user accessible
BYTEWIDE™ clock information in the by tes with
addresses 1FF8h-1FFFh. The clock locations
contain the century, year, m ont h, d ate, day , hour,
minute, and second in 24 hour BCD format (except
for the century). Corrections for 28, 29 (leap year),
30, and 31 day months are made a utomatically.
Byte 1FF8h is the clock control register. This b yte
controls user access to the clock information and
also stores the clock calibration setting.
5/21
Page 6
M48T59, M48T59Y, M48T59V
Table 9. Read Mode AC Characteristics
(T
= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
M48T59/M48T5 9Y/M 48T5 9V
Symbol Parameter
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXQX
Note: 1. CL = 100pF (see Fig 4).
2. C
Read Cycle Time 70 ns
(1)
Address Valid to Output Valid 70 ns
(1)
Chip Enable Low to Output Valid 70 ns
(1)
Output Enable Low to Output Valid 35 ns
(2)
Chip Enable Low to Output Transition 5 ns
(2)
Output Enable Low to Output Transition 5 ns
(2)
Chip Enable High to Output Hi-Z 25 ns
(2)
Output Enable High to Output Hi-Z 25 ns
(1)
Address Transition to Output Transition 10 ns
= 5pF (see Fig 4).
L
Figure 6. Read Mode AC Waveforms.
Unit-70
Min Max
A0-A12
E
G
DQ0-DQ7
Note: Write Enable (W
6/21
) = High.
tAVAV
VALID
tAVQV tAXQX
tELQV
tELQX
tGLQX
tGLQV
tGHQZ
VALID
tEHQZ
AI01385
Page 7
M48T59, M48T59Y, M48T59V
Table 10. Write Mode AC Characteristics
(T
= 0 to 70 °C or –40 to 85 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V or 3.0V to 3.6V)
A
M48T59/M48T 59Y/M 48T59V
Symbol Parameter
t
AVAV
t
AVWL
t
AVEL
t
WLWH
t
ELEH
t
WHAX
t
EHAX
t
DVWH
t
DVEH
t
WHDX
t
EHDX
(1, 2)
t
WLQZ
t
AVWH
t
AVE1H
(1, 2)
t
WHQX
Note: 1. CL = 5pF (see Fig 4).
2. If E
Write Cycle Time 70 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Chip Enable Low 0 ns
Write Enable Pulse Width 50 ns
Chip Enable Low to Chip Enable High 55 ns
Write Enable High to Address Transition 0 ns
Chip Enable High to Address Transition 0 ns
Input Valid to Write Enable High 30 ns
Input Valid to Chip Enable High 30 ns
Write Enable High to Input Transition 5 ns
Chip Enable High to Input Transition 5 ns
Write Enable Low to Output Hi-Z 25 ns
Address Valid to Write Enable High 60 ns
Address Valid to Chip Enable High 60 ns
Write Enable High to Output Transition 5 ns
goes low simultaneously with W going l ow, the output s remain in the h i gh i m pedance state.
Unit-70
Min Max
The eight clock bytes are not the actual clock
counters themselves; they are memory locat ions
consisting of BiPORT™ read/ write memory cells.
The M48T59/59Y/59V includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T59/59Y/59V also ha s its own P ower-fail
Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance
condition. When V
is out of tolerance, the circuit
CC
write protects the S RAM, p roviding a high degree
of data security in the midst of unpredictable s ystem operation brought on by low V
. As VCC falls
CC
below approximately 3V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
READ MODE
The M48T59/59Y/59V is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes
of data is to be acces sed. Valid data will be available at the Data I/O pi ns within Address Access
time (t
stable, providing that the E
are also satisfied. If the E
) after the last address input s ignal is
AVQV
and G access times
and G access times are
not met, valid data will be available after the latter
of the Chip Enable Access time (t
Enable Access time (t
GLQV
).
ELQV
) or Output
The state of the eight t hree-s tate Da ta I/O s i gnals
is controlled by E
ed before t
indeterminate state until t
puts are changed while E
and G. If the outputs are activat-
, the data lines will be driven to an
AVQV
. If the Ad dres s In-
AVQV
and G remain active,
output dat a will rem ain v alid for Outp ut Dat a Hold
time (t
) but will go indeterminate until the next
AXQX
Addr e ss Access.
7/21
Page 8
M48T59, M48T59Y, M48T59V
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
A0-A12
tAVEL
E
tAVWL
W
tWLQZ
DQ0-DQ7
VALID
tAVWH
tWLWH
Figure 8. Chip Enable Controlled, Write AC Waveforms
tDVWH
tWHAX
tWHQX
tWHDX
DATA INPUT
AI01386
8/21
A0-A12
E
W
DQ0-DQ7
tAVEL
tAVWL
tAVAV
VALID
tAVEH
tELEH
DATA INPUT
tDVEH
tEHAX
tEHDX
AI01387B
Page 9
M48T59, M48T59Y, M48T59V
WRITE MODE
The M48T59/59Y/59V is in the Write Mode whenever W
enced from the latter occurring falling edge of W
E
of W
throughout the cycle. E
a minimum of t
and E are low. The start of a write is refer-
or
. A write is terminated by the earlier rising edge
or E. The addresses must be held valid
or W must return high for
from Chip Enable or t
EHAX
WHAX
from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid t
prior to the end of write and remain valid for t
DVWH
WHDX
afterward. G should be kept high during write cycles to avoid bus contention; although, if the output
bus has been activated by a low on E
on W
will disable the outputs t
WLQZ
and G a low
after W falls.
DATA RETENTION MODE
With valid V
applied, the M48T59/59Y/59V op-
CC
erates as a conventional BYT EWIDE stat ic RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V
falls with in the V
CC
PFD
(max ), V
(min) window. All outputs become high impedance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V
(min), the user can be as-
PFD
sured the memory will be in a write protected state,
provided the V
fall time is not less than tF. The
CC
M48T59/59Y/59V may respond to transient noise
spikes on V
that reach into the deselect window
CC
Table 11. Register Map
Address
Data
D7 D6 D5 D4 D3 D2 D1 D0
1FFFh 10 Years Year Year 00-99
1FFEh 0 0 0 10 M Month Month 01-12
1FFDh 0 0 10 Date Date Date 01-31
1FFCh 0 FT CB CEB 0 Day Century/Day 00-01/01-07
1FFBh 0 0 10 Hours Hours Hour 00-23
Function/Rang e
BCD Format
PFD
1FFAh 0 10 Minutes Minutes Minutes 00-59
1FF9h ST 10 Seconds Seconds Seconds 00-59
1FF8h W R S Calibration Control
1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog
1FF6hAFEYABEYYYYYInterrupts
1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31
1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23
1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59
1FF2h RPT1 Alarm 10 Seconds Alar m Seco nds A lar m Secon ds 00-59
1FF1hYYYYYYYY Unused
1FF0hWDFAFZBLZZZZ Flags
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
Z = ’0’ and are Read onl y
AF = Alarm Flag
BL = Battery Low
WDS = Watch dog Steering Bit
BMB0-BMB4 = Watchdog M ultiplie r B i ts
RB0-RB1 = Watchdog Re s oluti on Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1- R PT4 = Alarm Repe at Mode Bits
WDF = Watchdog Flag
CEB = Cent ury Enable Bit
CB = Century Bit
9/21
Page 10
M48T59, M48T59Y, M48T59V
during the time the device is sampling V
. There-
CC
fore, decoupling of the power supply lines is recommended.
When V
drops below VSO, the control circuit
CC
switches power to the internal battery which preserves data and powers the clock. The internal
button cell w ill maintain data in the M48T59/5 9Y/
59V for an accum ulated period of at leas t 7 years
when V
turns and V
is less than VSO. As system pow er re-
CC
rises above VSO, the battery is dis-
CC
connected, and the power supply is switched to
external V
V
reaches V
CC
. Deselect continues for t
CC
PFD
(max).
REC
after
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER-ON RESET
The M48T59/59Y/59V continuously monitors V
When V
the RST
power-up for 40ms to 200ms after V
V
PFD
falls to the power fail detect trip point,
CC
pulls low (open drain) and remains low on
. RST is valid for all VCC conditions. The RST
CC
CC
passes
pin is an open drain output and an appropriate resistor to V
should be chosen to control rise time.
CC
PROGRAMMABLE INTERRUPTS
The M48T59/59Y/59V provides two programmable interrupts; an alarm and a watchdog. When an
interrupt condition occurs, the M48T59/59Y/59V
sets the appropriate flag bit in the flag register
1FF0h. The interrupt enable bits in (AFE and ABE)
in 1FF6h and the Watchdog Steering (WDS) bit in
1FF7h allow the interrupt to activate the IRQ
/FT
pin.
The interrupt flags and the IRQ
/FT output are
cleared by a read to the flags register. An interrupt
condition reset will not occur unless the addresses
are stable at the flag location for at least 15ns
while the divice is in the read mode as shown in
Figure 11.
The IRQ
/FT pin is an open drain output and requires a pull-up resistor (10kΩ recomme nded) to
V
. The pin remains in the high impedance state
CC
unless an interrupt occurs or the frequency test
mode is enabled.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIMEKEEPER cel ls in the R AM a r ra y are onl y d a ta registers, and not the actual clock counters, updating
.
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control register (1FF8h). As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
Setting the C l ock
Bit D7 of the Control register (1FF8h) is the
WRITE bit. Setting the WR ITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER r e g -
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
10/21
AI00594B
Page 11
M48T59, M48T59Y, M48T59V
isters. The user can then loa d them with the correct day, date, and time data in 24 hour BCD
format (see Table 12). Resetting the WRITE bit to
a ’0’ then transfers the values of all time registers
(1FF9h-1FFFh) to the actual TIMEKEEPER
counters and allows normal operation to re sume.
After the WRITE bit is reset, the next clock update
will occur within approximately one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ‘0’ .
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T 59/59Y/59V in
the DIP package, is shipped from
STMicroelectronics with the STOP bit set to a '1'.
When reset to a '0', the M48T59/59Y/59V oscillator starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT), the STOP bit (ST) or the CENTURY ENABLE bit (CEB).
Calib ratin g t h e C lock
The M48T59/59Y/59V is driven by a quartz controlled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per m illion) osc illator f requency error at 25°C, which equates to about ±1.53 minutes
per month. With the c alibration bits properly set,
the accuracy of each M48T59/59Y /59V improves
to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips
compensate for crystal frequency and temperature shift error with cumbersome trim capacitors.
The M48T59/59Y/59V design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Figure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five bit Calibration byte found in the
Control Register. Adding counts speeds the clock
up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control r egister (1FF8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 m inute
Figure 10. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0 10203040506070
∆F
F
Temperature °C
= -0.038 (T - T
ppm
2
C
T0 = 25 °C
)2 ± 10%
0
80–10–20–30–40
AI00999
11/21
Page 12
M48T59, M48T59Y, M48T59V
cycle. The first 62 m inutes i n t he c ycle m ay , onc e
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, t he first 12 will be affected,
and so on.
Therefore, each cal ibration step has the effect of
adding 512 or subtracting 256 oscillator cycles; for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the cal ibration registe r. Ass um ing that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 in crements in the Calibration by te
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T59/59Y/59V may
require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the final product is packaged in a non-user serviceable
enclosure. All the d esigner has t o do i s provide a
simple utility that accesses the Calibration byte.
The second approach is better suit ed to a manufacturing environment, and involves the use of the
FT pin. The pin will toggle at 512Hz when the
IRQ/
Stop bit (D7 of 1FF9h) is '0', the FT bit (D6 of
1FFCh) is '1', the AFE bit (D7 of 1FF6h) is '0', and
the Watchdog Steering bit (D7 of 1FF7h) i s '1' or
the Watchdog Register is reset (1FF7h = 0).
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024
Hz would indicate a +20 ppm oscillator frequency
error, requiring a –10 (WR001010) to be loaded
into the Calibration Byte for correction. Not e that
setting or changing the Calibration Byte does not
affect the Frequency test output frequency.
The IRQ
/FT pin is an open drain out put which requires a pull-up resistor for proper operation. A
500-10kΩ resistor is recommended in order to
control the rise time. The FT bit is cleared on power-down.
For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration".
SETTING ALARM CLOCK
Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a
prescribed time on a specific day of the month or
repeat every month, day, hour, minute, or second.
It can also be programmed to go off while the
M48T59 is in the battery back-up mode of operation to serve as a system wake-up call.
RPT1-RPT4 put the alarm in the repeat mode of
operation. Table 12 shows the possible configurations. Codes not listed in the table default to the
once per second mode t o qu ick ly alert t he user of
an incorrect alarm setting.
Table 12. Alarm Repeat Mode
RPT4 RPT3 RPT2 RPT1 Alarm Activated
1 1 1 1 Once per Second
1 1 1 0 Once per Minute
1 1 0 0 Once per Hour
1 0 0 0 Once per Day
0 0 0 0 Once per Month
Figure 11. Interrupt Reset Waveforms
A0-A12
ACTIVE FLAG BIT
IRQ/FT
12/21
15ns Min
ADDRESS 1FF0h
HIGH-Z
AI01388B
Page 13
M48T59, M48T59Y, M48T59V
Note: User must transition address (or toggle chip
enable) to see Flag bit change.
When the clock information matches the alarm
clock settings based on the m atch criteria d efined
by RPT1-RPT4, AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condition activa tes the IRQ
/FT pin. To disable alarm,
write ‘0’ to the Alarm Date register and RPT1-4.
The alarm flag and the I RQ
/FT output are cleared
by a read to the Flags register.
The IRQ
tery back-up mode. The IRQ
/FT pin can also be activated in the bat-
/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at syst em
boot-up to determine if an alarm was generated
while the M48T59 was in the deselect mode during
power-up. Figure 12 illustrates the b ack-up mode
alarm timing.
Figure 12. Back-up Mode Alarm Waveforms
WATCHDOG T IME R
The watchdog timer can be used to detect an outof-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the eight bit Watchdog Reg ister (Address 1FF7h). The five bits (BMB4-BMB0) store a
binary multiplier and the two lower order bits (RB1RB0) select the resol ution, where 00 = 1/16 sec ond, 01 = 1/4 s econd, 10 = 1 s econd, an d 11 = 4
seconds. The amount of time-out is then determined to be the mult iplication of the f ive bit multiplier value with the resolution. (For example:
writing 00001110 in the Watchdog Register = 3 x 1
or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T59 sets the WDF
(Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset.
WDF is reset by reading the F lags Register (Address 1FFOh).
V
CC
V
(max)
PFD
V
(min)
PFD
V
SO
ABE, AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
tREC
HIGH-Z
AI03254B
13/21
Page 14
M48T59, M48T59Y, M48T59V
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit. When set to a ’0’, the
watchdog will activate the IRQ
/FT pin when timedout. When WDS is set to a ’1’, the watchdog will
output a negative pulse on the RST
pin for a duration of 40ms to 200ms. The Watchdog register and
the FT bit will reset to a ’0’ at the end of a watchdog
time-out when the WDS bit is set to a ’1’.
The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Registe r.
The time-out period then st arts over. The watchdog timer is disabled by writing a value of
00000000 to the eight bits in the Watchdog Register. The watchdog function is automatically disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set
to output to the IRQ
/FT pin and the frequency test
function is activated, the watchdog or al arm function prevails and the frequency test function is denied.
BATTER Y LO W FLAG
The M48T59/59Y/59V automatically performs periodic battery voltage monitoring upon power-up
and at factory-programmed time intervals of 24
hours (at day rollover) as long as the device is
powered and the oscillator is running. The Battery
Low flag (BL), Bit D4 of the f lags Regist er 1F F0h,
will be asse rted high if the interna l or SNAPHAT
battery is found to be less than approximately
2.5V. The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests, either during the next
power-up sequence or the next scheduled 24-hour
interval.
If a battery low is generated during a power-up sequence, this indicates that the battery v oltage is
below 2.5V (approximately), which may be insufficient to maintain data integrity. Data should be
considered suspect and verified as correct. A fresh
battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the battery is near end of life. However, data has not been
compromised due to the fact that a nominal VCC
is supplied. In order to insure data integrity during
subsequent periods of b attery back -up mod e, it is
recommended that the battery be replaced. The
SNAPHAT top may be replaced while VCC is applied to the device.
Note: Battery monitoring is a useful technique only
when performed periodically. The M48T59/59Y/
59V only monitors the battery when a nominal
VCC is applied to the device. Thus applications
which require extensive durations in the battery
back-up mode should be powered-up period ically
(at least once every few mon ths) in order for this
technique to be beneficial. Additionally, if a battery
low is indicated, data integrity shoul d be verified
upon power-up via a checksum or other technique.
POWER-ON DEFAULTS
Upon application of power to the de vice, the following register bits are set to a ’0’ state: WDS;
BMB0-BMB4; RB0-RB1; AFE; ABE; W; R; FT.
(See Table 13).
Table 13. Default Values
Condition W R FT AFE ABE
Initial Power-up
(Battery Attach for SNAPHAT)
Subsequent Power-up / RESET
Power-down
Note: 1. WDS, BM B0-BMB4, RBO, RB1.
2. State of other control bits undefined.
3. State of other control bits rem ains unchanged.
4. Assuming these bits set to ’1’ prior to power-down.
14/21
(4)
(2)
(3)
WATCHDOG
Register
00000 0
00000 0
00011 0
(1)
Page 15
M48T59, M48T59Y, M48T59V
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, resulting in spikes on the V
bus. These transients
CC
can be reduced if capacitors are used to store energy, which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below V
by as much as one Volt. These nega-
SS
tive spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from V
connected to V
, anode to VSS). Schottky diode
CC
to VSS (cathode
CC
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount
Figure 13. Supply Voltage Protection
V
CC
V
CC
0.1µF DEVICE
V
SS
AI02169
15/21
Page 16
M48T59, M48T59Y, M48T59V
Table 14. Ordering Information Scheme
Example: M48T59Y -70 MH 1 TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
(1)
59
= VCC = 4.75V to 5.5V; V
59Y = V
59V = V
= 4.5V to 5.5V; V
CC
= 3.0V to 3.6V; V
CC
Speed
-70 = 70ns
Package
PC = PCDIP28
(2)
MH
= SOH28
Temperature Range
1 = 0 to 70 °C
(3)
6
= –40 to 85 °C
= 4.5V to 5.5V
PFD
= 4.2V to 4.5V
PFD
= 2.7V to 3.0V
PFD
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The M48T59 part is off ered with the PCDIP28 ( i. e. CAPHAT) package o nl y.
2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR12SH1" in pl astic tube o r "M 4T XX-BR12SH1TR" in Tape & Reel for m.
3. Avail able in SOIC package only.
Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH1" in conductive foam since will drain the lithium button-
cell battery.
For a list of available options (Speed, Pac kage, etc...) or for furthe r information on any aspect of this device, please contact the ST Sales Office nearest to you.
16/21
Page 17
M48T59, M48T59Y, M48T59V
Table 15. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
Symb
Typ Min Max Typ M in Max
A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350
B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070
C 0.20 0.31 0. 008 0.012
D 39.37 39.88 1.550 1.570
E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0. 090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630
L 3.05 3.8 1 0.120 0.150
N 28 28
mm inches
Figure 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A1AL
B1 B e1
eA
e3
D
N
E
1
Drawing is not to scale.
C
PCDIP
17/21
Page 18
M48T59, M48T59Y, M48T59V
Table 16. SOH28 - 28 l ead Plast i c Small Out line , battery S NAPHAT , Package M echan ical Data
Symb
Typ Min Max Typ Min Max
A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106
B 0.36 0.51 0.014 0.020
C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728
E 8.23 8.89 0.324 0.350
e 1.27 – – 0.050 – –
eB 3.20 3.61 0.126 0.142
H 11.51 12.70 0.453 0.500
L 0.41 1.27 0.016 0.050
α 0° 8° 0° 8°
N 28 28
mm inches
CP 0.10 0.004
Figure 15. SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
Be
eB
CP
D
N
E
H
LA1 α
1
SOH-A
Drawing is not to scale.
18/21
Page 19
M48T59, M48T59Y, M48T59V
Table 17. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
Symb
Typ Min Max Typ Min Max
A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
mm inches
Figure 16.
Drawing is not to scale.
M4T28-BR12SH SNAPH AT Housing for 48 mAh
eA
D
A1
E
Battery & Crystal, Package Outline
A
B
eB
SHTK-A
A2
A3
L
19/21
Page 20
M48T59, M48T59Y, M48T59V
Table 18. M4T32 -BR12SH SNAPHAT Ho using fo r 120mAh B attery & Cr ystal , Packag e Mechanic al Data
Symb
Typ Min Max Typ Min Max
A 10.54 0.415
A1 8.00 8.51 0.315 0.335
A2 7.24 8.00 0.285 0.315
A3 0.38 0.015
B 0.46 0.56 0.018 0.022
D 21.21 21.84 0.835 0.860
E 17.27 18.03 0.680 0.710
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142
L 2.03 2.29 0.080 0.090
mm inches
Figure 17. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A3
L
eA
D
A1
A
B
eB
E
SHTK-A
Drawing is not to scale.
20/21
Page 21
M48T59, M48T59Y, M48T59V
.
Information furnished is believed to be ac curate and reli able. Howev er, STMicroel ectronics assumes no responsibilit y for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implic ation or otherwise under any patent or patent rights of STMi croelectr onics. Specifications mentioned in thi s publicati on are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as cri tical comp onents in life support dev i ces or systems wi t hout express written ap proval of STMi croelect ro nics.
The ST log o i s registered trademark of STMicroelectronics
1999 STMicroel e ctronics - All Rights Reserved
All other names are the property of their respective owners.
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