Datasheet M48T58Y, M48T58, M48T58Y-70PC1, M48T58Y-70MH1 Datasheet (SGS Thomson Microelectronics)

64 Kbit (8Kb x8) TIMEKEEPER® SRAM

INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK , PO WE R-FAIL CONTRO L
CIRCUIT and BA T TER Y

BYTEWIDE RAM-LIKE CLOCK ACCE S S
BCD CODED YEAR, MONTH, DAY, DATE,

HOURS, MINUTES and SECONDS
FREQUENCY TEST OUTPUT for REAL TIME

CLOCK
AUTOMATIC POW ER-F AIL CH IP DES ELECT and

WRITE PROTECTION
WRITE PROTECT VOLT AGES

(V

= Power-fail Deselect Voltage):

PFD

– M48T58: 4.5V ≤ V
– M48T58Y: 4.2V ≤ V
SELF-CONTAINED BA T TER Y and CRYSTAL

in the CAPHAT DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC

and SNAPHAT

®

TOP

(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT

CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL

PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs

PFD

PFD

4.75V

≤

≤

4.5V

SNAPHAT (SH)

Battery/Crystal

28

28

1

SOH28 (MH)

Figure 1. Logic Diagram

V

CC

M48T58

M48T58Y

1

PCDIP28 (PC)

Battery/Crystal

CAPHAT

DESCRIPTION

The M48T58/58Y TIMEK E EPE R

®

RAM is an 8K x
8 non-volatile static RAM and real time clock. The
monolithic chip is available in two special packages

A0-A12

13

8

DQ0-DQ7

to provide a highly integrated battery backed-up
memory and real time clock solution.

T ab le 1. Signal Names

A0-A12 Address Inputs
DQ0-DQ7 Data Inputs / Outputs
FT Frequency Test Output (Open Drain)
E1 Chip Enable 1
E2 Chip Enable 2
G Output Enable
W Write Enable
V

CC

V

SS

July 1999 1/17

Supply Voltage
Ground

W

E1 FT

E2

G

M48T58

M48T58Y

V

SS

AI01374B

M48T58, M48T58Y

Figure 2A. DIP Pin Connections

FT V

1

A12

2
3

A7

4

A6

5

A5

6

A4

7

A3
A2
A1
A0

DQ0

8
9
10
11

M48T58

M48T58Y

12
13

DQ2

14

SS

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01375B

CC

W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

T ab le 2. Absolute Maximum Ratings

(1)

Figure 2B. SOIC Pin Connections

1

FT V

A12

DQ0

A7
A6
A5
A4
A3
A2
A1
A0

2
3
4
5
6
7

M48T58Y

8
9
10
11
12

DQ2

SS

13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AI01376B

Symbol Parameter Value Unit

T

A

T

STG

(2)

T

SLD

V

IO

V

CC

I

O

P

D

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indi cat ed in the operati onal
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negat i ve undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

T ab le 3. Operating Modes

Ambient Operating Temperature 0 to 70 °C
Storage T emper ature (VCC Off, Oscillator Off) –40 to 85 °C
Lead Solder Temperature for 10 seconds 260 °C
Input or Output Voltages –0.3 to 7 V
Supply Voltage –0.3 to 7 V
Output Current 20 mA
Power Dissipation 1 W

(1)

CC

W
E2
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5DQ1
DQ4
DQ3V

Mode V

CC

Deselect
Deselect X V
Write V

4.75V to 5.5V
or

4.5V to 5.5V

Read V
Read V
Deselect V

SO

to V

Deselect ≤ V

Notes

:1. X = V

2. See Table 7 for details.

or VIL; VSO = Battery Back-up Switchover Voltage.

IH

PFD

(min)

SO

(2)

E1 E2 G W DQ0-DQ7 Power

V

IH

IL

IL

IL

X X X X High Z CMOS Standby
X X X X High Z Battery Back-up Mode

2/17

X X X High Z Standby

IL

V

IH

V

IH

V

IH

X X High Z Standby
XVILD

V

IL

V

IH

V

IH

V

IH

IN

D

OUT

High Z Active

Active
Active

Figure 3. Block Diagram

M48T58, M48T58 Y

FT

OSCILLATOR AND

CLOCK CHAIN

32,768 Hz
CRYSTAL

POWER

LITHIUM

CELL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

V

CC

DESCRIPTION

(cont’d)

The M48T58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes t hat
can be performed.

The 28 pin 600mil DIP CAPHAT houses the
M48T58/58Y silicon with a quartz crystal and a long
life lithium button cell in a single package.

The 28 pin 330mil SOIC provides s ockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery and crystal. The unique design allows the
SNAPHAT battery package to be mounted on top
of the SOIC package after the completion of the
surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and
crystal damage due to the hig h temperatures re­quired for device surface-mounting. The SNAPHA T
housing is keyed to prevent reverse insertion.

The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.

8 x 8 BiPORT

SRAM ARRAY

A0-A12

DQ0-DQ7

E1
E2
W
G

AI01377C

V

PFD

8184 x 8

SRAM ARRAY

V

SS

Table 4. AC Measurement Conditions

Input Rise and Fall Times ≤ 5ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V

Note that Output Hi-Z is defined as the point where data is no
longer driven.

Figure 4. AC Testing Load Circuit

5V

1.9kΩ

DEVICE
UNDER

TEST

1kΩ

CL includes JIG capacitance

CL = 100pF or 5pF

OUT

AI01030

3/17

M48T58, M48T58Y

(1, 2)

T ab le 5. Capacitance

= 25 °C, f = 1 MHz )

(T

A

Symbol Parameter T est Condition Min Max Unit

C

IN

(3)

C

IO

Notes:

1. Effective capacitance measured with power supply at 5V .

2. Sampled only, not 100% tested.

3. Outputs deselected

Input Capacitance VIN = 0V 10 pF
Input / Output Capacitance V

= 0V 10 pF

OUT

T ab le 6. DC Characteristics

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

(T

A

Symbol Parameter Test Condition Min Max Unit

(1)

I

LI

(1)

I

LO

Supply Current Outputs open 50 mA

I

CC

I

CC1

I

CC2

(2)

V

IL

V

IH

V

OL

V

OH

Notes:

1. Outputs Deselected.

2. Negative spikes of –1V allowed for up to 10ns once per Cycle.

3. The FT pin is Open Drain.

T able 7. Power Down/Up Trip Points DC Characteristics

= 0 to 70°C)

(T

A

Input Leakage Current 0V ≤ VIN ≤ V
Output Leakage Current 0V ≤ V

Supply Current (Standby) TTL E1 = VIH, E2 = V

Supply Current (Standby) CMOS

E1 = VCC – 0.2V,
E2 = V

OUT

SS

CC

≤ V

CC

+ 0.2V

IL

Input Low Voltage –0.3 0.8 V
Input High Voltage 2.2 VCC + 0.3 V
Output Low Voltage I
Output Low Voltage (FT)

(3)

= 2.1mA 0.4 V

OL

IOL = 10mA 0.4 V

Output High Voltage IOH = –1mA 2.4 V

(1)

±1 µA
±5 µA

3mA

3mA

Symbol Parameter Min Typ Max Unit

V

PFD

V

PFD

V

SO

t

DR

Notes:

1. All voltages referenced to V

2. At 25°C

DESCRIPTION

For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28­BR12SH1".

As Figure 3 shows, the static memory array and the
quartz controlled clock oscillator of the
M48T58/58Y are integrated on one silicon chip.
The two circuits are interconnected at the upper
eight memory locations to provide user accessible

Power-fail Deselect Voltage (M48T58) 4.5 4.6 4.75 V
Power-fail Deselect Voltage (M48T58Y) 4.2 4.35 4.5 V
Battery Back-up Switchover Voltage 3.0 V

(2)

Expected Data Retention Time 7 YEARS

.

SS

(cont’d)

BYTEWIDE clock information in the bytes with
addresses 1FF8h-1FFFh. The clock locations con­tain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year), 30, and 31 day months are made
automatically. Byte 1FF8h is the clock control reg­ister. This byte controls user access to the clock
information and also stores the clock calibration
setting.

4/17

M48T58, M48T58 Y

T able 8. Power Down/Up Mode AC Characteristics

= 0 to 70°C)

(T

A

Symbol Parameter Min Max Unit

E1 or W at VIH or E2 at VIL before Power Down 0 µs
V

(max) to V

PFD

V

(min) to VSO VCC Fall Time 10 µs

PFD

V

(min) to V

PFD

VSO to V
V

(max) to V

PFD

passes V

CC

(min) to VSO fall time of less than tFB may cause corruption of RAM data.

PFD

PFD

(max) to Inputs Recognized 40 200 ms

PFD

(min) fall time of less than tF may result in deselection/writ e protection not occ urri ng until 200 µs after

PFD

(min).

PFD

(min) VCC Fall Time 300 µs

PFD

(max) VCC Rise Time 10 µs

PFD

(min) VCC Rise Time 1 µs

Notes

t

PD

(1)

t

F

t

FB

t

R

t

RB

t

REC

:1.V

2. V

(2)

V

Figure 5. Power Down/Up Mode AC Waveforms

V

CC

V

(max)

PFD

V

(min)

PFD

VSO

INPUTS

OUTPUTS

tF

tPD

VALID VALID

(PER CONTROL INPUT)

tFB

tDR

tRB

DON'T CARE

HIGH-Z

tR

tREC

RECOGNIZEDRECOGNIZED

(PER CONTROL INPUT)

AI01168C

5/17

M48T58, M48T58Y

T ab le 9. Read Mode AC Characteristics

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

(T

A

Symbol Parameter

Notes:

t

AVAV

(1)

t

AVQV

(1)

t

E1LQV

t

E2HQV

(1)

t

GLQV

(2)

t

E1LQX

t

E2HQX

(2)

t

GLQX

(2)

t

E1HQZ

(2)

t

E2LQZ

(2)

t

GHQZ

(1)

t

AXQX

1. C

= 100pF (see Figure 4).

L

= 5pF (see Figure 4).

2. C

L

Read Cycle Time 70 ns
Address Valid to Output Valid 70 ns
Chip Enable 1 Low to Output Valid 70 ns

(1)

Chip Enable 2 High to Output Valid 70 ns
Output Enable Low to Output Valid 35 ns
Chip Enable 1 Low to Output Transition 5 ns

(2)

Chip Enable 2 High to Output Transition 5 ns
Output Enable Low to Output Transition 5 ns
Chip Enable 1 High to Output Hi-Z 25 ns
Chip Enable 2 Low to Output Hi-Z 25 ns
Output Enable High to Output Hi-Z 25 ns
Address Transition to Output Transitio n 10 ns

M48T58 / M48T58Y

-70

Min Max

Unit

Figure 6. Read Mode AC Waveforms

A0-A12

E1

tE1LQX

E2

tE2HQX

G

DQ0-DQ7

Note:

Write Enable (

W) = High.

tAVAV
VALID

tAVQV tAXQX

tE1LQV

tE2HQV

tGLQV

tGLQX

tGHQZ

VALID

tE1HQZ

tE2LQZ

AI00962

6/17

M48T58, M48T58 Y

T ab le 10. Write Mode AC Characteristics

= 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)

(T

A

Symbol Parameter

t

AVAV

t

AVWL

t

AVE1L

t

AVE2H

t

WLWH

t

E1LE1H

t

E2HE2L

t

WHAX

t

E1HAX

t

E2LAX

t

DVWH

t

DVE1H

Write Cycle Time 70 ns
Address Valid to Write Enable Low 0 ns
Address Valid to Chip Enable 1 Low 0 ns
Address Valid to Chip Enable 2 High 0 ns
Write Enable Pulse Width 50 ns
Chip Enable 1 Low to Chip Enable 1 High 55 ns
Chip Enable 2 High to Chip Enable 2 Low 55 ns
Write Enable High to Address Transition 0 ns
Chip Enable 1 High to Address Transition 0 ns
Chip Enable 2 Low to Address Transition 0 ns
Input Valid to Write Enable High 30 ns
Input Valid to Chip Enable 1 High 30 ns

M48T58 / M48T58Y

-70

Min Max

Unit

Notes:

t

DVE2L

t

WHDX

t

E1HDX

t

E2LDX

(1, 2)

t

WLQZ

t

AVWH

t

AVE1H

t

AVE2L

(1, 2)

t

WHQX

1. C

= 5pF (see Figure 4).

L

E1 goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance state.

2. If

Input Valid to Chip Enable 2 Low 30 ns
Write Enable High to Input Transition 5 ns
Chip Enable 1 High to Input Transition 5 ns
Chip Enable 2 Low to Input Transition 5 ns
Write Enable Low to Output Hi-Z 25 ns
Address Valid to Write Enable High 60 ns
Address Valid to Chip Enable 1 High 60 ns
Address Valid to Chip Enable 2 Low 60 ns
Write Enable High to Output Transition 5 ns

7/17

M48T58, M48T58Y

Figure 7. Write Enable Controlled, Write AC Waveforms

tAVAV

A0-A12

tAVE1L

E1

tAVE2H

E2

tAVWL

W

tWLQZ

DQ0-DQ7

VALID

tAVWH

tWLWH

Figure 8. Chip Enable Controlled, Write AC Waveforms

tDVWH

tWHAX

tWHQX

tWHDX

DATA INPUT

AI00963

8/17

A0-A12

E1

E2

W

DQ0-DQ7

tAVAV
VALID

tAVE1H

tAVE1L

tAVE2H tE2HE2L

tAVWL

tE1LE1H

tAVE2L

tDVE1H
tDVE2L

tE1HAX

tE2LAX

tE1HDX
tE2LDX

DATA INPUT

AI00964B

M48T58, M48T58 Y

DESCRIPTION

(cont’d)

The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT read/write memory cells.
The M48T58/58Y includes a clock control circuit
which updates the clock bytes with current informa­tion once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.

The M48T58/58Y also has its own Power-fail De­tect circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi­tion. When V

is out of tolerance, the circuit write

CC

protects the SRAM, providing a high degree of data
security in the midst of unpr edictable system op­eration brought on by low V

. As VCC falls below

CC

approximately 3V , the c ontrol circuitry connects the
battery which maintains data and clock operation
until valid power returns.

READ MODE

The M48T58/58Y is in the Read Mode whenever
W (Write Enable) is high, E1 (Chip Enable 1) is low ,
and E2 (Chip Enable 2) is high. The unique address
specified by the 13 Address Inputs defines which
one of the 8,192 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the
E2, and

G access times are also satisfied. If the E1,

) after the last

AVQV

E1,

E2 and

G access times are not met, valid data will
be available after the latter of the Chip Enable
Access t ime s (t
Access time (t

E1LQV

GLQV

or t

).

) or Output Enable

E2HQV

The state of the eight three-state Data I/O signals
is controlled by
activated before t
to an indeterminate state until t
Inputs are changed while

E1, E2 and G. If the outputs are

, the data lines will be driven

AVQV

. If the Address

AVQV

E1, E2 and G remain
active, output data will remain valid for Output Data
Hold time (t

) but will go indeterminate until the

AXQX

next Address Access.

WRITE MODE

The M48T58/58Y is in the W rite Mode whenever

E1 are low and E2 is high. The start of a write

and

W

is referenced from the latter occurring falling edge

W or E1, or the rising edge of E2. A write is

of
terminated by the earlier rising edge of

W or E1, or
the falling edge of E2. The addresses must be held
valid throughout the cycle.
or E2 low for a minimum of t
Chip Enable or t

WHAX

E1 or W must return high

E1HA X

or t

E2LAX

from

from Write Enable prior to the
initiation of another read or write cycle. Data-in
must be valid t
remain valid for t

prior to the end of write and

DVWH

afterward. G should be kept

WHDX

high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on
disable the outputs t

E1 and G and a high on E 2, a low on W will

after W falls.

WLQZ

T ab le 11. Register Map

Address

D7 D6 D5 D4 D3 D2 D1 D0

1FFFh 10 Y ears Year Y ear 00-99

1FFEh 0 0 0 10 M. Month Month 01-12
1FFDh 0 0 10 Date Date Date 01-31
1FFCh 0 FT 0 0 0 Day Day 01-07

1FFBh 0 0 10 Hours Hours Hour 00-23

1FFAh 0 10 Minutes Minutes Minutes 00-59

1FF9h ST 10 Seconds Seconds Seconds 00-59

1FF8h W R S Calibration Control

Keys:

S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to ’0’ upon power, for normal clock operation)
R = READ Bi t
W = WRITE Bi t
ST = STOP Bit
0 = Must be set to ’0’

Data

Function/Range

BCD Format

9/17

M48T58, M48T58Y

DA TA RETENT ION MOD E

With valid V

applied, the M48T58/58Y operates

CC

as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, t he RAM will automat­ically power-fail deselect, write protecting itself
when V

falls within the V

CC

(max), V

PFD

PFD

(min)
window. All outputs become high impedance, and
all inputs are treated as "don’t care."

Note:

A power failure during a write cycle may
corrupt data at the c urrently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below V

(min), the user can

PFD

be assured the memory will be in a write protected
state, provided the V

fall time is not less than tF.

CC

The M48T58/58Y may respond to transient noise
spikes on V
during the time the device is s ampling V

that reach into the deselect window

CC

. There-

CC

fore, decoupling of the power supply lines is rec­ommended.

When V

drops below VSO, the control circuit

CC

switches power to the internal batter y which pre­serves data and powers the clock. The internal
button cell will maintain data in the M48T58/58Y for
an accumulated period of at least 7 years when V
is less than VSO. As system power returns and V

CC
CC

rises above VSO, the battery is disconnected, and
the power supply is switched to external V
protection continues until V
plus t
as V

(min). E1 should be kept high or E2 low

REC

rises past V

CC

(min) to prevent inadvertent

PFD

reaches V

CC

CC

PFD

. Write

(min)

write cycles prior to system stabilization. Normal
RAM operation can resume t
V

(max).

PFD

after VCC exceeds

REC

For more information on Battery Storage Life refer
to the Application Note AN1012.

CLOCK OPERATIONS
Reading the Clock

Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME­KEEPER cells in the RAM array are only data
registers, and not the actual clock counters, updat­ing the registers can be halted without disturbing
the clock itself.

Updating is halted when a ’1’ is written to the READ
bit, D6 in the Control register (1FF8h). As long as
a ’1’ remains in that position, updating is halted.

After a halt is issued, t he registers reflect the count;
that is, the day, date, and the time that were current
at the moment the halt command was issued.

All of the TIMEKEEPER registers are updated si­multaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.

Setting the Clock

Bit D7 of the Control register (1FF8h) is the WRITE
bit. Setting the WRITE bit to a ’1’, like the READ bit,
halts updates to the TIMEKEEPER registers. The
user can then load them with the correct day , date,
and time data in 24 hour BCD format (see Table

10). Resetting the WRITE bit to a ’0’ then transfers
the values of all time regi sters (1FF9h-1FFFh) to
the actual TIMEKEEPER counters and allows nor­mal operation to resume. The FT bit and the bits
marked as ’0’ in Table 10 must be written to ’0’ to
allow for normal TIMEKEEPER and RAM opera­tion. After the WRITE bit is reset, the next clock
update will occur within one second.

See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" for information on
Century Rollover.

Figure 9. Clock Calibration

NORMAL

POSITIVE
CALIBRATION

NEGATIVE
CALIBRATION

10/17

AI00594B

M48T58, M48T58 Y

Stopping and Starting the Oscilla tor

The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a ’1’ stops the oscillator. The M48T58/58Y is
shipped from STMicroelectronics with the STOP bit
set to a ’1’. When reset to a ’0’, the M48T58
oscillator starts within one second.

Calibrating the Clock

The M48T58/58Y is driven by a quartz controlled
oscillator with a nominal f requency of 32,768 Hz.
The devices are tested not to exceed 35 ppm (parts
per million) oscillator frequency error at 25°C,
which equates to about ± 1.53 minutes per month.
With the calibration bits properly set, the accuracy
of each M48T58 improves to better than ±4 ppm at
25°C.

The oscillation rate of any crystal changes with
temperature (see Figure 10). Most clock chips com­pensate for crystal frequency and temperature shift
error with cumbersome trim capacitors. The
M48T58/58Y design, however, employs periodic
counter correction. The calibration circuit adds or
subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9.
The number of times pulses are blanked (sub-

tracted, negative calibration) or split (added, posi­tive calibration) depends upon the value loaded
into the five Calibration bits found in the Control
Register. Adding counts s peeds the c lock up, sub­tracting counts slows the clock down.

The Calibration byte occupies the five lower order
bits (D4-D0) in the Control register (1FF 8h). These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; ’1’
indicates positive calibration, ’0’ indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a
binary ’1’ is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and
so on.

Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register. Assuming that the
oscillator is in fact running at exactly 32,768 Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or - 5.35 seconds per month
which corresponds to a total range of +5.5 or - 2.75
minutes per month.

Figure 10. Crystal Accuracy Across Temperature

ppm

20

0

-20

-40

∆F

= -0.038 (T - T

-60

-80

-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

F

ppm

2

C

T0 = 25 °C

)2 ± 10%

0

°C

AI02124

11/17

M48T58, M48T58Y

CLOCK OPERATIONS

(cont’d)

Two methods are available for ascertaining how
much calibration a given M48T58/58Y may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known
accurate reference (like WWV broadcasts). While
that may seem crude, it allows the des igner to give
the end user the ability to calibrate his clock as his
environment may require, even after the final prod­uct is packaged in a non-user serviceable enclo­sure. All the designer has to do is provide a simple
utility that accesses the Calibration byte.

The second approach is better suited to a manu­facturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register, is s et to a ’1’, and the oscillator is running
at 32,768 Hz, the Frequency T est (Pin 1) will toggle
at 512 Hz. Any deviation from 512 Hz indicates the
degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of

512.01024 Hz would indicate a +20 ppm oscillator
frequency error, requiring a -10 (W R001010) to be
loaded into the Calibration Byte for correction. Note
that setting or changing the Calibration Byte does
not affect the Frequency test output frequency.

The FT bit must be set using the same method used
to set the clock, using the Write bit.

The Frequency Test pin is an open drain output
which requires a pull-up resistor for pr oper oper a­tion. A 500-10kΩ resistor is recommended in order
to control the rise time.

For more information on calibration, see the Appli­cation Note AN934 "TIMEKEEPER Calibration".

POWER SUPPLY DECOUPLING and UNDER­SHOOT PROTECTION

transients, including those produced by output

I

CC

switching, can produce voltage fluctuations, result­ing in spikes on the V

bus. These transients can

CC

be reduced if capacitors are used to store energy,
which stabilizes the V

bus. The energy stored in

CC

the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur . A ceramic bypass capaci­tor value of 0.1µF (as shown in Figure 11) is rec­ommended in order to provide the needed filtering.

In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on V
values below V

by as much as one Volt. These

SS

that drive it to

CC

negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from V
connected to V

, anode to VSS). Schottky diode

CC

to VSS (cathode

CC

1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.

Figure 11. Supply Voltage Protection

V

CC

V

CC

0.1µF DEVICE

12/17

V

SS

AI02169

ORDERING INFORMATION SCHEME

Example: M48T58Y -70 MH 1 TR

M48T58, M48T58 Y

Supply Voltage and Write

Protect Voltage

(1)

58

VCC = 4.75V to 5.5V
V

= 4.5V to 4.75V

PFD

58Y V

Notes:

Caution:

= 4.5V to 5.5V

CC

V

= 4.2V to 4.5V

PFD

1. The M48T58 part is offered with the PCDIP28 (i.e. CAPHA T) package only.

2. The SOIC package (SOH28) requires the battery /c rystal package (SNAPHAT) which is ordered separately under the part number
"M4T28-BR12SH1" in plasti c tube or "M4T28 -BR 12SH 1T R" in Tape & Reel form.

Do not place the SNAPHAT battery/crystal package "M4T28-BR12SH1" in conductive foam since this will drain the lithiu m
button-cell battery.

Speed

-70 70ns

Package

PC PCDIP28

(2)

MH

SOH28

Temp. Range

1 0 to 70 °C

Shipping Method

for SOIC

blank Tubes
TR Tape & Reel

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.

13/17

M48T58, M48T58Y

PCDIP2 8 - 28 pin Plastic DIP, battery CAPHAT

Symb

Typ Min Max Typ Min Max

A 8.89 9.65 0.350 0.380
A1 0.38 0.76 0.015 0.030
A2 8.38 8.89 0.330 0.350

B 0.38 0.53 0.015 0.021
B1 1.14 1.78 0.045 0.070

C 0.20 0.31 0.008 0.012
D 39.37 39.88 1.550 1.570

E 17.83 18.34 0.702 0.722
e1 2.29 2.79 0.090 0.110
e3 29.72 36.32 1.170 1.430
eA 15.24 16.00 0.600 0.630

L 3.05 3.81 0.120 0.150

N28 28

mm inches

Drawing is not to scale.

14/17

B1 B e1

e3

D

N

1

A2

A1AL

E

C

eA

PCDIP

M48T58, M48T58 Y

SOH28 - 28 lead Plastic Small Outline, batte r y SN APHA T

Symb

Typ Min Max Typ Min Max

A 3.05 0.120
A1 0.05 0.36 0.002 0.014
A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012
D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e1.27– –0.050– –
eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α 0° 8° 0° 8°

N28 28

CP 0.10 0.004

mm inches

Be

Drawing is not to scale.

N

1

SOH-A

A2

A

C

eB

CP

D

E

H

LA1 α

15/17

M48T58, M48T58Y

SH - 4-pin SNAPHAT Housing for 49mAh Battery

Symb

Typ Min Max Typ Min Max

A 9.78 0.385
A1 6.73 7.24 0.265 0.285
A2 6.48 6.99 0.255 0.275
A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590
eA 15.55 15.95 0.612 0.628
eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

mm inches

Drawing is not to scale.

16/17

eA

D

A1

E

A2

A

B

A3

L

eB

SHTK-A

M48T58, M48T58 Y

Information furnished is believed to be accurate and reliable. However, STMicroelectronics as sumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and repl aces all information previously supplied. STMicroelectron ics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

© 1999 STMicroelectronics - All Rights Reserved

® TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics



CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta

Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

STMicroelectronics GROUP OF COMPANIES

http://www.st.com

17/17