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LM1882-R-54ACT715-R

Datasheet LM1882-54ACT715, LM1882-R-54ACT715-R Datasheet (National Semiconductor)

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Page 1
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LM1882•54ACT715
December 1998
LM1882
•
54ACT715
LM1882-R
54ACT715-R Programmable Video Sync
•
Generator
General Description
These devices make no assumptions concerning the system architecture. Line rate and field/frame rate are all a function of the values programmed into the data registers, the status register, and the input clock frequency.
The ’ACT715/LM1882 is mask programmed to default to a Clock Disable state. Bit10oftheStatus Register, Register 0, defaults to a logic “0”. This facilitates (re)programming be­fore operation.
The ’ACT715-R/LM1882-R is the same as the ’ACT715/ LM1882 in all respects except that the ’ACT715-R/
Connection Diagrams
Pin Assignment for
DIP and SOIC
LM1882-R is mask programmed to default to a Clock En­abled state. Bit 10 of the Status Register defaults to a logic “1”. Although completely (re)programmable, the ’ACT715-R/ LM1882-R version is better suited for applications using the default 14.31818 MHz RS-170 register values. This feature allows power-up directly into operation, following a single CLEAR pulse.
Features
n Maximum Input Clock Frequency>130 MHz n Interlaced and non-interlaced formats available n Separate or composite horizontal and vertical Sync and
Blank signals available
n Complete control of pulse width via register
programming
n All inputs are TTL compatible n 8 mA drive on all outputs n Default RS170/NTSC values mask programmed into
registers
n 4 KV minimum ESD immunity n ’ACT715-R/LM1882-R is mask programmed to default to
a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing
Pin Assignment
for LCC
•
LM1882-R
•
54ACT715-R Programmable Video Sync Generator
DS100232-1
Order Number LM1882CN or LM1882CM
For Default RS-170, Order Number
LM1882-RCN or LM1882-RCM
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
™
FACT
is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100232 www.national.com
DS100232-2
Page 2
Logic Block Diagram
Pin Description
There are a Total of 13 inputs and 5 outputs on the ’ACT715/ LM1882.
Data Inputs D0–D7: The Data Input pins connect to the Ad­dress Register and the Data Input Register.
ADDR/DATA: The ADDR/DATA signal is latched into the de­vice on the falling edge of the LOAD signal. The signal deter­mines if an address (0) or data (1) is present on the data bus.
L/HBYTE: The L/HBYTE signal is latched into the device on the falling edge of the LOAD signal. The signal determines if data will be read into the 8 LSB’s (0) or the 4 MSB’s (1) of the Data Registers. A 1 on this pin when an ADDR/DATA is a 0 enables Auto-Load Mode.
CLOCK: System CLOCK input from which all timing is de­rived. The clock pin has been implemented as a Schmitt trig­ger for better noise immunity. The CLOCK and the LOAD signal are asynchronous and independent. Output state changes occur on the falling edge of CLOCK.
CLR: The CLEAR pin is an asynchronous input that initial­izes the device when it is HIGH. Initialization consists of set­ting all registers to their mask programmed values, and ini­tializing all counters, comparators and registers. The CLEAR pin has been implemented as a Schmitt trigger for better noise immunity. A CLEAR pulse should be asserted by the user immediately after power-up to ensure proper initializa­tion of the registers—even if the user plans to (re)program the device.
Note: A CLEAR pulse will disable the CLOCK on the ’ACT715/LM1882 and
will enable the CLOCK on the ’ACT715-R/LM1882-R.
DS100232-3
ODD/EVEN: Output that identifies if display is in odd (HIGH) or even (LOW) field of interlace when device is in interlaced mode of operation. In noninterlaced mode of operation this output is always HIGH. Data can be serially scanned out on this pin during Scan Mode.
VCSYNC: Outputs Vertical or Composite Sync signal based on value of the Status Register. Equalization and Serration pulses will (if enabled) be output on the VCSYNC signal in composite mode only.
VCBLANK: Outputs Vertical or Composite Blanking signal based on value of the Status Register.
HBLHDR: Outputs Horizontal Blanking signal, Horizontal Gating signal or Cursor Position based on value of the Sta­tus Register.
HSYNVDR: Outputs Horizontal Sync signal, Vertical Gating signal or Vertical Interrupt signal based on value of Status Register.
Register Description
All of the data registers are 12 bits wide. Width’s of all pulses are defined by specifying the start count and end count of all pulses. Horizontal pulses are specified with-respect-to the number of clock pulses per line and vertical pulses are speci­fied with-respect-to the number of lines per frame.
REG0— STATUS REGISTER
The Status Register controls the mode of operation, the sig­nals that are output and the polarity of these outputs. The de­fault value for the Status Register is 0 (000 Hex) for the ’ACT715/LM1882 and is “1024” (400 Hex) for the ’ACT715-R/LM1882-R.
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Page 3
Register Description (Continued) Bits 0–2
B2B1B0VCBLANK VCSYNC HBLHDR HSYNVDR
0 0 0 CBLANK CSYNC HGATE VGATE
(DEFAULT)
0 0 1 VBLANK CSYNC HBLANK VGATE 0 1 0 CBLANK VSYNC HGATE HSYNC 0 1 1 VBLANK VSYNC HBLANK HSYNC 1 0 0 CBLANK CSYNC CURSOR VINT 1 0 1 VBLANK CSYNC HBLANK VINT 1 1 0 CBLANK VSYNC CURSOR HSYNC 1 1 1 VBLANK VSYNC HBLANK HSYNC
Bits 3–4
B4B
3
0 0 Interlaced Double Serration and
(DEFAULT) Equalization
0 1 Non Interlaced Double Serration 1 0 Illegal State 1 1 Non Interlaced Single Serration and
Double Equalization and Serration mode will output equal­ization and serration pulses at twice the HSYNC frequency (i.e., 2 equalization or serration pulses for every HSYNC pulse). Single Equalization and Serration mode will output an equalization or serration pulse for every HSYNC pulse. In Interlaced mode equalization and serration pulses will be output during the VBLANK period of every odd and even field. Interlaced Single Equalization and Serration mode is not possible with this part.
Bits 5–8
B5— VCBLANK Polarity B6— VCSYNC Polarity B7— HBLHDR Polarity B8— HSYNVDR Polarity
Bits 9–11
Bits 9 through 11 enable several different features of the de­vice.
B9— Enable Equalization/Serration Pulses (0)
B10— Disable System Clock (0)
B11— Disable Counter Test Mode (0)
Equalization
Disable Equalization/Serration Pulses (1)
Enable System Clock (1) Default values for B10 are “0” in the ’ACT715/
LM1882 and “1” in the ’ACT715-R/LM1882-R.
Enable Counter Test Mode (1) This bit is not intended for the user but is for internal
testing only.
Mode of Operation
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of clock cycles per line and the characteristics of the Horizontal Sync and Blank pulses.
REG1— Horizontal Front Porch REG2— Horizontal Sync Pulse End Time REG3— Horizontal Blanking Width REG4— Horizontal Interval Width
Line
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of lines per frame, and the characteristics of the Vertical Blank and Sync Pulses.
REG5— Vertical Front Porch REG6— Vertical Sync Pulse End Time REG7— Vertical Blanking Width REG8— Vertical Interval Width
EQUALIZATION AND SERRATION PULSE SPECIFICATION REGISTERS
These registers determine the width of equalization and ser­ration pulses and the vertical interval over which they occur.
REG 9 — Equalization Pulse Width End Time REG10— Serration Pulse Width End Time REG11— Equalization/Serration Pulse Vertical
Interval Start Time
REG12— Equalization/Serration Pulse Vertical
Interval End Time
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Interrupt signal if used.
REG13— Vertical Interrupt Activate Time REG14— Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or they generate separate Horizontal and Vertical Gating sig­nals.
REG15— Horizontal Cursor Position Start Time REG16— Horizontal Cursor Position End Time REG17— Vertical Cursor Position Start Time REG18— Vertical Cursor Position End Time
#
of Clocks per
#
of Lines per Frame
Signal Specification
HORIZONTAL SYNC AND BLANK SPECIFICATIONS
All horizontal signals are defined by a start and end time. The start and end times are specified in number of clock cycles per line. The start of the horizontal line is considered pulse 1 not 0. All values of the horizontal timing registers are referenced to the falling edge of the Horizontal Blank signal (see
Figure 1
causes the first falling edge of the Horizontal Blank reference pulse, edges referenced to this first Horizontal edge are n + 1 CLOCKs away, where “n” is the width of the timing in ques­tion. Registers 1, 2, and 3 are programmed in this manner. The horizontal counters start at 1 and count until HMAX. The value of HMAX must be divisible by 2. This limitation is im-
). Since the first CLOCK edge, CLOCK#1,
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Page 4
Signal Specification (Continued)
posed because during interlace operation this value is inter­nally divided by 2 in order to generate serration and equal-
FIGURE 1. Horizontal Waveform Specification
ization pulses at 2 x the horizontal frequency. Horizontal signals will change on the falling edge of the CLOCK signal. Signal specifications are shown below.
DS100232-4
Horizontal Period (HPER) Horizontal Blanking Width:=[REG(3) − 1] x ckper Horizontal Sync Width: Horizontal Front Porch:
VERTICAL SYNC AND BLANK SPECIFICATION
Figure 2
.) Vertical Frame Period (VPER)=REG(8) x hper Vertical Field Period (VPER/n)=REG(8) x hper/n Vertical Blanking Width=[REG(7) − 1] x hper/n
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=
REG(4) x ckper
=
[REG(2) − REG(1)] x ckper
=
[REG(1) − 1] x ckper
#
1, causes the first falling edge of the
Vertical Syncing Width=[REG(6) − REG(5)] x hper/n Vertical Front Porch=[REG(5) − 1] x hper/n where n=1 for noninterlaced
n=2 for interlaced
COMPOSITE SYNC AND BLANK SPECIFICATION
Horizontal Equalization PW=[REG(9) − REG(1)] x ckper
REG9=(HFP)+(HEQP)+1
Horizontal Serration PW:
Where n
=
1 for noninterlaced single serration/
equalization n=2 for noninterlaced double serration/
equalization n=2 for interlaced operation
=
[REG(4)/n + REG(1) − REG(10)] x ckper
REG 10 (HPER/2) − (HSERR) + 1
=
Figure 3
(HFP) +
.)
Page 5
Signal Specification (Continued)
FIGURE 2. Vertical Waveform Specification
FIGURE 3. Equalization/Serration Interval Programming
DS100232-5
DS100232-12
HORIZONTAL AND VERTICAL GATING SIGNALS
Horizontal Drive and Vertical Drive outputs can be utilized as general purpose Gating Signals. Horizontal and Vertical Gat­ing Signals are available for use when Composite Sync and Blank signals are selected and the value of Bit 2 of the Sta­tus Register is 0. The Vertical Gating signal will change in the same manner as that specified for the Vertical Blank.
Horizontal Gating Signal Width=[REG(16) − REG(15)] x
Vertical Gating Signal Width:
CURSOR POSITION AND VERTICAL INTERRUPT
The Cursor Position and Vertical Interrupt signal are avail­able when Composite Sync and Blank signals are selected and Bit 2 of the Status Register is set to the value of 1. The Cursor Position generates a single pulse of n clocks wide during every line that the cursor is specified. The signals are generated by logically ORing (ANDing) the active LOW (HIGH) signals specified by the registers used for generating Horizontal and Vertical Gating signals. The Vertical Interrupt signal generates a pulse during the vertical interval speci­fied. The Vertical Interrupt signal will change in the same manner as that specified for the Vertical Blanking signal.
Horizontal Cursor Width=[REG(16) − REG(15)] x ckper Vertical Cursor Width=[REG(18) − REG(17)] x hper Vertical Interrupt Width=[REG(14) − REG(13)] x hper
ckper
=
[REG(18) − REG(17)] x hper
Addressing Logic
The register addressing logic is composed of two blocks of logic. The first is the address register and counter (AD­DRCNTR), and the second is the address decode (AD­DRDEC).
ADDRCNTR LOGIC
Addresses for the data registers can be generated by one of two methods. Manual addressing requires that each byte of each register that needs to be loaded needs to be ad­dressed. Toload both bytes of all 19 registers would require a total of 57 load cycles (19 address and 38 data cycles). Auto Addressing requires that only the initial register value be specified. The Auto Load sequence would require only 39 load cycles to completely program all registers (1 address and 38 data cycles). In the auto load sequence the low order byte of the data register will be written first followed by the high order byte on the next load cycle. At the time the High Byte is written the address counter is incremented by 1. The counter has been implemented to loop on the initial value loaded into the address register. For example: If a value of 0 was written into the address register then the counter would count from 0 to 18 before resetting back to 0. If a value of 15 was written into the address register then the counter would count from 15 to 18 before looping back to 15. If a value greater than or equal to 18 is placed into the address register the counter will continuously loop on this value. Auto ad­dressing is initiated on the falling edge of LOAD when AD­DRDATA is 0 and LHBYTE is 1. Incrementing and loading of data registers will not commence until the falling edge of LOAD after ADDRDATA goes to 1. The next rising edge of
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Addressing Logic (Continued)
LOAD will load the first byte of data. Auto Incrementing is disabled on the falling edge of LOAD after ADDRDATA and LHBYTE goes low.
Manual Addressing Mode
#
Cycle
1 Enable Manual Addressing Load Address m 2 Enable Lbyte Data Load Load Lbyte m 3 Enable Hbyte Data Load Load Hbyte m 4 Enable Manual Addressing Load Address n 5 Enable Lbyte Data Load Load Lbyte n 6 Enable Hbyte Data Load Load Hbyte n
Load Falling Edge Load Rising Edge
Auto Addressing Mode
#
Cycle
1 Enable Auto Addressing Load Start Address n 2 Enable Lbyte Data Load Load Lbyte (n) 3 Enable Hbyte Data Load Load Hbyte (n); Inc Counter 4 Enable Lbyte Data Load Load Lbyte (n+1) 5 Enable Hbyte Data Load Load Hbyte (n+1); Inc Counter 6 Enable Manual Addressing Load Address
Load Falling Edge Load Rising Edge
DS100232-7
ADDRDEC LOGIC
The ADDRDEC logic decodes the current address and gen­erates the enable signal for the appropriate register. The en­able values for the registers and counters change on the fall­ing edge of LOAD. Two types of ADDRDEC logic is enabled by 2 pair of addresses, Addresses 22 or 54 (Vectored Re­start logic) and Addresses 23 or 55 (Vectored Clear logic). Loading these addresses will enable the appropriate logic and put the part into either a Restart (all counter registers are reinitialized with preprogrammed data) or Clear (all registers are cleared to zero) state. Reloading the same ADDRDEC address will not cause any change in the state of the part. The outputs during these states are frozen and the internal
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DS100232-8
CLOCK is disabled. Clocking the part during a Vectored Re­start or Vectored Clear state will have no effect on the part. To resume operation in the new state, or disable the Vec­tored Restart or Vectored Clear state, another non-ADDRDEC address must be loaded. Operation will be­gin in the new state on the rising edge of the non-ADDRDEC load pulse. It is recommended that an unused address be loaded following an ADDRDEC operation to prevent data registers from accidentally being corrupted. The following Addresses are used by the device.
Address 0 Status Register REG0 Address 1–18Data Registers REG1–REG18
Page 7
Addressing Logic (Continued)
Address 19–21Unused Address 22/54Restart Vector (Restarts Device) Address 23/55Clear Vector (Zeros All Registers) Address 24–31Unused Address 32–50Register Scan Addresses Address 51–53Counter Scan Addresses Address 56–63Unused At any given time only one register at most is selected. It is
possible to have no registers selected.
VECTORED RESTART ADDRESS
VECTORED CLEAR ADDRESS
is possible without interruption or data and performance cor­ruption. If the defaulted 14.31818 MHz RS-170 values are being used, preconditioning and restarting can be minimized by using the CLEAR pulse instead of the Vectored Restart operation. The ’ACT715-R/LM1882-R is better suited for this application because it eliminates the need to program a 1 into Bit 10 of the Status Register to enable the CLOCK. Gen Locking to another count location other than the very begin­ning or separate horizontal/vertical resetting is not possible with the ’ACT715/LM1882 nor the ’ACT715-R/LM1882-R.
SCAN MODE LOGIC
A scan mode is available in the ACT715/LM1882 that allows the user to non-destructively verify the contents of the regis­ters. Scan mode is invoked through reading a scan address into the address register. The scan address of a given regis­ter is defined by the Data register address + 32. The internal Clocking signal is disabled when a scan address is read. Disabling the clock freezes the device in it’s present state. Data can then be serially scanned out of the data registers through the ODD/EVEN Pin. The LSB will be scanned out first. Since each register is 12 bits wide, completely scanning out data of the addressed register will require 12 CLOCK pulses. More than 12 CLOCK pulses on the same register will only cause the MSB to repeat on the output. Re-scanning the same register will require that register to be reloaded. The value of the two horizontal counters and 1 ver­tical counter can also be scanned out by using address num­bers 51–53. Note that before the part will scan out the data, the LOAD signal must be brought back HIGH.
Normal device operation can be resumed by loading in a non-scan address. As the scanning of the registers is a non-destructive scan, the device will resume correct opera­tion from the point at which it was halted.
RS170 Default Register Values
The tables below show the values programmed for the RS170 Format (using a 14.31818 MHz clock signal) and how they compare against the actual EIA RS170 Specifica­tions. The default signals that will be output are CSYNC, CBLANK, HDRIVE and VDRIVE. The device initially starts at the beginning of the odd field of interlace. All signals have active low pulses and the clock is disabled at power up. Reg­isters 13 and 14 are not involved in the actual signal informa­tion. If the Vertical Interrupt was selected so that a pulse in­dicating the active lines would be output.
DS100232-9
FIGURE 4. ADDRDEC Timing
GEN LOCKING
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R is de­signed for master SYNC and BLANK signal generation. However,the devices can be synchronized (slaved) to an ex­ternal timing signal in a limited sense. Using Vectored Re­start, the user can reset the counting sequence to a given lo­cation, the beginning, at a given time, the rising edge of the LOAD that removes Vector Restart. At this time the next CLOCK pulse will be CLOCK 1 and the count will restart at the beginning of the first odd line.
Preconditioning the part during normal operation, before the desired synchronizing pulse, is necesasry. However, since LOAD and CLOCK are asynchronous and independent, this
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Page 8
RS170 Default Register Values (Continued)
Reg D Value H Register Description
REG0 0 000 Status Register (715/LM1882) REG0 1024 400 Status Register
REG1 23 017 HFP End Time REG2 91 05B HSYNC Pulse End Time REG3 157 09D HBLANK Pulse End Time REG4 910 38E Total Horizontal Clocks REG5 7 007 VFP End Time REG6 13 00D VSYNC Pulse End Time REG7 41 029 VBLANK Pulse End Time REG8 525 20D Total Vertical Lines REG9 57 039 Equalization Pulse End Time REG10 410 19A Serration Pulse Start Time REG11 1 001 Pulse Interval Start Time REG12 19 013 Pulse Interval End Time REG13 41 029 Vertical Interrupt Activate Time REG14 526 20E Vertical Interrupt Deactivate Time REG15 911 38F Horizontal Drive Start Time REG16 92 05C Horizontal Drive End Time REG17 1 001 Vertical Drive Start Time REG18 21 015 Vertical Drive End Time
Input Clock 14.31818 MHz 69.841 ns Line Rate 15.73426 kHz 63.556 µs Field Rate 59.94 Hz 16.683 ms Frame Rate 29.97 Hz 33.367 ms
(715-R/LM1882-R)
Rate Period
RS170 Horizontal Data
Signal Width µs
HFP 22 Clocks 1.536 1.5
HSYNC Width 68 Clocks 4.749 7.47 4.7
HBLANK Width 156 Clocks 10.895 17.15 10.9
HDRIVE Width 91 Clocks 6.356 10.00 0.1H
HEQP Width 34 Clocks 2.375 3.74 2.3
HSERR Width 68 Clocks 4.749 7.47 4.7
HPER iod 910 Clocks 63.556 100
RS170 Vertical Data
VFP 3 Lines 190.67 6 EQP Pulses
VSYNC Width 3 Lines 190.67 6 Serration Pulses
VBLANK Width 20 Lines 1271.12 7.62 0.075V
VDRIVE Width 11.0 Lines 699.12 4.20 0.04V
VEQP Intrvl 9 Lines 3.63 9 Lines/Field
VPERiod (field) 262.5 Lines 16.683 ms 16.683 ms/Field
VPERiod (frame) 525 Lines 33.367 ms 33.367 ms/Frame
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%
H Specification (µs)
± ± ±
±
0.005H
±
±
±
±
0.006V
0.1
0.1
0.2
0.1
0.1
0.005V
Page 9
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Junction Temperature (T
Ceramic 175˚C Plastic 140˚C
Distributors for availability and specifications.
Supply Voltage (V
DC Input Diode Current (I
=
−0.5V −20 mA
V
I
=
V
V
I
CC
DC Input Voltage (V
DC Output Diode Current (I
=
−0.5V −20 mA
V
O
=
V
V
O
CC
DC Output Voltage (V
) −0.5V to +7.0V
CC
)
IK
+0.5V +20 mA
) −0.5V to VCC+0.5V
I
)
OK
+0.5V +20 mA
) −0.5V to VCC+0.5V
O
DC Output Source
or Sink Current (I
or Ground Current
DC V
CC
per Output Pin (I
Storage Temperature (T
)
O
or I
CC
)
GND
) −65˚C to +150˚C
STG
±
15 mA
±
20 mA
Recommended Operating Conditions
Supply Voltage (VCC) 4.5V to 5.5V Input Voltage (V Output Voltage (VO) 0VtoV Operating Temperature (TA)
54ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
from 0.8V to 2.0V
V
IN
V
CC
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. National does not recom­mend operation of FACT
I
@
4.5V, 5.5V 125 mV/ns
DC Characteristics
For ’ACT Family Devices over Operating Temperature Range (unless otherwise specified)
LM1882 54ACT/LM1882 LM1882
=
T
V
CC
Symbol Parameter (V) C
+25˚C T
A
=
50 pF to +125˚C to +85˚C Units Conditions
L
Typ Guaranteed Limits
V
Minimum High Level 4.5 4.49 4.4 4.4 4.4 V I
OH
Output Voltage 5.5 5.49 5.4 5.4 5.4 V
4.5 3.86 3.7 3.76 V V
5.5 4.86 4.7 4.76 V I
V
Maximum Low Level 4.5 0.001 0.1 0.1 0.1 V I
OL
Output Voltage 5.5 0.001 0.1 0.1 0.1 V
4.5 0.36 0.5 0.44 V V
5.5 0.36 0.5 0.44 V I
I
OLD
Minimum Dynamic 5.5 32.0 32.0 mA V Output Current
I
OHD
Minimum Dynamic 5.5 −32.0 −32.0 mA V Output Current
I
IN
Maximum Input 5.5
±
0.1
Leakage Current
I
CC
Supply Current 5.5 8.0 160 80 µA V Quiescent
I
CCT
Maximum ICC/Input 5.5 0.6 1.6 1.5 mA V
Note 2: All outputs loaded; thresholds on input associated with input under test. Note 3: Test Load 50 pF, 500Ω to Ground.
=
−55˚C T
A
=
50 pF
C
L
±
1.0
=
A
±
1.0 µA V
)
J
) 0VtoV
®
circuits outside databook specifications.
−40˚C
=
−50 µA
OUT
(Note 2)
=
V
IN
IL/VIH
=
−8 mA
OH
=
50 µA
OUT
(Note 2)
=
V
IN
IL/VIH
=
+8 mA
OH
=
1.65V
OLD
=
3.85V
OHD
=
, GND
V
I
CC
=
, GND
V
IN
CC
=
− 2.1V
V
IN
CC
CC CC
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Page 10
AC Electrical Characteristics
V
CC
Symbol Parameter (V) C
Min Typ Max Min Max Min Max
f
MAXI
Interlaced f
MAX
5.0 170 190 130 150 MHz
(HMAX/2 is ODD)
f
MAX
Non-Interlaced f
MAX
5.0 190 220 145 175 MHz
(HMAX/2 is EVEN)
t
PLH1
t
PHL1
t
PLH2
t
PHL2
t
PLH3
Clock to Any Output 5.0 4.0 13.0 15.5 3.5 19.5 3.5 18.5 ns
Clock to ODDEVEN 5.0 4.5 15.0 17.0 3.5 22.0 3.5 20.5 ns (Scan Mode) Load to Outputs 5.0 4.0 11.5 16.0 3.0 20.0 3.0 19.5 ns
AC Operating Requirements
Symbol Parameter V
Control Setup Time
t
sc
t
sc
ADDR/DATA to LOAD− 5.0 3.0 4.0 4.5 4.5 ns L/HBYTE to LOAD− 3.0 4.0 4.5 4.5 ns Data Setup Time
t
sd
D7–D0 to LOAD+ 5.0 2.0 4.0 4.5 4.5 ns Control Hold Time
t
hc
LOAD− to ADDR/DATA 5.0 0 1.0 1.0 1.0 ns LOAD− to L/HBYTE 0 1.0 1.0 1.0 ns Data Hold Time
t
hd
t
rec
LOAD+ to D7–D0 5.0 1.0 2.0 2.0 2.0 ns LOAD+ to CLK (Note 4) 5.0 5.5 7.0 8.0 8.0 ns Load Pulse Width
t
wld−
t
wld+
t
wclr
t
wck
LOW 5.0 3.0 5.5 5.5 5.5 ns HIGH 5.0 3.0 5.0 7.5 7.5 ns CLR Pulse Width HIGH 5.0 5.5 6.5 9.5 9.5 ns CLOCK Pulse Width 5.0 2.5 3.0 4.0 3.5 ns (HIGH or LOW)
Note 4: Removal of Vectored Reset or Restart to Clock.
CC
(V) to +125˚C to +85˚C
LM1882 54ACT/LM1882 LM1882
=
T
+25˚C T
A
=
50 pF to +125˚C to +85˚C Units
L
=
−55˚C T
A
=
C
50 pF C
L
=
−40˚C
A
=
50 pF
L
LM1882 54ACT/LM1882 LM1882
=
T
+25˚C T
A
=
−55˚C T
A
=
−40˚C Units
A
Typ Guaranteed Minimums
Capacitance
Symbol Parameter Typ Units Conditions
C
IN
C
PD
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Input Capacitance 7.0 pF V Power Dissipation 17.0 pF V Capacitance
CC CC
=
5.0V
=
5.0V
Page 11
Capacitance (Continued)
FIGURE 5. AC Specifications
Additional Applications Information
POWERING UP
Figure 6
enabling of the CLOCK after power-up. Should control sig­nals be difficult to obtain, tion to automatically enable the CLOCK upon power-up. Use of the ’ACT715-R/LM1882-R eliminates the need for most of this circuitry. Modifications of the made to obtain the lone CLEAR pulse still needed upon power-up.
Note that, although during a Vectored Restart none of the preprogrammed registers are affected, some signals are af­fected for the duration of one frame only. These signals are the Horizontal and Vertical Drive signals. After a Vectored Restart the beginning of these signals will occur at the first CLK. The end of the signals will occur as programmed. At the completion of the first frame, the signals will resume to their programmed start and end time.
illustrates a hardwired solution to facilitate the
Figure 7
illustrates a possible solu-
Figure 7
circuit can be
DS100232-6
PREPROGRAMMING “ON-THE-FLY”
Although the ’ACT715/LM1882 and ’ACT715-R/LM1882-R are completely programmable, certain limitations must be set as to when and how the parts can be reprogrammed. Care must be taken when reprogramming any End Time reg­isters to a new value that is lower than the current value. Should the reprogramming occur when the counters are at a count after the new value but before the old value, then the counters will continue to count up to 4096 before rolling over.
The second recommendation is to program a Vectored Re­start as the final step of reprogramming. This will ensure that all registers are set to the newly programmed values and that all counters restart at the first CLK position. This will avoid overrunning the counter end times and will maintain the video integrity.
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Additional Applications Information (Continued)
FIGURE 6. Default RS170 Hardwire Configuration
DS100232-10
Note: A 74HC221A may be substituted for the 74HC423A Pin 6 and Pin 14 must be hardwired to GND Components
R1: 4.7k C1: 10 µF R2:10k C2: 50 pF
FIGURE 7. Circuit for Clear and Load Pulse Generation
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DS100232-11
Page 13
13
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Integrated Circuit (S)
NS Package Number M20B
20-Lead Plastic Dual-In-Line Package (P)
NS Package Number N20B
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54ACT715-R Programmable Video Sync Generator
•
LM1882-R
•
LIFE SUPPORT POLICY
54ACT715
•
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE­VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI­CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys­tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail-
LM1882
ure to perform when properly used in accordance
2. A critical component in any component of a life support device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
National Semiconductor Corporation
Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com
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National Semiconductor Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor Asia Pacific Customer Response Group
Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com
National Semiconductor Japan Ltd.
Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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