Datasheet LCX038AST Datasheet (Sony)

Page 1

1.8cm (0.7 Type) Black-and-White LCD Panel

Description

The LCX038AST is a 1.8cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with a built-in peripheral driving circuit. Use of three LCX038AST panels provides a full-color representation. The striped arrangement suitable for data projectors is capable of displaying fine text and vertical lines.

The adoption of DMS∗1structure and high light resistance structure realize a high luminance screen. And cross talk free circuit and ghost free circuit contribute to high picture quality.

This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. The built-in 5V interface circuit leads to lower voltage of timing and control signals.

The panel contains an active area variable circuit which supports S-XGA 5:4 and PC-98 8:5 data signals by changing the active area according to the type of input signal.

∗1

Dual Metal Shield

Features

• Number of active dots: 786,432 (0.7 Type, 1.8cm in diagonal)

• XGA, SVGA, VGA, NTSC, PAL display

• SXGA display with simple display

• High optical transmittance: 21% (typ.)

• Built-in cross talk free circuit and ghost free circuit

• High contrast ratio with normally white mode: 350 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

• Antidust glass package

• Left twist liquid crystal

Element Structure

• Dots: 1024 (H) × 768 (V) = 786,432

• Built-in peripheral driver using polycrystalline silicon super thin film transistors

Applications

• Liquid crystal data projectors

• Liquid crystal multimedia projectors

• Liquid crystal rear-projector TVs, etc.

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E00447A0Y

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

LCX038AST

∗

The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.

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LCX038AST

H Shift Register (Bidirectional Scanning)

Up/Down and/or Right/Left

Inversion Control Circuit

Precharge Control

Circuit

COM PAD

COM

VSIG6

VSIG5

VSIG4

VSIG3

VSIG2

VSIG1

Vss

ENB

DWN

PCG

VCK

VST

RGT

BLK

HCK2

HCK1

HST

SSGL

PSIG

Black Frame Control Circuit

Side-Black Control Circuit

V Shift Register

(Bidirectional Scanning)

Black Frame Control Circuit

V Shift Register

(Bidirectional Scanning)

SSGR

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12

Input Signal Level Shifter Circuit

Block Diagram

Page 3

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LCX038AST

Absolute Maximum Ratings (VSS = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V BLK, ENB, DWN HB, VB

• Video signal input pin voltage VSIG1 to 12, PSIG –1.0 to +15 V

• Operating temperature

∗

Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

∗

Panel temperature inside the antidust glass

Operating Conditions (VSS = 0V)

• Supply voltage

HVDD 13.5 ± 0.5V VVDD 15.5 ± 0.5V

• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)

Vin 5.0 ± 0.5V

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LCX038AST

Pin Description

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PSIG VSSGR VSIG1 VSIG2 VSIG3 VSIG4 VSIG5 VSIG6 VSIG7 VSIG8 VSIG9 VSIG10 VSIG11 VSIG12 HVDD RGT HST HCK2 HCK1 VSS VSSGL BLK ENB VCK VST DWN HB VB PCG VVDD COM TEST

Symbol Description

Uniformity improvement signal GND for right V gate Video signal 1 to panel Video signal 2 to panel Video signal 3 to panel Video signal 4 to panel Video signal 5 to panel Video signal 6 to panel Video signal 7 to panel Video signal 8 to panel Video signal 9 to panel Video signal 10 to panel Video signal 11 to panel Video signal 12 to panel Power supply for H driver Drive direction pulse for H shift register (H: normal, L: reverse) Start pulse for H shift register drive Clock pulse for H shift register drive 2 Clock pulse for H shift register drive 1 GND (H, V drivers) GND for left V gate Input for PC98 mode Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Drive direction pulse for V shift register (H: normal, L: reverse) Display switch for S-XGA Display switch for PC98 mode Improvement pulse for uniformity Power supply for V driver Common voltage of panel Test pin, leave this pin open

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LCX038AST

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)

(1) VSIG1 to VSIG12, PSIG

HVDD

250Ω

Input

1MΩ

Level conversion circuit

(2-phase input)

2.5kΩ2.5kΩ

HVDD

Input

1MΩ

Level conversion circuit

(single-phase input)

250Ω250Ω

HVDD

Input

1MΩ

Level conversion circuit

(single-phase input)

250Ω250Ω

VVDD

Input

1MΩ

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

VVDD

Input

1MΩ

Level conversion circuit

(single-phase input)

Input

VVDD

1MΩ

(2) HCK1, HCK2

(3) RGT

(4) HST

(5) PCG, VCK

(6) VST, BLK, ENB, HB, VB, DWN

(7) COM

Input

HVDD

Signal line

1MΩ

are all Vss.

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LCX038AST

Input Signals

1. Input signal voltage conditions (VSS = 0V)

∗1

Input video signal shall be symmetrical to VVC.

∗2

The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower.

∗3

Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG12 and which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, upper shows signal level of the 1st step, lower shows signal level of the 2nd step. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 450ns (as shown in a diagram below). The optimum input voltage of PSIG may be changed according as drive conditions of the drive side.

Level Conversion Circuit

The LCX038AST has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.

trPSIG tfPSIG

VVC

PSIG

PCG

90%

10%

PRG

∗

PsigG

PsigB

Input waveform of uniformity improvement signal PSIG

∗4

PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel.

Item

H shift register input voltage HST, HCK1, HCK2, RGT

(Low) (High)

VHIL VHIH

VVIL VVIH

VVC Vsig Vcom VpsigB VpsigG

–0.5

4.5

–0.5

4.5

7.4 VVC – 5.0 VVC – 0.5 VVC ± 4.9 VVC ± 1.8

0.0

5.0

0.0

5.0

7.5

7.0 VVC – 0.4 VVC ± 5.0 VVC ± 1.9

0.4

5.5

0.4

5.5

7.6 VVC + 5.0 VVC – 0.3 VVC ± 5.1 VVC ± 2.0

V V

V V V

V shift register input voltage HB, VB, BLK, VST, VCK, PCG, ENB, DWN

Video signal center voltage Video signal input range

∗1

Common voltage of panel

∗2

Uniformity improvement signal input voltage (PSIG)

∗3

Symbol Min. Typ.

Max. Unit

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LCX038AST

2. Clock timing conditions (Ta = 25°C) (XGA mode: fHckn = 3.9MHz, fVck = 34.3kHz)

∗5

Hckn means Hck1 and Hck2.

∗6

Blk is the timing during PC98 mode, which keeps "H" level in other modes.

Hst rise time Hst fall time Hst data set-up time Hst data hold time Hckn rise time

∗5

Hckn fall time

∗5

Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time Enb rise time Enb fall time Horizontal video period completed to Enb fall time Enb rise to PRG∗4fall time Enb fall to Pcg rise time Enb pulse width Pcg rise time Pcg fall time Pcg rise to Vck rise/fall time Pcg fall to horizontal video period start time Pcg pulse width PRG∗4rise to Pcg rise time PRG∗4fall to Pcg fall time PRG∗4pulse width Blk rise time Blk fall time Blk rise to Enb fall time Blk fall to Pcg rise time

trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb tdEnb toPRG

∗4

toPcg twEnb trPcg tfPcg toVck toVideo twPcg toPcgr toPcgf twPRG

∗4

trBlk tfBlk toEnb toPcg

— —

55 55

—

— –15 –15

—

2 2

—

760 110 830

1650

—

–100

170

1400

–10 570 830

—

–1

— —

65 65

— —

0 0

— —

7 7

— — — —

800 120

1000

— — —

200

1700

700

1000

— —

1 0

30 30 75 75 30 30 15

15 100 100

12 100 100 100 100

—

130

—

30 100

—

100 100

0 1

µs

Item Symbol Min. Typ. Max. Unit

HST

HCK

VST

VCK

ENB

PCG

BLK

∗6

PRG

∗4

µs

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LCX038AST

∗7

Definitions: The right-pointing arrow ( ) means +.

The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement.

Hst rise time

HST

HCK

Hst fall time

Hst data set-up time

Hst data hold time

Hckn rise time

∗5

Hckn fall time

∗5

Hck1 fall to Hck2 rise time

Hck1 rise to Hck2 fall time

• Hckn

∗5

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

• Hckn

∗5

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

• Hckn

∗5

duty cycle 50% to1Hck = 0ns to2Hck = 0ns

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

Item Symbol Waveform Conditions

90%

10%

90%

Hst

trHst tfHst

50%

∗

Hst

Hck1

tdHst thHst

50% 50%

∗

Hckn

10%

90%

trHckn tfHckn

50%

∗7

Hck1

to2Hck to1Hck

50%

Hck2

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LCX038AST

VCK

ENB

Vck rise time

Vck fall time

Enb rise time

Enb fall time

Horizontal video period completed to Enb fall time

trVck

tfVck

trEnb

tfEnb

tdEnb

Enb rise to PRG∗4fall time

Enb fall to Pcg rise time

toPRG

∗4

toPcg

Enb pulse width

twEnb

Item Symbol Waveform Conditions

Vck

10%

90%

trVck tfVck

90%

10%

tfEnb trEnb

Enb

50%

toPRG

∗

Enb

∗

50%

PRG

∗

H. Blanking periodH. Video period

tdEnb

PCG

50%

toPcg

50%

twEnb

Vst rise time

VST

Vst fall time

Vst data set-up time

Vst data hold time

trVst

tfVst

tdVst

thVst

90%

10%

90%

Vst

trVst tfVst

50%

∗

Vst

Vck

tdVst thVst

50%

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LCX038AST

Item Symbol Waveform Conditions

PRG∗4fall to Pcg fall time

PRG

∗4

toPcgf

PRG∗4pulse width

twPRG

∗

50%

∗

PRG

∗

Pcg

toPcgf

50%

twPRG

∗

toPcgr

50%

∗

Blk

50%

toPcg

50%

toEnb

50%

Pcg

Enb

BLK

Blk rise time

trBlk

Blk fall time

tfBlk

Blk rise to Enb fall time

toEnb

Blk fall to Pcg rise time

toPcg

90%

10%

90%

tfBlk trBlk

∗8

PCG input pin and PRG∗4should be "H" level during the horizontal 1H period, where the above BLK is low more than 10ns.

∗8

twPcg

50%

toVideo

Pcg

∗

50%

Vck

H. blanking period H. video period

toVck

PCG

∗8

Pcg rise time

trPcg

Pcg fall time

tfPcg

Pcg rise to Vck rise/fall time

toVck

Pcg fall to horizontal video period start time

Pcg pulse width

PRG∗4rise to Pcg rise time

toVideo

twPcg

toPcgr

90%

10%

90%

Pcg

trpcg tfpcg

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LCX038AST

Electrical Characteristics (Ta = 25°C, HVDD = 13.5V, VVDD = 15.5V)

1. Horizontal drivers

Item

Input pin capacitance HCKn

HST

Input pin current HCK1

HCK2 HST

RGT Video signal input pin capacitance Current consumption

CHckn CHst

Csig IH

HCK1 = GND HCK2 = GND HST = GND RGT = GND

HCKn: HCK1, HCK2 (3.9MHz)

— —

–500

–1000

–500 –150

— —

15 15

–200 –300 –150

–40

10.0

20 20

— — — —

200

15.0

pF pF µA µA µA µA pF

Symbol Min. Typ. Max. Unit Condition

2. Vertical drivers

Item

Input pin capacitance VCK

VST Input pin current VCK, PCG VST, ENB, DWN, BLK, HB,

VB Current consumption

CVck CVst

— —

–1000

–150

—

15 15

–150

–30

3.0

20 20

— —

6.0

pF pF µA

µA

Symbol Min. Typ. Max. Unit Condition

3. Total power consumption of the panel

4. Pin input resistance

Item

Pin – V

SS input resistance Rpin 0.4 1 — MΩ

Symbol Min. Typ. Max. Unit

Item

COM pin capacitance COM — 17 25 nF

Symbol Min. Typ. Max. Unit

Item

Total power consumption of the panel

PWR — 200 350 mW

Symbol Min. Typ. Max. Unit

VCK = GND, PCG = GND VST, ENB, DWN, BLK, HB,

VB = GND VCK: (34.3kHz)

5. Uniformity improvement signal

Item

Input pin capacitance for uniformity improvement signal

CPSIGo 11 nF

Symbol Min. Typ. Max. Unit

—

6. COM pin capacitance

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LCX038AST

Reflection Preventive Processing

When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This prevents characteristic deterioration caused by luminous reflection.

Electro-optical Characteristics (XGA mode)

Item

Contrast ratio

25°C 25°C

25°C

60°C

25°C

60°C

25°C

60°C

0°C

25°C

0°C 25°C 60°C 25°C 25°C

CR T RV90-25 GV90-25 BV90-25 RV90-60 GV90-60 BV90-60 RV50-25 GV

50-25

BV50-25 RV50-60 GV50-60 BV50-60 RV10-25 GV10-25 BV10-25 RV10-60 GV10-60 BV10-60 ton0 ton25 toff0 toff25 F YT60 CTK

1 2

5 6 7

—

Optical transmittance

V-T characteristics

V90

V50

ON time

OFF time

V10

Response time

Flicker Image retention time Cross talk

Symbol Measurement method Min. Typ. Max. Unit

250

0.9

1.0

1.1

0.8

0.9

1.0

1.2

1.3

1.4

1.2

1.3

1.4

1.6

1.7

1.8

1.6

1.7

1.8

— — — — — — —

350

1.2

1.3

1.4

1.1

1.2

1.3

1.5

1.6

1.7

1.5

1.6

1.7

1.9

2.0

2.1

1.9

2.0

2.1

28.0

14.0

72.0

34.0

–67.0

—

— —

1.5

1.6

1.7

1.4

1.5

1.6

1.8

1.9

2.0

1.8

1.9

2.0

2.2

2.3

2.4

2.2

2.3

2.4

80.0

40.0

200.0

70.0

–40.0

—

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LCX038AST

<Electro-optical Characteristics Measurement>

• Measurement system I

• Measurement system II

Light Detector

Measurement

Equipment

Optical fiber

LCD panel

Light receptor lens

Drive Circuit

Light

Source

Basic measurement conditions (1) Driving voltage HVDD = 13.5V, VVDD = 15.5V VVC = 7.5V, Vcom = 7.1V (2) Measurement temperature 25°C unless otherwise specified. (3) Measurement point One point in the center of the screen unless otherwise specified. (4) Measurement systems Two types of measurement systems are used as shown below. (5) Video input signal voltage (Vsig) Vsig = 7.5 ± VAC [V] (VAC = signal amplitude)

Projection size: 101.6cm (40 in) Projection lens: F1.7 Light source: 120W UHP lamp Incidence illumination system: F#2.5 Polarzer: Side of incidence light-Polatechno's SHC-128U

Side of output light-Polatechno's SKN-18243

Screen

LCD Projector

Approx. 2000mm

Luminance

Meter

1. Contrast Ratio

Contrast Ratio (CR) is given by the following formula (1).

CR =

L (White)

... (1)

L (Black)

L (White): Surface luminance of the center of the screen at the input signal amplitude V

AC = 0.5V.

L (Black): Surface luminance of the center of the screen at VAC = 5.0V. Both luminosities are measured by System I.

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LCX038AST

2. Optical Transmittance

Optical Transmittance (T) is given by the following formula (2).

White luminance

T = × 100 [%] ... (2)

Luminance of light source

"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V on Measurement System I.

3. V-T Characteristics

V-T characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively.

4. Response Time

Response time ton and toff are defined by formulas (3) and (4) respectively.

ton = t1 – tON ...(3) toff = t2 – tOFF ...(4)

t1: time which gives 10% transmittance of

the panel.

t2: time which gives 90% transmittance of

the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure.

90 V50 V10

VAC – Signal amplitude [V]

Transmittance [%]

Input signal voltage (Waveform applied to the measured pixels)

5.0V

0.5V

7.5V

100%

90%

10%

tON t1

ton

tOFF t2

toff

Optical transmittance output waveform

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LCX038AST

5. Flicker

Flicker (F) is given by formula (5). DC and AC (XGA/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster∗mode are measured by a DC voltmeter and a spectrum analyzer in System II.

F [dB] = 20 log

{

AC component

}

...(5)

DC component

6. Image Retention Time

Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.5 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time till the residual image becomes indistinct.

∗

Monoscope signal conditions: Vsig = 7.5 ± 5.0 or ±2.0 [V] (shown in the right figure) Vcom = 7.1V

7. Cross Talk

Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around a black window (Vsig = 5.0V/1V).

Cross talk value CTK = × 100 [%]

∗

Each input signal voltage for gray raster mode is given by Vsig = 7.5 ± V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics.

Black level

White level

Vsig waveform

7.5V

5.0V

2.0V

5.0V

2.0V

W1'

W3'

W2' W4'

Wi' – Wi

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LCX038AST

Viewing angle characteristics (Typical value)

270

180

Theta

Phi

7050

100

160

280

340

400

220

φ180°

φ270°

φ0°

φ90°

θ0°

Marking

Measurement method

Page 17

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LCX038AST

Optical transmittance of LCD panel (Typical value)

400 500 600 700

Wavelength [nm]

Trans. [%]

Measurement method: Measurement system II

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LCX038AST

1. Dot Arrangement

The dots are arranged in a stripe. The shaded area is used for the dark border around the display.

4 dots

1032 dots

4 dots

772 dots

2 dots

1024 dots (Effective 14.336mm)

768 dots (Effective 10.752mm)

Gate SW

Active area

Photo-Shielding

Gate SW

2 dots

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LCX038AST

2. LCD Panel Operations

[Description of basic operations]

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 768 gate lines sequentially in a single horizontal scanning period. (XGA mode)

• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 1024 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines.

• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 1024 × 768 dots to display a picture in a single vertical scanning period.

• The data and video signals shall be input with the 1H-inverted system.

[Description of operating mode]

This LCD panel can change the active area by displaying a black frame to support various computer or video signals. The active area is switched by HB, VB and BLK. However, the center of the screen is not changed. The active area setting modes are shown below.

HB VB BLK Screen aspect ratio

∗1

4:3

1024 × 768

5:4

∗2

960 × 768

8:5

1024 × 640

∗1

Input BLK pulse (refer to drive waveform and vertical blanking period of PC98 made).

∗2

For only aspect ratio 5:4 mode, set Psig and COM voltage as shown below. The value of PsigG and COM voltage is typical value. It is necessary to optimize the voltage for each set construction.

Psig

COM

PRG

∗

VVC + 5.0 [V]

VVC + 1.0 [V]

VCOM + 2.0

VVC – 5.0 [V]

VVC

VVC – 1.0 [V]

VCOM

VCOM – 2.0

Psig B

Psig G

∗3

PRG shows the time of the 1st step of Psig signal, and it is not input to the panel.

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LCX038AST

This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems.

• Right/left inverse mode

• Up/down inverse mode

These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are shown below.

Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin block upside.

To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for both the H and V systems must be varied. The phase relationship between the start pulse and the clock for each mode is shown below.

(1) Vertical direction display cycle (DWN = H, L)

RGT Mode

Right scan Left scan

DWN Mode

Down scan Up scan

Vertical display cycle 768H

VCK

766

767 768

VST

765

Vertical display cycle 640H

VCK

638

639 640

VST

637

(1.2) PC98

(1.1) XGA, SXGA

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LCX038AST

(2) Horizontal direction display cycle

(2.1.1) XGA, PC98 (RGT = H)

1234

Horizontal display cycle

HST

HCK1

83 84 85 86

HCK2

(2.1.2) XGA, PC98 (RGT = L)

Horizontal display cycle

HST

HCK1

123 4 83 84 85 86

HCK2

(2.2.1) SXGA (RGT = H)

Horizontal display cycle

HST

HCK1

123 4 77 78 79 80

HCK2

(2.2.2) SXGA (RGT = L)

Horizontal display cycle

HST

HCK1

77 78 79 80

HCK2

1234

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LCX038AST

(3) Vertical blanking cycle of PC98 mode

The input waveforms of PCG, PRG∗1and PSIG should be changed as shown below when BLK pulse is input.

BLK

VCK

ENB

PCG

PRG

∗

PSIG

Vertical blanking cycle

∗1

PRG shows the period of PSIG black level, it is not input to the panel.

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LCX038AST

3. 12-dot Simultaneous Sampling

The horizontal shift register samples signals VSIG1 to VSIG12 simultaneously. This requires phase matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the LCD panel.

The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT = Low level), the phase settings for signals VSIG1 to VSIG12 are exactly reversed.

VSIG1

S/H

CK12

VSIG2

VSIG3

VSIG4

VSIG5

VSIG6

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12

LCX038AST

S/H

CK11

S/H

CK10

S/H

CK9

S/H

CK8

S/H

CK7

S/H

CK6

S/H

CK5

S/H

CK4

S/H

CK3

S/H

CK2

S/H

CK1

VSIG1

VSIG2

VSIG3

VSIG4

VSIG5

VSIG6

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12

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LCX038AST

<Phase relationship of delaying sample-and-hold pulses> (right scan)

HCKn

CK1 CK2

CK3 CK4

CK5 CK6

CK7 CK8

CK9 CK10 CK11

CK12

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LCX038AST

Display System Block Diagram

An example of display system is shown below.

LCX038

S/H Driver CXA3512R

LCX038

S/H Driver CXA3512R

LCX038

S/H Driver CXA3512R

PLL CXA3106AQ

Color Shading Correction CXA3503R

Gamma CXA2111R

L.P.F.

Timing Generator CXA3500R

R G B

HSYNC

VSYNC

DSYNC

MCLK/2

PRG, CLP

VST

ENB, PRG, FRP

Timing Pulses

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LCX038AST

Notes on Handling

(1) Static charge prevention

Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels.

(2) Protection from dust and dirt

a) Operate in a clean environment. b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective

sheet carefully so as not to damage the glass panel.

c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a clean-

room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.

d) Use ionized air to blow dust off the glass panel.

(3) Light resistance

Orientation film and organic matter such as liquid crystal used inside of the LCD panel deteriorate by the light chemical reaction. As a result, its indication characteristics may irreversible change. The progress of its chemical reaction is influenced by short wavelength side's light (characteristics of UV cut filter) and temperature when quantitiy of light is constant. To control its progress, attach suitable UV cut filter between light source and LCD panel. (Sharp characteristic's filter of λ > 425nm is recommended.) Also, use suitable IR cut filter to lower the temperature of LCD panel and cool the panel carefully.

(4) Other handling precautions

a) Do not twist or bend the flexible PC board especially at the connecting region because the board is

easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel

damages. g) Minimum radius of bending curvature for a flexible substrate must be 1mm. h) Torque required to tighten screws on a panel must be 0.098N · m (measurement screw: JCIS Type 1,

M1.7 flat head screw) or less. i) Do not pressure the portion other than mounting hole (cover).

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LCX038AST

Package Outline Unit: mm

Mass

5.6g

4.7 ± 0.2

Thickness of the connector

0.3 ± 0.05

2.2 ± 0.1

Incident light

Output light Polarizing Axis

Active Area

25.0 ± 0.15

(14.33)

(10.75)

12.0

± 0.15

(75.5)

101.5

± 1.4

23.0

± 0.1

26.0

± 0.15

8-R1.0

1.5

± 0.1

12.5 ± 0.15

2.0 ± 0.1

21.0 ± 0.1

5-φ1.8 ± 0.05

Incident light Polarizing Axis

16.5 ± 0.05

The rotation angle of the active area relative to H and V is ± 1°.

electrode (enlarged)

P0.5 × 31 = 15.5 ± 0.1

0.5 ± 0.1

PIN32

PIN1

0.35 ± 0.03

0.5

± 0.15

4.0

± 0.4

Description

Molding material

Outside frame

Reinforcing board

Reinforcing material

F P C

1 2 3 4 5 6

Cover 1 Cover 2

8 9

Glass 1

Glass 2

Sony Corporation