Datasheet LCX028AMT Datasheet (Sony)

LCX028AMT

4.6cm (1.8-inch) Black-and-White LCD Panel

Description

The LCX028AMT is a 4.6cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX028AMT panels
provides a full-color representation. The striped
arrangement suitable for data projectors is capable
of displaying fine text and vertical lines.

The adoption of an advanced on-chip black matrix
realizes a high luminance screen. And cross talk free
circuit and ghost free circuit contribute to high
picture quality.

This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.

The panel contains an active area variable circuit
which supports 4:3 and 16:9 data signals by changing
the active area according to the type of input signal.

Features

• Number of active dots: 1,310,720 (1.8-inch, 4.6cm in diagonal)

• 4:3 and 16:9 aspect-ratio switching function

4:3 (1280 (H) × 960 (V))

16:9 (1280 (H) × 720 (V))

• High optical transmittance: 27% (typ.)

• Built-in cross talk free circuit and ghost free circuit

• High contrast ratio with normally white mode: 250 (typ.)

• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)

• Up/down and/or right/left inverse display function

• Antidust glass package

• Microlens used

Element Structure

• Dots: 1280 (H) × 1024 (V) = 1,310,720

• Built-in peripheral driver using polycrystalline silicon super thin film transistors

Applications

• Liquid crystal data projectors

• Liquid crystal multimedia projectors

• Liquid crystal rear-projector TVs, etc.

– 1 –

E99230-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

∗

The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.

– 2 –

LCX028AMT

18

COM

VSIG6

VSIG5

VSIG4

VSIG3

VSIG2

VSIG1

Vss

VV

DD

HV

DD

ENB

DWN

PCG

VCK

VST

RGT

BLK

HCK2

HCK1

HST

V

SS

G

PSIG

17

20

19

22

23

16

2

24

VB1

VB2

25

29

26

28

15

30

27

COMR

9

12

11

10

8

7

4

3

5

13

6

14

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12

1

21

COML

32

H Shift Register (Bidirectional Scanning)

Up/Down and/or Right/Left

Inversion Control Circuit

V Shift Register

(Bidirectional Scanning)

Precharge Control

Circuit

COM
PAD

V Shift Register

(Bidirectional Scanning)

Black Frame Control Circuit

Black Frame Control Circuit

Input Signal
Level Shifter
Circuit

31

Block Diagram

– 3 –

LCX028AMT

Absolute Maximum Ratings (VSS = 0V)

• H driver supply voltage HVDD –1.0 to +20 V

• V driver supply voltage VVDD –1.0 to +20 V

• Common pad voltage COM, COML, COMR –1.0 to +17 V

• H shift register input pin voltage HST, HCK1, HCK2, –1.0 to +17 V

RGT

• V shift register input pin voltage VST, VCK, PCG, –1.0 to +17 V
BLK, ENB, DWN
VB1, VB2

• Video signal input pin voltage SIG1 to 12, PSIG –1.0 to +15 V

• Operating temperature

∗

Topr –10 to +70 °C

• Storage temperature Tstg –30 to +85 °C

∗

Panel temperature inside the antidust glass

Operating Conditions (VSS = 0V)

• Supply voltage

HVDD 15.5 ± 0.5V
VVDD 15.5 ± 0.5V

• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins)

– 4 –

LCX028AMT

Pin Description

Pin
No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

PSIG
COMR
VSIG1
VSIG2
VSIG3
VSIG4
VSIG5
VSIG6
VSIG7
VSIG8
VSIG9
VSIG10
VSIG11
VSIG12
HVDD
RGT
HST
HCK1
HCK2
VSS
COML
BLK
ENB
VCK
VST
DWN
VB1
VB2
PCG
VVDD
VSSG
COM

Symbol Description

Uniformity improvement signal
Voltage for right CS (storage capacity) electrode line
Video signal 1 to panel
Video signal 2 to panel
Video signal 3 to panel
Video signal 4 to panel
Video signal 5 to panel
Video signal 6 to panel
Video signal 7 to panel
Video signal 8 to panel
Video signal 9 to panel
Video signal 10 to panel
Video signal 11 to panel
Video signal 12 to panel
Power supply for H driver
Drive direction pulse for H shift register (H: nomal, L: reverse)
Start pulse for H shift register drive
Clock pulse for H shift register drive 1
Clock pulse for H shift register drive 2
GND (H, V drivers)
Voltage for left CS (storage capacity) electrode line
Black Frame display pulse
Enable pulse for gate selection
Clock pulse for V shift register drive
Start pulse for V shift register drive
Drive direction pulse for V shift register (H: nomal, L: reverse)
Display area switching 1
Display area switching 2
Improvement pulse for uniformity
Power supply for V driver
GND for V gate
Common voltage of panel

– 5 –

LCX028AMT

Input Equivalent Circuit

To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)

Input

LC

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

VV

DD

Input

Level conversion circuit

(single-phase input)

250Ω250Ω

HV

DD

Input

Level conversion circuit

(single-phase input)

2.5kΩ2.5kΩ

HV

DD

Input

HV

DD

250Ω

250Ω

250Ω

250Ω

Level conversion circuit

(2-phase input)

Input

HV

DD

Signal line

(1) VSIG1 to VSIG12, PSIG

(2) HCK1, HCK2

(3) RGT

(4) HST

(5) PCG, VCK

(6) VST, BLK, ENB, DWN, VB1, VB2

(7) COM, COML, COMR

1MΩ

Input

1MΩ

1MΩ

1MΩ

Level conversion circuit

(single-phase input)

250Ω250Ω

VV

DD

Input

1MΩ

1MΩ

1MΩ

VVDD

1MΩ

Input

1MΩ

(8) HVDD, VSSG, VVDD

are all Vss.

Level conversion circuit

(2-phase input)

– 6 –

LCX028AMT

Input Signals

1. Input signal voltage conditions (VSS = 0V)

Item

H shift register input voltage
HST, HCK1, HCK2, RGT

(Low)
(High)

(Low)

(High)

VHIL
VHIH

VVIL

VVIH
VVC

Vsig
Vcom
VpsigB
VpsigG

–0.5

4.5

–0.5

4.5

6.9
VVC – 4.5
VVC – 0.6
VVC ± 4.4
VVC ± 1.7

0.0

5.0

0.0

5.0

7.0

7.0
VVC – 0.5
VVC ± 4.5
VVC ± 1.8

0.4

5.5

0.4

5.5

7.1
VVC + 4.5
VVC – 0.4
VVC ± 4.6
VVC ± 1.9

V
V

V

V
V

V
V

V

V shift register input voltage
VB1, VB2, BLK, VST,
VCK, PCG, ENB, DWN

Video signal center voltage
Video signal input range

∗1

Common voltage of panel

∗2

Uniformity improvement signal
input voltage (PSIG)

∗3

Symbol Min. Typ. Max. Unit

∗1

Input video signal shall be symmetrical to VVC.

∗2

The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.

∗3

Input a uniformity improvement signal PSIG in the same polarity with video signals VSIG1 to VSIG12 and
which is symmetrical to VVC. PSIG wave form is 2 steps like below, in the upper chart, upper shows signal
level of the 1st step, lower shows signal level of the 2nd step. Also, the rising and falling of PSIG are
synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed
within 400ns (as shown in a diagram below).

Level Conversion Circuit

The LCX028AMT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.

trPSIG
tfPSIG

VVC

PSIG

PCG

90%

10%

PRG

∗

4

PsigG

PsigB

Input waveform of uniformity improvement signal PSIG

∗4

PRG shows the time of the 1st step of PSIG signal, and it is not input to the panel.

– 7 –

LCX028AMT

2. Clock timing conditions (Ta = 25°C) (SXGA mode: fHckn = 4.5MHz, fVck = 32.0kHz, fv = 60Hz)

∗5

Hckn means Hck1 and Hck2.

∗6

The minimum value of tdEnb is 450ns. When H-BLK has a long cycle and has some time to spare, take
more time prior to other value.

∗7

Blk is the timing during 4:3 and 16:9 aspect-ratio mode, which keeps "H" level in other modes.

Hst rise time
Hst fall time
Hst data set-up time
Hst data hold time
Hckn rise time

∗5

Hckn fall time

∗5

Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Vst rise time
Vst fall time
Vst data set-up time
Vst data hold time
Vck rise time
Vck fall time
Enb rise time
Enb fall time
Horizontal video period completed to Enb fall time
Enb rise to horizontal video period started
Enb fall to Pcg rise time
Enb pulse width
Pcg rise time
Pcg fall time
Pcg rise to Vck rise/fall time
Pcg fall to horizontal video period start time
Pcg pulse width
PRG∗4rise to Pcg rise time
PRG∗4fall to Pcg fall time
PRG∗4pulse width
Blk rise time
Blk fall time
Blk rise to Enb fall time
Blk fall to Pcg rise time

trHst
tfHst
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trVst
tfVst
tdVst

thVst
trVck
tfVck
trEnb
tfEnb
tdEnb
toPRG

∗4

toPcg
twEnb
trPcg
tfPcg
toVck
toVideo
twPcg
toPcgr
toPcgf
twPRG

∗4

trBlk
tfBlk
toEnb
toPcg

—
—
35
35
—

—
–15
–15

—

—

2

2
—
—
—
—

450

∗6

800
750

1800

—
—

–100

200

1600

–10
400

1100

—
—

2
–1

—
—
45
45
—
—

0

0
—
—

6

6
—
—
—
—

700
1100
1000

—
—
—

0

270
1800

0

600
1200

—
—

1
0

30
30
55
55
30
30
15

15
100
100

10

10
100
100
100
100

—

—

—

—

30

30
100

—

—

10

—

—
100
100

0
1

ns

µs

ns

Item Symbol Min. Typ. Max. Unit

HST

HCK

VST

VCK

ENB

PCG

BLK

∗5

PRG

∗4

µs

– 8 –

LCX028AMT

∗8

Definitions: The right-pointing arrow ( ) means +.
The left-pointing arrow ( ) means –.
The black dot at an arrow ( ) indicates the start of measurement.

<Horizontal Shift Register Driving Waveform>

Hst rise time

HST

HCK

Hst fall time

Hst data set-up time

Hst data hold time

Hckn rise time

∗5

Hckn fall time

∗5

Hck1 fall to Hck2 rise time

Hck1 rise to Hck2 fall time

• Hckn

∗5

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗5

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

• Hckn

∗5

duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns

trHst

tfHst

tdHst

thHst

trHckn

tfHckn

to1Hck

to2Hck

Item Symbol Waveform Conditions

90%

10%

10%

90%

Hst

trHst tfHst

50%

50%

∗

8

Hst

Hck1

tdHst thHst

50%

50%

∗

5

Hckn

10%

10%

90%

90%

trHckn tfHckn

50%

50%

∗

8

Hck1

to2Hck to1Hck

50%

50%

Hck2

– 9 –

LCX028AMT

<Vertical Shift Register Driving Waveform>

VCK

Vck rise time

Vck fall time

trVck

tfVck

Item Symbol Waveform Conditions

Vck

10%

10%

90%

90%

trVckn tfVckn

Vst rise time

VST

Vst fall time

Vst data set-up time

Vst data hold time

trVst

tfVst

tdVst

thVst

90%

10%

10%

90%

Vst

trVst tfVst

50%

50%

∗

8

Vst

Vck

tdVst thVst

50%

50%

ENB

Enb rise time

Enb fall time

Horizontal video period
completed to Enb fall time

trEnb

tfEnb

tdEnb

Enb rise to PRG∗4fall time

Enb fall to Pcg rise time

toPRG

∗4

toPcg

Enb pulse width

twEnb

90%

90%

10%

10%

tfEnb trEnb

Enb

50%

50%

toPRG

∗

4

Enb

∗

8

50%

PRG

∗

4

H. Blanking periodH. Video period

tdEnb

PCG

50%

toPcg

50%

twEnb

– 10 –

LCX028AMT

Item Symbol Waveform Conditions

PRG∗4fall to Pcg fall time

PRG

∗4

toPcgf

PRG∗4pulse width

twPRG

∗4

50%

∗

8

PRG

∗

4

Pcg

toPcgf

50%

50%

twPRG

∗

4

toPcgr

50%

∗

8

Blk

50%

toPcg

50%

toEnb

50%

50%

Pcg

Enb

BLK

Blk rise time

trBlk

Blk fall time

tfBlk

Blk rise to Enb fall time toEnb

Blk fall to Pcg rise time

toPcg

90%

10%

10%

90%

tfBlk trBlk

∗9

PCG input pin and PRG∗4should be "H" level during the horizontal 1H period, where the above BLK is low
more than 10ns.

∗9

twPcg

50%

50%

toVideo

Pcg

∗

8

50%

Vck

H. blanking period H. video period

toVck

PCG

∗9

Pcg rise time

trPcg

Pcg fall time

tfPcg

Pcg rise to Vck rise/fall
time

toVck

Pcg fall to horizontal
video period start time

Pcg pulse width

PRG∗4rise to Pcg rise time

toVideo

twPcg

toPcgr

90%

10%

10%

90%

Pcg

trpcg tfpcg

– 11 –

LCX028AMT

Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)

1. Horizontal drivers

Item

Input pin capacitance HCKn

HST

Input pin current HCK1

HCK2
HST

RGT
Video signal input pin capacitance
Current consumption

CHckn
CHst

Csig
IH

HCK1 = GND
HCK2 = GND
HST = GND
RGT = GND

HCKn: HCK1, HCK2 (4.5MHz)

—

—
–1000
–1000

–500
–150

—

—

35

25
–500
–500
–190

–40
200

17.0

40
30
—
—
—
—

250

25.0

pF
pF
µA
µA
µA
µA
pF

mA

Symbol Min. Typ. Max. Unit Condition

2. Vertical drivers

Item

Input pin capacitance VCK

VST
Input pin current VCK,PCG
VST, ENB, DWN, BLK, HB,

VB
Current consumption

CVck
CVst

IV

—
—

–500
–150

—

15
15

–150

–35

4.0

20
20
—

—

6.0

pF
pF

µA
µA

mA

Symbol Min. Typ. Max. Unit Condition

3. Total power consumption of the panel

4. Pin input resistance

Item

Pin – VSS input resistance Rpin 0.4 1 — MΩ

Symbol Min. Typ. Max. Unit

Item

COM pin capacitance
(COM, COML, COMR Total)

COM — 25 30 nF

Symbol Min. Typ. Max. Unit

Item

Total power consumption of the panel

PWR — 330 480 mW

Symbol Min. Typ. Max. Unit

VCK = GND, PCG = GND
VST, ENB, DWN,BLK, HB

VB = GND
VCK: (32.0kHz)

5. Uniformity improvement signal

Item

Input pin capacitance for uniformity
improvement signal

CPSIGo 15 nF

Symbol Min. Typ. Max. Unit

—

18

6. COM pin capacitance

– 12 –

LCX028AMT

Reflection Preventive Processing

When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.

Electro-optical Characteristics (SXGA mode)

Item

Contrast ratio

25°C
25°C

25°C

60°C

25°C

60°C

25°C

60°C

0°C

25°C

0°C
25°C
60°C
25°C
25°C

CR
T
RV90-25
GV90-25
BV90-25
RV90-60
GV90-60
BV90-60
RV50-25
GV50-25
BV50-25
RV50-60
GV50-60
BV50-60
RV10-25
GV10-25
BV10-25
RV10-60
GV10-60
BV10-60
ton0
ton25
toff0
toff25
F
YT60
CTK

1
2

3

4

5
6
7

—
%

V

ms

dB

s

%

Optical transmittance

V-T
characteristics

V90

V50

ON time

OFF time

V10

Response time

Flicker
Image retention time
Cross talk

Symbol Measurement method Min. Typ. Max. Unit

150

24

0.9

1.0

1.2

0.9

1.0

1.1

1.3

1.4

1.5

1.2

1.3

1.4

1.7

1.8

1.9

1.7

1.8

1.8
—
—
—
—
—
—
—

250

27

1.3

1.4

1.6

1.3

1.4

1.5

1.7

1.8

1.9

1.6

1.7

1.8

2.1

2.2

2.3

2.1

2.2

2.2

24.0

9.0

99.0

27.0

–82.0

0

—

—
—

1.6

1.7

1.9

1.6

1.7

1.8

2.0

2.1

2.2

1.9

2.0

2.1

2.4

2.5

2.6

2.4

2.5

2.5

80.0

40.0

200.0

70.0

–40.0

—

5

– 13 –

LCX028AMT

<Electro-optical Characteristics Measurement>

• Measurement system I

• Measurement system II

Luminance

Meter

Measurement

Equipment

Light Detector

Measurement

Equipment

Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent
Projection lens: Focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(× 24, Sensor area: 7mmφ)
Polarizer: Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T or equivalent

Optical fiber

LCD panel

Light receptor lens

Drive Circuit

Light

Source

Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.0V, Vcom = 6.5V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement systems are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V] (VAC = signal amplitude)

Screen

LCD Projector

Approx. 2000mm

1. Contrast Ratio

Contrast Ratio (CR) is given by the following formula (1).

CR =

L (White)

... (1)

L (Black)

L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 4.5V.
Both luminosities are measured by System I.

– 14 –

LCX028AMT

2. Optical Transmittance

Optical Transmittance (T) is given by the following formula (2).

White luminance

T = × 100 [%] ... (2)

Luminance of light source

"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V
on Measurement System I.

3. V-T Characteristics

V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.

4. Response Time

Response time ton and toff are defined by
formulas (5) and (6) respectively.

ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)

t1: time which gives 10% transmittance of

the panel.

t2: time which gives 90% transmittance of

the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.

90

50

10

V

90 V50 V10

VAC – Signal amplitude [V]

Transmittance [%]

Input signal voltage (Waveform applied to the measured pixels)

4.5V

0.5V

7.0V

0V

Optical transmittance output waveform

100%

90%

10%

0%

tON t1

ton

tOFF t2

toff

– 15 –

LCX028AMT

5. Flicker

Flicker (F) is given by formula (7). DC and AC (SXGA: 30Hz, rms) components of the panel output signal
for gray raster∗mode are measured by a DC voltmeter and a spectrum analyzer in System II.

F [dB] = 20log

{

AC component

}

...(7)

DC component

6. Image Retention Time

Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.

∗

Monoscope signal conditions:
Vsig = 7.0 ± 4.5 or ±2.0 [V]
(shown in the right figure)
Vcom = 6.6V

7. Cross Talk

Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V).

Cross talk value CTK = × 100 [%]

∗

Each input signal voltage for gray raster mode
is given by Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.

Black level

White level

Vsig waveform

7.0V

0V

4.5V

2.0V

4.5V

2.0V

W1

W1

'

W3

W3

'

W2
W2

' W4'

W4

Wi' – Wi

Wi

– 16 –

LCX028AMT

Viewing angle characteristics (without microlens)

90

270

180

0

Theta

Phi

7050

100

150

200

250

50

20

10

CR = 5

10 30

θ

φ

φ180°

X

φ270°

Y

φ0°

φ90°

Z

θ0°

Marking

Measurement method

– 17 –

LCX028AMT

Optical transmittance of LCD panel (Typical Value)

30

20

10

0

400 500 600 700

Wavelength [nm]

Trans. [%]

Measurement method: Measurement system II

– 18 –

LCX028AMT

1. Dot Arrangement

The dots are arranged in a stripe. The shaded area is used for the dark border around the display.

8 dots

1296 dots

8 dots

1032 dots

4 dots

1280 dots (Effective 35.84mm)

1024 dots (Effective 28.672mm)

4 dots

Active area

Photo-Shielding

Gate SW Gate SWGate SW Gate SW

– 19 –

LCX028AMT

2. LCD Panel Operations

[Description of basic operations]

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse

to every 1024 gate lines sequentially in a single horizontal scanning period. (SXGA mode)

• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1280 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.

• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 1024 × 1280 dots to display a
picture in a single vertical scanning period.

• The data and video signals shall be input with the 1H-inverted system.

[Description of operating mode]

This LCD panel can change the active area by displaying a black frame to support various computer or video
signals. The active area is switched by VB1, VB2 and BLK. However, the center of the screen is not changed.
The active area setting modes are shown below.

HB VB BLK Screen aspect ratio

H H

H

L

H

∗1

∗1

5:4

1280 × 1024

4:3

1280 × 960

16:9

1280 × 720

L

L

∗1

Input BLK pulse (refer to drive waveform and vertical blanking period of black frame mode).

– 20 –

LCX028AMT

(1) Vertical direction display cycle (DWN = H, L)

RGT Mode

Right scan
Left scan

H
L

DWN Mode

Down scan
Up scan

H

L

This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.

• Right/left inverse mode

• Up/down inverse mode

These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below.

Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.

To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
both the H and V systems must be varied. The phase relationship between the start pulse and the clock for
each mode is shown below.

Vertical display cycle 1024H

VD

1 2

VCK

3 102110221023

VST

1024

4

(1.1) SXGA

– 21 –

LCX028AMT

(2) Horizontal direction display cycle

(2.1.1) SXGA (RGT = H)

1 2 3 4

Horizontal display cycle

HST

HCK1

105 106 107 108

HCK2

HD

(2.1.2) SXGA (RGT = L)

Horizontal display cycle

HST

HCK1

1 2 3 4 105 106 107 108

HCK2

HD

(3) Vertical blanking cycle of black frame mode (4:3 and 16:9 display mode)

The input waveforms of PCG, PRG∗1and PSIG should be changed as shown below when BLK pulse is input.

BLK

VCK

ENB

PCG

PRG

∗

1

PSIG

Vertical blanking cycle

∗1

PRG shows the period of PSIG black level, it is not input to the panel.

– 22 –

LCX028AMT

3. 12-dot Simultaneous Sampling

The horizontal shift register samples signals VSIG1 to VSIG12 simultaneously. This requires phase
matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus,
phase matching between each signal is required using an external signal delaying circuit before applying
the video signal to the LCD panel.

The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT =
Low level), the phase settings for signals VSIG1 to VSIG12 are exactly reversed.

VSIG1

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

CK6

VSIG2

VSIG3

VSIG4

VSIG5

VSIG6

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12

3

4

5

6

7

8

9

10

11

12

13

14

LCX028AMT

S/H

CK5

S/H

CK4

S/H

CK3

S/H

CK2

S/H

CK1

CK6

S/H

CK5

S/H

CK4

S/H

CK3

S/H

CK2

S/H

CK1

VSIG (odd)

VSIG (even)

– 23 –

LCX028AMT

<Phase relationship of delaying sample-and-hold pulses> (right scan)

HCKn

CK1

CK2

CK3

CK4

CK5

CK6

Display System Block Diagram

An example of display system is shown below.

Digital
Signal
Driver

CXD2467Q

R-IN

G-IN

B-IN

VSYNC

HSYNC

D/A

D/A

D/A

D/A

D/A

D/A

OSC

MCK

CXA3197R

S/H Driver
CXA2112R

S/H Driver
CXA2112R

S/H Driver
CXA2112R

S/H Driver
CXA2112R

S/H Driver
CXA2112R

S/H Driver
CXA2112R

LCX028

LCX028

LCX028

FRP · PRG

HCK · VCK

– 24 –

LCX028AMT

Notes on Handling

(1) Static charge prevention

Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.

(2) Protection from dust and dirt

a) Operate in a clean environment.
b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective

sheet carefully so as not to damage the glass panel.

c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a clean-

room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.

d) Use ionized air to blow dust off the glass panel.

(3) Other handling precautions

a) Do not twist or bend the flexible PC board especially at the connecting region because the board is

easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel

damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 3kg · cm or less.
i) Use appropriate filter to protect a panel.
j) Do not pressure the portion other than mounting hole (cover).

– 25 –

LCX028AMT

Package Outline Unit: mm

Active Area

Incident

light

Incident light
Polarizing Axis

1

4

3

5

2

7

9

8

6

Description

Molding material

Outside frame

Reinforcing board

Reinforcing material

F P C

No

1
2
3
4
5
6

Cover 1

7
8

Cover 2

9

Glass 1
Glass 2

weight 25g

The rotation angle of the active area relative to H and V is ± 1°.

electrode (enlarged)

0.5 ± 0.1

0.5 ± 0.15

4.0 ± 0.4

PIN32

PIN1

(28.7)

50.0 ± 0.15

40.0 ± 0.1

5.0 ± 0.1

25.0 ± 0.25

(35.8)

25.0 ± 0.25

3.0 ± 0.1

50.0 ± 0.1

56.0 ± 0.15

107.6 ± 1.4

(51.6)

2.2 ± 0.1

2.3 ± 0.1

5.4 ± 0.1

16.5 ± 0.05

φ2.2 ± 0.1

4-R3.0

Thickness of the connector 0.3 ± 0.05

3-φ2.3 ± 0.05
C0.8

Output light
Polarizing Axis

P 0.5 ± 0.02 × 31 = 15.5 ± 0.03

0.35 ± 0.03