Datasheet LCK4802 Datasheet (AGERE)

LCK4802
Low-Voltage PECL Differential Clock

Preliminary Data Sheet

July 2001

General

The LCK4802 is a low-voltage, 3.3 V PECL
differential clock synthesizer. The LCK4802 supports
two differential PECL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multip le proces so r systems that
require PECL differential inputs. The LCK4802
contains a fully integrated PLL (phase-locked loop)
which multiplies the PECL_CLK input frequency to
match individual processor clock frequencies. The
PLL can be bypassed so that the PCLK outputs are
fed from the PECL_CLK or PECL_CLK input for test
purposes. All outputs are powered from a 2 V
external supply to reduce on-chip power
consumption. All outputs are PECL. The PLL can
operate in the internal feedback mode, or in the
external feedback mode for board level debugging
applications.

Description

Features

■

Two fully selectable clock inputs.

■

Fully integrated PLL.

■

336 MHz to 1 GHz output frequencies.

■

PECL outputs.

■

PECL reference clock.

■

32-pin TQFP package.

PCLK0_EN (PULL-UP)
PCLK1_EN (PULL-UP)

TESTM

(PULL-UP)

PLLREF_EN (PULL-UP)

REF_SEL (PULL-UP)

PECL_CLK (PULL-UP)
PECL_CLK

PECL_CLK (PULL-UP)
PECL_CLK

EXTFB_EN

PLL_BYPASS

(PULL-UP)

(PULL-UP)

(PULL-UP)

EXTFB_IN (PECL)

(PULL-DOWN)

(PULL-UP)

SEL[4:0] (PULL-UP)

(PULL-UP)

RESET

(PULL-UP)

1

0

1

/M

DECODE

0

PLL

0

1

/N

Figure 1. LCK4802 Logic Diagram

0

1

PCLK0

PCLK0

(PECL)

PCLK1

(PECL)

PCLK1

EXTFB_OUT

EXTFB_OUT

(PECL)

2274.b (F)

LCK4802
Low-Voltage PECL Differential Clock

Preliminary Data Sheet

July 2001

Description

(continued)

V

RESET

SEL[4]

SEL[3]

SEL[2]

SEL[1]

SEL[0]

DDA

V

PLL_BYPASS

24 1723 22 21 20 19 18

25

SS

26

27

28

29

30

31

32

18234567

DDD

V

DDPECL

PLLREF_EN

V

SS

V

TESTM

PCLK0

PCLK0

PCLK1

PCLK0_EN

REF_SEL

PCLK1_EN

DDPECL

PCLK1

V

EXTFB_OUT

16

EXTFB_OUT

15

V

PECL_CLK

9

DDPECL

EXTFB_IN

EXTFB_IN

EXTFB_EN

PECL_CLK

PECL_CLK

2275 (F)

14

13

12

11

10

PECL_CLK

Figure 2. 32-Pin TQFP

2 Agere Systems Inc.

Preliminary Data Sheet
July 2001

Pin Information

Table 1. Pin Description

Pin Number Pin Name

I/O

LCK4802

Low-Voltage PECL Differential Clock

1

Type Description

1V

DDD

2TESTM
3V

SS

P Power Supply 3.3 V power supply.

I LVCMOS M divider test pins.

G Ground Digital ground.
4 PCLK0_EN I LVCMOS PCLK0 enable.
5 PCLK1_EN I LVCMOS PCLK1 enable.
6 REF_SEL I LVCMOS Selects the PLL input reference clock.
7 PECL_CLK I Differential PECL PLL reference clock input.
8 PECL_CLK

I Differential PECL PLL reference clock input.

9 PECL_CLK I Differential LVPECL PLL reference clock input.

10 PECL_CLK
11 EXTFB_EN

I Differential LVPECL PLL reference clock input.

I LVCMOS External feedback enable.
12 EXTFB_IN I Differential PECL External feedback input.
13 EXTFB_IN
14 V

DDPECL

15 EXTFB_OUT

I Differential PECL External feedback input.

P Power Supply Output buffers power supply.

O Differential PECL External feedback output clock.
16 EXTFB_OUT O Differential PECL External feedback output clock.
17 V

DDPECL

18 PCLK1

P Power Supply Output buffers power supply.

O Differential PECL Output clock 1.
19 PCLK1 O Differential PECL Output clock 1.
20 PCLK0

O Differential PECL Output clock 0.
21 PCLK0 O Differential PECL Output clock 0.
22 VDDPECL

P Power Supply Output buffers power supply.
23 PLLREF_EN I LVCMOS PLL reference enable.
24 PLL_BYPASS
25 V

SS

26 RESET

I LVCMOS Input signal PLL bypass.

P Ground Analog ground for PLL.

I LVCMOS PLL bypass reset (for test use).
27 SEL[4] I LVCMOS Selection of input and feedback frequency.
28 SEL[3] I LVCMOS Selection of input and feedback frequency.
29 SEL[2] I LVCMOS Selection of input and feedback frequency.
30 SEL[1] I LVCMOS Selection of input and feedback frequency.
31 SEL[0] I LVCMOS Selection of input and feedback frequency.
32 V

1. P = power, I = input, G = ground, O = output.

DDA

P Power Supply 3.3 V filtered for PLL (PLL power supply).

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LCK4802
Low-Voltage PECL Differential Clock

Preliminary Data Sheet

July 2001

Pin Information

Table 2. Frequency Selection

Selection Input

4 3 2 1 0 M N 70 100 120 125

0 0 0 0 0 5 24 336 480 576 600
0 0 0 0 1 5 25 350 500 600 625
0 0 0 1 0 5 26 364 520 624 650
0 0 0 1 1 5 27 378 540 648 675
0 0 1 0 0 5 28 392 560 672 700
0 0 1 0 1 5 29 406 580 696 725
0 0 1 1 0 5 30 420 600 720 750
0 0 1 1 1 5 31 434 620 744 775
0 1 0 0 0 5 32 448 640 768 800
0 1 0 0 1 5 33 462 660 792 825
0 1 0 1 0 5 34 476 680 816 850
0 1 0 1 1 5 35 490 700 840 875
0 1 1 0 0 5 36 504 720 864 900
0 1 1 0 1 5 37 518 740 888 925
0 1 1 1 0 5 38 532 760 912 950
0 1 1 1 1 5 39 546 780 936 975
1 0 0 0 0 5 40 560 800 960 1000
1 0 0 0 1 5 41 564 820 984 NA
1 0 0 1 0 5 42 588 840 NA NA
1 0 0 1 1 5 43 602 860 NA NA
1 0 1 0 0 5 44 616 880 NA NA
1 0 1 0 1 5 45 630 900 NA NA
1 0 1 1 0 5 46 644 920 NA NA
1 0 1 1 1 5 47 658 940 NA NA
1 1 0 0 0 5 48 672 960 NA NA
1 1 0 0 1 5 49 686 980 NA NA
1 1 0 1 0 5 50 700 1000 NA NA
11011 5 51 714 NA NA NA
11100 5 52 728 NA NA NA
11101 5 53 742 NA NA NA
11110 5 54 756 NA NA NA
11111 5 55 770 NA NA NA

(continued)

Divide

Feedback

Divide

PCLK (MHz)

for Given Input Frequency (MHz)

4 Agere Systems Inc.

Preliminary Data Sheet
July 2001

LCK4802

Low-Voltage PECL Differential Clock

Pin Information

(continued)

Table 3. Function Control

Control Pin 0 1

REF_SEL PECL_CLK. PECL_CLK.

TESTM

PLLREF_EN Disable the input to the PLL and reset

M divider test mode enabled. Reference fed to bypass MUX.

Enable the input to the PLL.

the M divider.

PLL_BYPASS

Outputs fed by input reference or M

Outputs fed by VCO.

divider.
EXTFB_EN
PCLK0_EN PCLK0 = low, PCLK 0
PCLK1_EN PCLK1 = low, PCLK 1

RESET

External feedback enabled. Internal feedback enabled.

= high. PCLK0 = high, PCLK0 = lo w.
= high. PCLK1 = high, PCLK1 = lo w.

Resets feedback N divider. Feedback enabled.

SEL[4:0] See Table 2 on page 4. See Table 2 on page 4.

Absolute Maximum Characteristics

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.

Table 4. Absolute Maximum Ratings

Parameter Symbol Min Typical Max Unit

Power Supply V

Input Voltage V
Write Current I
Storage Temperature T

DDD/VDDA

V

DDPECL

IN

IN

S

–0.5 — 4.4 V
–0.5 — 4.4
–0.5 — V

DDD

+ 0.3 V

–1 — 1 mA

–50 — 150 °C

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LCK4802
Low-Voltage PECL Differential Clock

Electrical Characteristics

Table 5. dc Characteristics

Preliminary Data Sheet

July 2001

V

DDA

= V

DDD

= 3.3 V ± 5%, V

DDPECL

= 1.7 V—2.1 V, TA = 0 °C—70 °C.

Symbol Description Min Typ Max Unit Condition

V

IH

V

V

CMR

V

PP

V

OH

V

OL

DDI

I

I

DDA

I

DDO

Theta

IL

JA

Input High Voltage 2.2 — 2.4 V LVCMOS
Input Low Voltage 1.5 — 1.8 V LVCMOS
Input High Voltage
Input Low Voltage

1

1

DDD

V

– 1.3 — V

DDD

– 0.5 V LVPECL

0.5 — — V LVPECL
Output High Voltage 2.0 — 2.6 V PECL
Output Low Voltage 1.3 — 1.9 V PECL
Core Supply Current — — 140 mA —
PLL Supply Current — 15 20 mA —
Output Supply Current — 150 — mA —
Junction to Ambient

—53—°C/W—

Thermal Resistance

1. dc levels will vary 1:1 with V

2. Two PCLK signals to 25 Ω, and one EXTFB signal through 50 Ω.

3. 1.3 M/s (250 fpm) airflow.

DDD

.

2
3

6 Agere Systems Inc.

Preliminary Data Sheet
July 2001

LCK4802

Low-Voltage PECL Differential Clock

Electrical Characteristics

(continued)

T a ble 6. ac Characteristics

V

DDA

= V

DDD

= 3.3 V ± 5%, V

DDPECL

= 1.7 V—2.1 V, TA = 0 °C—70 °C.

Symbol Description Min Typ Max Unit Condition

fref Input Frequen cy — 70—125 — MHz —

fMAX Maximum Output

336 — 1000 MHZ —

1

Frequency

tsk (o) Skew Error (PCLK) — — 35 ps —

jit (0)

t

jit (cc)

t

Phase Jitter (I/O Jitter) — — (output period)/2 — —
Cycle-to-Cycle Jitter

—— 5 %—

2

2

3

2,

(Full Period)

4

jit (1/2 period)

t

Cycle-to-Cycle Jitter

—— 8 %—

2,

(Half Period)

DIFout

V

V

X

t

lock

1. When the phase-locked loop is active but in bypass mode, fref maximum is limited by input the buffer; optimum performance is obtained
from PECL input.

2. A t differential pair crossover.

3. Full PC LK period.

4. Half PCLK period.

Differential Output

Peak-to-Peak Swing

Differential Output

Crosspoint Voltage

0.6 — — V For all PECL
output pairs.

0.68 — 0.9 V For all PECL
output pairs.

Maximum PLL Lock Time — — 10 ms —

V
V

V

DIF

V

CM

V

V
V

Figure 3. PECL Differential Input Levels

Z = 50 Ω

OUTPUT

R

T

= 25 Ω

V

= V

(GROUND)

TT

SS

Figure 4. Output Termination and ac Test Reference

DDPECL
OH

X

OL
SS

2276 (F)

2277.a (F)

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LCK4802
Low-Voltage PECL Differential Clock

Preliminary Data Sheet

July 2001

Applications

Power Supply Filtering

The LCK4802 is a mixed analog/digital product. Because of this, it exhibits some sensitivities that would not
necessarily be seen on a fully digital product. Analog circuitry is susceptible to random noise, the worst case being
when this noise is seen on the power supply pins. The LCK4802 provides separate power supplies for the output
buffers (V
switching noise from the internal analog PLL. In a controlled evaluation board environment, this level of isolation is
adequate. However, in a digital system, a second level of isolation is suggested.

DDPECL

) and the phase-locked loop (V

DDA

) of the device in order to isolate the high digital output

The easiest way to accomplish this is to add a power supply filter on the V

DDA

pin of the LCK4802. Figure 5 on
page 9 shows the typical power supply scheme. The filter should be designed in the 10 kHz—1 MHz range, since
this is the most likely frequency range to cause spectral content noise.

Note the dc voltage drop between V
tolerated when a 3.3 V V

DDD

supply is used. The power supply filter in Figure 5 must be 5 Ω—10 Ω in order to

DDD

and V

DDA

on the power supply filter. Very little dc voltage drop can be

meet the drop criteria. The RC filter in Figure 5 will provide a broadband filter with approximately 100:1 attenuation
above 20 kHz.

The impedance of an individual capacitor begins to appear inductive and increases with frequency as the noise
frequency crosses the series resonant point of the capacitor. The parallel capacitor combination ensures that for
frequencies much greater than the bandwidth of the PLL there is always a low-impedance path.

8 Agere Systems Inc.

Preliminary Data Sheet
July 2001

LCK4802

Low-Voltage PECL Differential Clock

Applications

(continued)

VDDA

DDD

V

0.01 µF

3.3 V

RS = 5—10 Ω

22 µF

0.01 µF

2278 (F)

Figure 5. Power Supply Filter

Although the LCK4802 has an isolated power supply and grounds, as well as fully differential PLL, there still may
be applications in which overall performance is being compromised due to system power supply noise. The power
supply filter schemes discussed are adequate to eliminate power supply noise problems in most designs.

Agere Systems Inc. 9

LCK4802
Low-Voltage PECL Differential Clock

Outline Diagram

Dimensions are in millimeters.

9.00 ± 0.20

7.00 ± 0.20

PIN #1
IDENTIFIER ZON E

32 25

1

24

7.00

± 0.20

Preliminary Data Sheet

July 2001

1.00 REF

0.25

GAGE PLANE

SEATING PLANE

0.45/0.75

DETAIL A

9.00

± 0.20

8

9

16

17

0.09/0.200

DETAIL A

DETAIL B

1.40 ± 0.05

1.60 MAX

0.30/0.45

DETAIL B

0.20

M

SEATING PLANE

0.10

0.80 TYP

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Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

0.05/0.15

12-3076(F)

Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.

July 2001
DS01-265HSI