The LCK4802 is a low-voltage, 3.3 V PECL
differential clock synthesizer. The LCK4802 supports
two differential PECL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multip le proces so r systems that
require PECL differential inputs. The LCK4802
contains a fully integrated PLL (phase-locked loop)
which multiplies the PECL_CLK input frequency to
match individual processor clock frequencies. The
PLL can be bypassed so that the PCLK outputs are
fed from the PECL_CLK or PECL_CLK input for test
purposes. All outputs are powered from a 2 V
external supply to reduce on-chip power
consumption. All outputs are PECL. The PLL can
operate in the internal feedback mode, or in the
external feedback mode for board level debugging
applications.
PPower SupplyOutput buffers power supply.
23PLLREF_ENILVCMOSPLL reference enable.
24PLL_BYPASS
25V
SS
26RESET
ILVCMOSInput signal PLL bypass.
PGroundAnalog ground for PLL.
ILVCMOSPLL bypass reset (for test use).
27SEL[4]ILVCMOSSelection of input and feedback frequency.
28SEL[3]ILVCMOSSelection of input and feedback frequency.
29SEL[2]ILVCMOSSelection of input and feedback frequency.
30SEL[1]ILVCMOSSelection of input and feedback frequency.
31SEL[0]ILVCMOSSelection of input and feedback frequency.
32V
1. P = power, I = input, G = ground, O = output.
DDA
PPower Supply3.3 V filtered for PLL (PLL power supply).
Agere Systems Inc.3
Page 4
LCK4802
Low-Voltage PECL Differential Clock
Preliminary Data Sheet
July 2001
Pin Information
Table 2. Frequency Selection
SelectionInput
43210MN70100120125
00000524336480576600
00001525350500600625
00010526364520624650
00011527378540648675
00100528392560672700
00101529406580696725
00110530420600720750
00111531434620744775
01000532448640768800
01001533462660792825
01010534476680816850
01011535490700840875
01100536504720864900
01101537518740888925
01110538532760912950
01111539546780936975
100005405608009601000
10001541564820984NA
10010542588840NANA
10011543602860NANA
10100544616880NANA
10101545630900NANA
10110546644920NANA
10111547658940NANA
11000548672960NANA
11001549686980NANA
110105507001000NANA
11011551714 NA NA NA
11100552728 NA NA NA
11101553742 NA NA NA
11110554756 NA NA NA
11111555770 NA NA NA
(continued)
Divide
Feedback
Divide
PCLK (MHz)
for Given Input Frequency (MHz)
4Agere Systems Inc.
Page 5
Preliminary Data Sheet
July 2001
LCK4802
Low-Voltage PECL Differential Clock
Pin Information
(continued)
Table 3. Function Control
Control Pin01
REF_SELPECL_CLK.PECL_CLK.
TESTM
PLLREF_ENDisable the input to the PLL and reset
M divider test mode enabled.Reference fed to bypass MUX.
= high.PCLK0 = high, PCLK0 = lo w.
= high.PCLK1 = high, PCLK1 = lo w.
Resets feedback N divider.Feedback enabled.
SEL[4:0]See Table 2 on page 4.See Table 2 on page 4.
Absolute Maximum Characteristics
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
1. When the phase-locked loop is active but in bypass mode, fref maximum is limited by input the buffer; optimum performance is obtained
from PECL input.
2. A t differential pair crossover.
3. Full PC LK period.
4. Half PCLK period.
Differential Output
Peak-to-Peak Swing
Differential Output
Crosspoint Voltage
0.6——VFor all PECL
output pairs.
0.68—0.9VFor all PECL
output pairs.
Maximum PLL Lock Time——10ms—
V
V
V
DIF
V
CM
V
V
V
Figure 3. PECL Differential Input Levels
Z = 50 Ω
OUTPUT
R
T
= 25 Ω
V
= V
(GROUND)
TT
SS
Figure 4. Output Termination and ac Test Reference
DDPECL
OH
X
OL
SS
2276 (F)
2277.a (F)
Agere Systems Inc.7
Page 8
LCK4802
Low-Voltage PECL Differential Clock
Preliminary Data Sheet
July 2001
Applications
Power Supply Filtering
The LCK4802 is a mixed analog/digital product. Because of this, it exhibits some sensitivities that would not
necessarily be seen on a fully digital product. Analog circuitry is susceptible to random noise, the worst case being
when this noise is seen on the power supply pins. The LCK4802 provides separate power supplies for the output
buffers (V
switching noise from the internal analog PLL. In a controlled evaluation board environment, this level of isolation is
adequate. However, in a digital system, a second level of isolation is suggested.
DDPECL
) and the phase-locked loop (V
DDA
) of the device in order to isolate the high digital output
The easiest way to accomplish this is to add a power supply filter on the V
DDA
pin of the LCK4802. Figure 5 on
page 9 shows the typical power supply scheme. The filter should be designed in the 10 kHz—1 MHz range, since
this is the most likely frequency range to cause spectral content noise.
Note the dc voltage drop between V
tolerated when a 3.3 V V
DDD
supply is used. The power supply filter in Figure 5 must be 5 Ω—10 Ω in order to
DDD
and V
DDA
on the power supply filter. Very little dc voltage drop can be
meet the drop criteria. The RC filter in Figure 5 will provide a broadband filter with approximately 100:1 attenuation
above 20 kHz.
The impedance of an individual capacitor begins to appear inductive and increases with frequency as the noise
frequency crosses the series resonant point of the capacitor. The parallel capacitor combination ensures that for
frequencies much greater than the bandwidth of the PLL there is always a low-impedance path.
8Agere Systems Inc.
Page 9
Preliminary Data Sheet
July 2001
LCK4802
Low-Voltage PECL Differential Clock
Applications
(continued)
VDDA
DDD
V
0.01 µF
3.3 V
RS = 5—10 Ω
22 µF
0.01 µF
2278 (F)
Figure 5. Power Supply Filter
Although the LCK4802 has an isolated power supply and grounds, as well as fully differential PLL, there still may
be applications in which overall performance is being compromised due to system power supply noise. The power
supply filter schemes discussed are adequate to eliminate power supply noise problems in most designs.
Agere Systems Inc.9
Page 10
LCK4802
Low-Voltage PECL Differential Clock
Outline Diagram
Dimensions are in millimeters.
9.00 ± 0.20
7.00 ± 0.20
PIN #1
IDENTIFIER ZON E
3225
1
24
7.00
± 0.20
Preliminary Data Sheet
July 2001
1.00 REF
0.25
GAGE PLANE
SEATING PLANE
0.45/0.75
DETAIL A
9.00
± 0.20
8
9
16
17
0.09/0.200
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
0.30/0.45
DETAIL B
0.20
M
SEATING PLANE
0.10
0.80 TYP
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:http://www.agere.com
E-MAIL:docmaster@micro.lucent.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-41 06)
ASIA PACIFIC: Agere Systems Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:Agere Systems (Shanghai) Co., Ltd., 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
Tel. (86) 21 50471212, FAX (86) 21 50472266
JAPAN:Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chom e, Shinagawa- k u, Tokyo 141, Japan
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.