Page 1
Hex Schmitt-Trigger Inverter
The 74LV14 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT14.
The 74LV14 provides six inverting buffers with Schmitt-trigger
action.
•
Wide Operating Voltage: 1.0 to 5.5 V
•
Optimized for Low Voltage applications: 1.0 to 3.6 V
•
Accepts TTL input levels between V
•
Low input current
=2.7 V and VCC =3.6 V
CC
TECHNICAL DATA
IN74LV14
ORDERING INFORMATION
IN74LV14N Plastic
IN74LV14D SOIC
IZ74LV14 Chip
TA = -40° ÷ 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Input Output
A
LH
HL
Y=
A
PIN 14 =V
PIN 7 = GND
CC
1
Page 2
IN74LV14
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
IIK*
IOK*
Io*
CC
DC supply voltage (Referenced to GND)
1
DC input diode current
2
DC output diode current
3
DC output source or sink current
-0.5 ÷ +7.0
±
20
±
50
±
25
-bus driver outputs
I
GND
DC GND current for types with
±
50
- bus driver outputs
I
CC
DC VCC current for types with
±
50
- bus driver outputs
P
Tstg Storage temperature
T
Power dissipation per paskade, plastic DIP+
D
SOIC package+
Lead temperature, 1.5 mm from Case for 10 seconds
L
750
500
-65 ÷ +150
260
(Plastic DIP ), 0.3 mm (SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
1
: V
*
2
: Vo < -0.5V or Vo > VCC+0.5V
*
3
: -0.5V < Vo < VCC+0.5V
*
SOIC Package: : - 8 mW/°C from 70° to 125°C
<
-0.5V or V
I
>
V
+0.5V
I
CC
V
mA
mA
mA
mA
mA
mW
°
C
°
C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
VIN, V
T
tr, t
CC
A
f
DC Supply Voltage (Referenced to GND) 1.0 5.5 V
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -40 +125
Input Rise and Fall Time
1.0 V≤V
2.0 V≤V
2.7 V≤V
3.6 V≤V
<2.0 V
CC
<2.7 V
CC
<3.6 V
CC
≤5.5 V
CC
0
0
0
0
CC
500
200
100
50
V
°
C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
and V
IN
should be constrained to the range
OUT
CC
Unused outputs must be left open.
2
).
Page 3
IN74LV14
DC ELECTRICAL CHARACTERISTICS
V
Symbol Parameter
VIT+ Positive-Going
Input Threshold
Voltage
VIT- Negative-Going
Input Threshold
Voltage
V
H
Hysteresis
Voltage
V
OH
High-Level
Output Voltage
V
OH
High-Level
Output Voltage
V
OL
Low-Level
Output Voltage
Test
Conditions
≥
V
V
O
OH
≤
V
V
O
OL
≥
V
V
O
OH
≤
V
V
O
OL
VI = V
IH
or V
IL
IO = -100
µ
A
VI = V
IH
or V
IL
IO = -6.0
mA
V
= V
I
IH
or V
IL
IO = -12.0
mA
VI = V
IH
or V
IL
IO = 100
µ
A
CC
V
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
2.0
2.7
3.0
3.6
4.5
5.5
1.2
–
2.0
2.7
3.0
3.6
4.5
5.5
3.0 2.48 - 2.40 - 2.20 -
–
4.5 3.70 - 3.60 - 3.50 -
–
1.2
–
2.0
2.7
3.0
3.6
4.5
5.5
(Voltages Referenced to GND)
Guaranteed Limit
25°C-40
°C ÷
85°C-40
°C ÷
125°C
min max min max min max
0.45
0.85
1.05
1.25
1.55
1.75
2.15
0.2
0.35
0.45
0.65
0.85
0.95
1.15
0.2
0.25
0.35
0.45
0.45
0.45
0.65
1.05
1.85
2.55
2.85
3.45
4.35
5.35
-
-
-
-
-
-
-
0.95
1.35
1.95
2.15
2.35
3.10
3.80
0.65
0.85
1.35
1.45
1.75
1.95
1.15
0.65
0.75
1.05
1.15
1.15
1.35
1.45
-
-
-
-
-
-
-
0.15
0.15
0.15
0.15
0.15
0.15
0.15
0.4
0.8
1.0
1.2
1.5
1.7
2.1
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.15
0.3
0.4
0.6
0.8
0.9
1.1
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.4
2.0
2.2
2.4
3.15
3.85
0.7
0.9
1.4
1.5
1.8
2.0
2.26
0.7
0.9
1.4
1.5
1.8
2.0
2.6
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.4
0.8
1.0
1.2
1.5
1.7
2.1
0.15
0.3
0.4
0.6
0.8
0.9
1.1
0.15
0.3
0.4
0.6
0.8
0.9
1.1
1.0
1.8
2.5
2.8
3.4
4.3
5.3
-
-
-
-
-
-
-
1.0
1.4
2.0
2.2
2.4
3.15
3.85
0.7
0.9
1.4
1.5
1.8
2.0
2.26
0.7
0.9
1.4
1.5
1.8
2.0
2.6
-
-
-
-
-
-
-
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Unit
V
V
V
V
V
V
3
Page 4
IN74LV14
DC ELECTRICAL CHARACTERISTICS
V
Symbol Parameter
V
OL
Low-Level
Output Voltage
I
IL
Low-Level
Input Leakage
Current
I
IH
High-Level
Input Leakage
Current
I
CC
Quiescent
Supply Current
(per Package)
I
CC1
Additional
Quiescent
Supply Current
on input
Test
Conditions
VI = V
IH
or I
= 6.0
O
mA
V
= V
I
IH
or V
IL
IO = 12.0
mA
VI=0 V 5.5 - -0.1 - -1.0 - -1.0
VI= V
СС
VI=0 В or
V
СС
IO = 0 µA
V
= V
I
СС
0.6V
I
= 0 µA
O
CC
V
3.0 - 0.33 - 0.40 - 0.50
–
4.5 - 0.40 - 0.55 - 0.65
–
5.5 - 0.1 - 1.0 - 1.0
5.5 - 4.0 - 20 - 40
-
2.7
3.6
(continuation)
Guaranteed Limit
25°C-40
°C ÷
85°C-40
°C ÷
125°C
min max min max min max
- 0.2 - 0.5 - 0.85 mA
Unit
V
µ
A
µ
A
.
4
Page 5
IN74LV14
AC ELECTRICAL CHARACTERISTICS
V
Symbol Parameter
t
PLH
, t
PHL
Propagation
Delay, Input A
to Output Y
(Figure 1 )
C
I
Input
Capacitance
C
PD
Input А
Test
Conditions
V
=0 V or
I
V
1
tLH = t
HL
=2.5 ns
С
= 50 pF
L
R
= 1 kΩ
L
VI=0 V or
V
СС
t
HL
V
0.1
t
CC
V
1.2
2.0
2.7
3.0
4.5
5.5
5.5
0.9
X
PHL
(CL=50 pF, tLH =tHL = 2.5 ns, RL=1 kΩ)
Guaranteed Limit
25°C-40
°C ÷
85°C-40
°C ÷
125°C
min max min max min max
-
150
-
-
-
-
28
22
17
14
-
170
-
-
-
-
37
28
22
18
-
200
-
-
-
-
48
35
28
23
-7.0-7.0-7.0
-30-30-30
t
LH
V
0.9
V
X
0.1
t
PLH
1
GND
Unit
ns
pF
pF
Output Y
PULSE
GENERATOR
V
OH
V
Y
VX=0.5 V
CC
V
Y
V
OL
Figure 1. Switching Waveforms
V
CC
V
I
DEVICE
UNDER
R
TEST
T
V
O
C
L
Termination resistance RT – should
be equal to Z
R
L
of pulse generators
OUT
Figure 2. Test Circuit
5
Page 6
CHIP PAD DIAGRAM IZ74LV14
1.33 0.03
±
IN74LV14
13
12
14
±
1.42 0.03
01
02
03
Chip marking
IN74LV14
(x=0.130; y=0.130
Pad size 0.108 x 0.108 mm (Pad size is given as per
Thickness of chip 0.46 ± 0,02 mm
11
10
04
)
metallization
09
08
07
05 06
layer)
PAD LOCATION
Pad No Symbol X Y
01 A1 0.130 0.463
02 Y1 0.130 0.230
03 A2 0.381 0.126
04 Y2 0.616 0.126
05 A3 0.881 0.126
06 Y3 1.116 0.126
07 GND 1.115 0.631
08 Y4 1.115 0.846
09 A4 1.115 1.181
10 Y5 0.804 1.194
11 A5 0.569 1.194
12 Y6 0.378 1.194
13 A6 0.143 1.194
14 V
CC
0.130 0.813
6
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