Datasheet ISO103B, ISO103 Datasheet (Burr Brown)

Duty Cycle

Modulator

Duty Cycle

Demodulator

Rectifiers

Filters

Oscillator

Driver

Sense

V

OUT

Com 2
–V

CC2

Sync*

Enable

+V

CC2

Gnd 2

+V

CC1

–V

CC1

Gnd 1

Com 1

V

IN

Ps Gnd

–V

C

+V

C

Sync

*Ground if not used

®

ISO103

Low-Cost, Internally Powered

ISOLATION AMPLIFIER

ISO103

FEA TURES

● SIGNAL AND POWER IN ONE

DOUBLE-WIDE (0.6") SIDE-BRAZED
PACKAGE

● 5600Vpk TEST VOLTAGE

● 1500Vrms CONTINUOUS AC BARRIER

RATING

APPLICATIONS

● MULTICHANNEL ISOLATED DATA

ACQUISITION

● ISOLATED 4-20mA LOOP RECEIVER AND

POWER

● POWER SUPPLY AND MOTOR CONTROL

● GROUND LOOP ELIMINATION

● WIDE INPUT SIGNAL RANGE:

–10V to +10V

● WIDE BANDWIDTH:

20kHz Small Signal, 20kHz Full Power

● BUILT-IN ISOLATED POWER:

±10V to ±18V Input, ±50mA Output

● MULTICHANNEL SYNCHRONIZATION

CAPABILITY (TTL)

● BOARD AREA ONLY 0.72in.2 (4.6cm2)

DESCRIPTION

The ISO103 isolation amplifier provides both signal
and power across an isolation barrier. The ceramic
non-hermetic hybrid package with side-brazed pins
contains a transformer-coupled DC/DC converter and
a capacitor-coupled signal channel.

Extra power is available on the isolated input side for
external input conditioning circuitry. The converter is
protected from shorts to ground with an internal cur­rent limit, and the soft-start feature limits the initial
currents from the power source. Multiple-channel syn­chronization can be accomplished by applying a TTL
clock signal to paralleled Sync pins. The Enable con-

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©

1989 Burr-Brown Corporation PDS-1004E Printed in U.S.A. August, 1999

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trol is used to turn off transformer drive while keeping
the signal channel demodulator active. This feature
provides a convenient way to reduce quiescent current
for low power applications.

The wide barrier pin spacing and internal insulation
allow for the generous 1500Vrms continuous rating.
Reliability is assured by 100% barrier breakdown
testing that conforms to UL1244 test methods. Low
barrier capacitance minimizes AC leakage currents.

These specifications and built-in features make the
ISO103 easy to use, as well as providing for compact
PC board layouts.

SPECIFICATIONS

ELECTRICAL

At TA = +25°C and V

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
ISOLATION

Rated Continuous Voltage

AC, 60Hz T

DC T
Test Breakdown, 100% AC, 60Hz 10s 5657 ✻ Vpk
Isolation-Mode Rejection 1500Vrms, 60Hz 130 ✻ dB

Barrier Impedance 10
Leakage Current 240Vrms, 60Hz 1 2 ✻✻µA

GAIN

Nominal 1 ✻ V/V
Initial Error ±0.12 ±0.3 ±0.08 ±0.15 % FSR
Gain vs Temperature ±60 ±100 ±20 ±50 ppm/°C
Nonlinearity V

INPUT OFFSET VOLTAGE

Initial Offset ±20 ±60 ✻✻mV

vs Temperature ±300 ±500 ✻✻µV/°C

vs Power Supplies V

vs Output Supply Load I

SIGNAL INPUT

Voltage Range Output Voltage in Range ±10 ±15 ✻✻ V
Resistance 200 ✻ kΩ

SIGNAL OUTPUT

Voltage Range ±10 ±12.5 ✻✻ V
Current Drive ±5 ±15 ✻✻ mA
Ripple Voltage, 800kHz Carrier 25 ✻ mVp-p

Capacitive Load Drive 1000 ✻ pF
Voltage Noise 4 ✻ µV/√Hz

FREQUENCY RESPONSE

Small Signal Bandwidth 20 ✻ kHz
Slew Rate 1.5 ✻ V/µs
Settling Time 0.1%, –10/10V 75 ✻ µs

POWER SUPPLIES

Rated Voltage, V
Voltage Range ±10 ±18 ✻✻V
Input Current I

Ripple Current No Filter 60 ✻ mAp-p

Rated Output Voltage Load = 15mA ±14.25 ±15 ±15.75 ✻✻✻V
Output 50mA Balanced Load 10 ✻✻V

Load Regulation Balanced Load 0.3 ✻ %/mA
Line Regulation 1.12 ✻ V/V
Output Voltage vs Temperature 2.5 ✻ mV/°C
Voltage Balance Error, ±V
Voltage Ripple (800kHz) No External Capacitors 50 ✻ mVp-p

Output Capacitive Load 1 ✻ µF
Sync Frequency Sync-Pin Grounded

TEMPERATURE RANGE

Specification –25 +85 ✻✻°C
Operating –25 +85 ✻✻°C
Storage –25 +125 ✻✻°C

✻ Specifications same as ISO103.
NOTE: (1) Conforms to UL1244 test methods. 100% tested at 1500Vrms for 1 minute. (2) If using external synchronization with a TTL-level clock, frequency should
be between 1.2MHz and 2MHz with a duty-cycle greater than 25%.

= ±15V, ±15mA output current unless otherwise noted.

CC2

(1)

to T

MIN

MAX

to T

MIN

MAX

2121VDC 160 ✻ dB

= –10V to 10V ±0.026 ±0.075 ±0.018 ±0.050 % FSR

O

V

= –5V to 5V ±0.009 ✻ ±0.025 %FSR

O

= ±10V to ±18V 0.9 ✻ mV/V

CC2

= 0 to ±50mA ±0.3 ✻ mV/mA

O

400Ω/4.7nF (See Figure 4) 5 ✻ mVp-p

CC2

= ±15mA +90/–4.5 ✻ mA

O

I

= 0mA +60/–4.5 ✻ mA

O

C

= 1µF3 ✻ mAp-p

IN

100mA Single-Ended Loads 10 ✻✻V

CC1

C

= 1µF5 ✻ mVp-p

EXT

ISO103 ISO103B

1500 ✻ Vrms
2121 ✻ VDC

12

|| 9 ✻ Ω || pF

±15 ✻ V

0.05 ✻ %

(2)

1.6 ✻ MHz

®

ISO103

2

ABSOLUTE MAXIMUM RATINGS

Supply Without Damage .................................................................... ±18V

V

, Sense Voltage............................................................................. ±50V

IN

Com 1 to Gnd 1 or Com 2 to Gnd 2 ..............................................±200mV

Enable, Sync........................................................................... 0V to +V

Continuous Isolation Voltage ..................................................... 1500Vrms

V

, dv/dt ..................................................................................... 20kV/µs

ISO

Junction Temperature ...................................................................... 150°C

Storage Temperature...................................................... –25°C to +125°C

Lead Temperature,10s .................................................................... 300°C

Output Short to Gnd 2 Duration ............................................... Continuous

±V

to Gnd 1 Duration .......................................................... Continuous

CC1

CC2

ELECTROSTATIC
DISCHARGE SENSITIVITY

Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.

PIN CONFIGURATION

1

+V

C

+V

2

CC1

3

–V

CC1

–V

4

CC1

Com 2

9

V

10

OUT

Sense

11
12

Gnd 2

*Operation requires this pin be grounded or driven with TTL levels.

24

Ps Gnd
23 Gnd 1

22 V

IN

21 Com 1

16

–V

CC2

15

Sync*

+V

14

CC2

Enable

13

PACKAGE/ORDERING INFORMATION

PACKAGE SPECIFIED
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE NUMBER

ISO103 24-Pin DIP 231 –25°C to +85°C

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/ ) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “ISO103/2K5” will get a single 2500­piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

(1)

RANGE MARKING NUMBER

(2)

MEDIA

®

3

ISO103

TYPICAL PERFORMANCE CURVES

At TA = +25°C, V

= ±15VDC, ±15mA output current, unless otherwise noted.

CC2

RECOMMENDED RANGE OF ISOLATION VOLTAGE

10k

2.1k
1k

100

10

Maximum Isolation Voltage (Vpk)

1

100 1k 10k 100k 1M 10M

10

3

1

0.3

THD+N (%)

0.1

0.03

Barrier Voltage Rating

2100V

at 75kHz

Operational

Region

Isolation Voltage Frequency (Hz)

DISTORTION vs FREQUENCY

V = 2Vp-p

O

V = 20Vp-p

O

Non-Specified

Signal

Operation

140

130

120

110

100

Isolation-Mode Rejection (dB)

90

10 100 1k 10k 100k

3

0

–3

–6

Gain (dB)

–9

–12

IMR/LEAKAGE vs FREQUENCY

IMR

Isolation Voltage Frequency (Hz)

GAIN/PHASE vs FREQUENCY

Leakage at

1500Vrms

PHASE

Leakage at

240Vrms

GAIN

10m

1m

100µ

10µ

1µ

Barrier Leakage Current (Arms)

100n

0

45

90

Phase Shift (°)

135

180

0.01
20 100 1k 10k

Frequency (Hz)

LARGE SIGNAL TRANSIENT RESPONSE

20

10

0

Output Voltage (V)

–10

–20

0 50 100

Time (µs)

20k

–15

Small Signal Frequency (Hz)

ISOLATED POWER SUPPLY

17

16

15

CC1

14

±V Output Voltage (V)

13

0
0

LOAD REGULATION AND EFFICIENCY

Balanced Load Efficiency

Output Voltage
Single-Ended Loads

10
20

±V Supply Output Current (mA)

CC1

1k100 10k 100k

Output Voltage
Balanced Loads

20
40

30
60

40
80

60

45

30

Efficiency (%)

15

0

®

ISO103

4

TYPICAL PERFORMANCE CURVES (CONT)

ISOLATION POWER SUPPLY VOLTAGE

vs TEMPERATURE

–25 0 25 50 75 100

Temperature (°C)

2

1

0

–1

–2

V (%)∆

CC2

At TA = +25°C, V

19
18

17
16
15
14

CC1

13

+V (V)

12
11
10

9

= ±15VDC, ±15mA output current, unless otherwise noted.

CC2

ISOLATED POWER SUPPLY LINE REGULATION

±15mA Load

1.12V/V

9 10111213141516171819

+V (V)

CC2

ISOLATED SUPPLY VOLTAGE AND V

vs SYNC FREQUENCY

5

V

CC1

2.5

V

0

OS

∆ V (mV)

–2.5

–5

1 1.5 2 2.5

Sync Frequency (MHz)

OS

250

125

OS

0

CC1

∆ V (mV)

–125

–250

®

5

ISO103

THEORY OF OPERATION

The block diagram on the front page shows the isolation
amplifier’s synchronized signal and power configuration,
which eliminate beat frequency interference. A proprietary
800kHz oscillator chip, power MOSFET transformer driv­ers, patented square core wirebonded transformer, and single
chip diode bridge provide power to the input side of the
isolation amplifier as well as external loads. The signal
channel capacitively couples a duty-cycle encoded signal
across the ceramic high-voltage barrier built into the pack­age. A proprietary transmitter-receiver pair of integrated
circuits, laser trimmed at wafer level, and coupled through a
pair of matched “fringe” capacitors, result in a simple,
reliable design.

SIGNAL AND POWER CONNECTIONS

Figure 1 shows the proper power supply and signal connec­tions. All power supply pins should be bypassed as shown
with the π filter for +V
than ±15mA are drawn from the isolated supply. Separate
rectifier output pins (±V
(±VC) allow additional ripple filtering and/or regulation. The
separate input and output common pins and output sense are
low current inputs tied to the signal source ground, output
ground, and output load, respectively, to minimize errors
due to IR drop in long conductors. Otherwise, connect Com
1 to Gnd 1, Com 2 to Gnd 2, and Sense to V
ISO103 socket. The enable pin may be left open if the
ISO103 is continuously operated. If not, a TTL low level
will disable the internal DC/DC converter. The Sync input
must be grounded for unsynchronized operation while a

1.2MHz to 2MHz TTL clock signal provides synchroniza­tion of multiple units.

, an option recommended if more

CC2

) and amplifier supply input pins

CC1

OUT

at the

The ISO103 isolation amplifier contains a transformer­coupled DC/DC converter that is powered from the output
side of the isolation amplifier. All power supply pins (1, 2,
3, 4, 14, and 16) of the ISO103 have an internal 0.1µF
capacitor to ground. L1 is used to slow down fast changes in
the input current to the DC/DC converter. C1 is used to help
regulate the voltage ripple caused by the current demands of
the converter. L1, C1, and C2 are optional, however, recom­mended for low noise applications.

The DC/DC converter creates an unregulated ±15V output
to ±V

. If the ISO103 is the only device using the DC/DC

CC1

converter for power, pins 1 and 2 and pins 3 and 4 can be
connected directly without CO or LO in the circuit. If an
external capacitor is used in this configuration, it should not
exceed 1µF. This configuration is possible because the
isolation amplifier and the DC/DC converter are synchro­nized internally.

If additional devices are powered by the DC/DC converter
of the ISO103, the application may require that the ripple
voltage of the ISO103 converter be attenuated. In which
case, LO and CO should be added to the circuit. The inductor
is used to attenuate the ripple current and a higher value
capacitor can be used to reduce the ripple voltage even
further.

OPTIONAL GAIN AND OFFSET ADJUSTMENTS

Rated gain accuracy and offset performance can be achieved
with no external adjustments, but the circuit of Figure 2a
may be used to provide a gain trim of ±0.5% for the values
shown; greater range may be provided by increasing the size
of R1 and R2. Every 2kΩ increase in R1 will give an
additional 1% adjustment range, with R2 ≥ 2R1. If safety or
convenience dictate location of the adjustment potentiome­ter on the other side of the barrier from the position shown
in Figure 2a, the position of R1 and R2 may be reversed.

V

IN

Com

24 23 22 21 16 15 14 13

PS

*Optional Filtering:
For L

O

0 ≤ LO < 10µH
C

< 1µF

O

For L

O

LO ≥ 10µH, < 10Ω
C

≤ 10µF

O

+

Supply

Outputs

–

Gnd 1 Com 1V

Gnd

+V

+V

CC1

C

123491011 12

C

O

L *

O

ISO103

–V

IN

CC1

FIGURE 1. Signal and Power Connections.

®

ISO103

L *

Isolation

Barrier

1µF

C

(3)

L

C

1µF

2

+V

Sync Enable

–V

CC2

(2) (1)

–V

Com 2

C

C

O

O

V

OUT

Sense Gnd 2

I

CC2

1

+

10µF
Tantalum

Sense

Com 2

Com Return

V

OUT

–V

CC2

+V

CC2

NOTES: (1) Enable = pin open
or TTL high. (2) Ground sync
if not used. (3) π filter reduces
ripple current; L

R

L

= 10µH, <10Ω.

1

6

Gains greater than 1 may be obtained by using the circuit of
Figure 2b. Note that the effect of input referred errors will be
multiplied at the output in proportion to the increase in gain.
Also, the small-signal bandwidth will be decreased in in­verse proportion to the increase in gain. In most instances, a
precision gain block at the input of the isolation amplifier
will provide better overall performance.

2kΩ

1kΩ

22

R

1

V

IN

21

11

R

2

V

OUT

10

9

FIGURE 2a. Gain Adjust.

22

V

IN

21

Gain = 1 +

Sense

11

10

9

R

R

1

1

+

( )

R2200k

V

OUT

R

1

R

2

FIGURE 2b. Gain Setting.

Figure 3 shows a method for trimming VOS of the ISO103.
This circuit may be applied to either Signal Com (input or
output) as desired for safety or convenience. With the values
shown, ±15V supplies and unity gain, the circuit will pro­vide ±150mV adjustment range and 0.25mV resolution with
a typical trim potentiometer. The output will have some
sensitivity to power supply variations. For a ±100mV trim,
power supply sensitivity is 8mV/V at the output.

+V

or +V

CC1

CC2

Signal Com 1

or

Signal Com 2

100kΩ

–V

CC1

or –V

1MΩ

10kΩ

CC2

FIGURE 3. VOS Adjust.

Sense

22

V

IN

21

11

V

400Ω

10

9

OUT

4.7nF

FIGURE 4. Ripple Reduction.

MULTICHANNEL SYNCHRONIZATION

Synchronization of multiple ISO103s can be accomplished
by connecting pin 15 of each device to an external TTL level
oscillator, as shown in Figure 7. The PWS750-1 oscillator is
convenient because its nominal synchronizing output fre­quency is 1.6MHz, resulting in a 800kHz carrier in the
ISO103 (its nominal unsynchronized value). The open col­lector output typically switches 7.5mA to a 0.2V low level
so that the external pull-up resistor can be chosen for
different pull-up voltages as shown in Figure 7. The number
of channels synchronized by one PWS750-1 is determined
by the total capacitance of the sync voltage conductors. They
must be less than 1000pF to ensure TTL level switching at
800kHz. At higher frequencies the capacitance must be
proportionally lower.

Customers can supply their own TTL level synchronization
logic provided the frequency is between 1.2MHz and 2MHz,
and the duty cycle is greater than 25%.

Multichannel synchronization with reduced power dissipa­tion for applications requiring less than ±15mA from V

CC1

is accomplished by driving both the Sync input pin (15) and
Enable pin (13) with the TTL oscillator as shown in Figure 5.

ISOLATION BARRIER VOLTAGE

The typical performance of the ISO103 under conditions of
barrier voltage stress is indicated in the first two perform­ance curves—Recommended Range of Isolation Voltage
and IMR/ Leakage vs Frequency. At low barrier modulation
levels, errors can be determined by the IMRR characteristic.
At higher barrier voltages, typical performance is obtained
as long as the dv/dt across the barrier is below the shaded
area in the first curve. Otherwise, the signal channel will be
interrupted, causing the output to distort, and/or shift DC
level. This condition is temporary, with normal operation
resuming as soon as the transient subsides. Permanent dam­age to the integrated circuits occurs only if transients exceed
20kV/µs. Even in this extreme case, the barrier integrity is
assured.

OPTIONAL OUTPUT FILTER

Figure 4 shows an optional output ripple filter that reduces
the 800kHz ripple voltage to <5mVp-p without compromis­ing DC performance. The small signal bandwidth is ex­tended above 30kHz as a result of this compensation.

HIGH VOLTAGE TESTING

The ISO103 was designed to reliably operate with 1500Vrms
continuous isolation barrier voltage. To confirm barrier
integrity, a two-step breakdown test is performed on 100%
of the units. First, a 5600V peak, 60Hz barrier potential is

7

ISO103

®

applied for 10s to verify that the dielectric strength of the
insulation is above this level. Following this exposure, a
1500Vrms, 60Hz potential is applied for one minute to
conform to UL1244. Life-test results show reliable opera­tion under continuous rated voltage and maximum operat­ing temperature conditions.

ISO103

+V

CC2

I (Reduced)

Q

131415

TTL Osc.

1mA

PT100
RTD

1mA

119.4Ω

98.5Ω

2.5kΩ

11

3

–

5
6

+

4

0.01µF

20mA

i (mA) = 0.4221R – 46.4

OT

10

8

12

XTR101

7

i

O

9

0.01µF

+

1/2 W

750Ω

2N2222A
TO-18

External
Load
<15mA

+

–

1234

12

FIGURE 5. Reduced Power Dissipation.

+

1µF

16

10

11

3

12

420

1µF

5V

15

14

5

–

V

O

RCV

2

4

12

22
24
23
21

34

14

ISO 103

16 15

1µF

1µF

10
11
12

9

+15V

V

OUT

–15V

4

50 150°C

FIGURE 6. Isolated 4-20mA Instrument Loop.

T

0

50 150°C

T

®

ISO103

8

V

IN1

24 23 22 21

–V

CC2+VCC2

16 15 14

Sync 1.6MHz

Channel 1

ISO 103

1234

+
–

V

IN2

24 23 22 21

Channel 2

ISO 103

1234

+
–

Additional Channels

FIGURE 7. Synchronized-Multichannel Isolation.

9101112

16 15 14

9101112

12

37

R

V

OUT1

V

OUT2

1114

PWS750-1

V

R =

7.5

NOTES:
(1) PWS750-1 can
sync > 20 ISO103.
(2) Bypass supplies
as shown in Figure 1.

CC2

k

Ω

®

9

ISO103