Datasheet IRF7807VD2 Datasheet (International Rectifier)

PD-94079

IRF7807VD2

FETKY™ MOSFET / SCHOTTKY DIODE

• Co-Pack N-channel HEXFET

and Schottky Diode

• Ideal for Synchronous Rectifiers in DC-DC
Converters Up to 5A Output

• Low Conduction Losses

• Low Switching Losses



Power MOSFET

A/S
A/S

A/S

1

2

3

4

G

8

K/D

7

K/D

6

K/D

5

K/D

• Low Vf Schottky Rectifier

Description

SO-8

Top View

The FETKY™ family of Co-Pa ck HEXFETMOSFETs and
Schottky diodes offers the designer an innovative, board

space saving solution for switching regulator and power
management applications. HEXFET power MOSFETs
utilize advanced processing techniques to achieve

DEVICE CHARACTERISTICSU

extremely low on-resistance per silicon area. Combining
this technology with International Rectifier’s low forward
drop Schottky rectifiers results in an extremely efficient
device suitable for use in a wide variety of portable
electronics applications.

The SO-8 has been modified through a customized
leadframe for enhanced thermal characteristics. The SO-

IRF7807VD2

R

(on)

DS

Q

G

Q

sw

Q

oss

17mΩ

9.5nC

3.4nC
12nC

8 package is designed for v apor phase, infrared or w a ve
soldering techniques.

Absolute Maximum Ratings

Parameter Symbol Max. Units

Drain-Source Voltage V
Gate-Source Voltage V
Continuous Drain or Source 25°CI
Current (V

≥ 4.5V) 70°C6.6A

GS

Pulsed Drain CurrentQ I

Power DissipationS 25°CP

DS

GS

D

DM

D

70°C1.6

30

±20

8.3

66

2.5

V

W

Schottky and Body Diode 25°C IF (AV) 3.7 A
Average ForwardCurrentT 70°C2.3
Junction & Storage Temperature Range T

J, TSTG

–55 to 150 °C

Thermal Resistance

Parameter Max. Units

Maximum Junction-to-AmbientS R
Maximum Junction-to-Lead R

θJA

θJL

50 °C/W
20 °C/W

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03/05/01

IRF7807VD2

Electrical Characteristics

Parameter Min Typ Max Units Conditions

Drain-to-Source BV
Breakdown Voltage

Static Drain-Source R
on Resistance

Gate Threshold Voltage V
Drain-Source Leakage I

Current

Current* 6.0 mA V

Gate-Source Leakage I
Current*

DSS

GSS

Total Gate Charge* Q
Pre-Vth Q

Gate-Source Charge VDS = 16V
Post-Vth Q

Gate-Source Charge
Gate to Drain Charge Q
Switch Chg(Q

+ Qgd) Q

gs2

Output Charge* Q
Gate Resistance R
Turn-on Delay Time t

Rise Time t

d (on)

r

Turn-off Delay Time td
Fall Time t

f

30 –– VVGS = 0V, ID = 250µA

DSS

DS

GS(th)

(on)

17 25 mΩ VGS = 4.5V, ID = 7.0AR

1.0 V VDS = VGS,ID = 250µA
50 µA VDS = 24V, VGS = 0

DS

Tj = 100°C

±100 nA VGS = ±20V

G

GS1

GS2

GD

sw

oss

G

9.5 14 VGS=4.5V, ID=7.0A

2.3

1.0 nC

2.4

3.4 5.2
12 16.8 VDS = 16V, VGS = 0

2.0 Ω

6.3 VDD = 16V, ID = 7.0A

1.2 ns VGS = 5V, RG= 2Ω

(off)

11 Resistive Load

2.2

= 24V, VGS = 0,

Schottky Diode & Body Diode Ratings and Characteristics

Parameter Min Typ Max Units Conditions

Diode Forward Voltage V

SD

0.54 V Tj = 25°C, Is = 3.0A, V

0.43 Tj = 125°C, Is = 3.0A, V

GS

GS

=0VR

Reverse Recovery Time trr 36 ns Tj = 25°C, Is = 7.0A, VDS = 16V
Reverse Recovery Charge Qrr 41 nC di/dt = 100A/µs

Forward Turn-On Time t

Notes:

Q Repetitive rating; pulse width limited by max. junction temperature.
R Pulse width ≤ 400 µs; duty cycle ≤ 2%.
S When mounted on 1 inch square copper board
T 50% Duty Cycle, Rectangular
U

Typical values of R

measured at VGS = 5.0V , IF = 7.0A.
* Device are 100% tested to these parameters.

(on) measured at VGS = 4.5V, QG, QSW and Q

DS

Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

on

OSS

2 www.irf.com

=0VR

)

Power MOSFET Selection for DC/DC
Converters

Control FET

Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the R
MOSFET, but these conduction losses are only about
one half of the total losses.

ds(on)

of the

V

GTH

t1

IRF7807VD2

Drain Current

Gate V oltage

t2

t3

4

1

Power losses in the control switch Q1 are given
by;

P

= P

loss

This can be expanded and approximated by;

P

loss

conduction

I

=

()

rms




+I



+Q

()

g

Q



+



This simplified loss equation includes the terms Q
and Q

charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Q
Fig 1.

the gate driver between the time that the threshold
voltage has been reached (t1) and the time the drain
current rises to I
age begins to change. Minimizing Q
tor in reducing switching losses in Q1.

put capacitance of the MOSFET during every switch­ing cycle. Figure 2 shows how Q
parallel combination of the voltage dependant (non­linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.

which are new to P ower MOSFET data sheets.

oss

Q

is a sub element of traditional gate-source

gs2

Q

indicates the charge that must be supplied by

gs2

Q

is the charge that must be supplied to the out-

oss

+ P

2

R

×

ds(on)

Q

gd

×

×

oss

2

V

×

in

i

g

V

f

×

g

V

×

×

in

(t2) at which time the drain volt-

dmax

switching

f

×



f



and Q

gs1

+ P




+I×



+ P

drive






gs2

oss

output

Q

gs2

×

i

g

, can be seen from

is a critical fac-

gs2

is formed by the




V

f

×

in



gs2

t0

2

*

P

+

output



f

+

(



Drain V oltage

Q

V

×

rr

×

in

GS1QGS2QGD

Q

Figure 1: Typical MOSFET switching waveform

Synchronous FET

The power loss equation for Q2 is approximated

by;

P
P
+Q

*dissipated primarily in Q1.

P

=

loss

conduction

2

I

=

loss

rms

()

()

g



Q

oss



+

2



P

+

drive

R

×

ds(on)

V

×

f

×

g

V

×

×

in

f

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IRF7807VD2

For the synchronous MOSFET Q2, R

portant character istic; however, once again the im-

ds(on)

is an im-

portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con­trol IC so the gate drive losses become much more
significant. Secondly, the output charge Q
verse recovery charge Qrr both generate losses that

and re-

oss

are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be­tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca­pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn

Typical Mobile PC Application

The performance of these new devices has been tested
in circuit and correlates well with performance predic­tions generated by the system models. An advantage of
this new technology platform is that the MOSFETs it
produces are suitable for both control FET and synchro­nous FET applications. This has been demonstrated with
the 3.3V and 5V converters. (Fig 3 and Fig 4). In these
applications the same MOSFET IRF7807V was used for
both the control FET (Q1) and the synchronous FET
(Q2). This provides a highly effective cost/performance
solution.

the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Q
potential for Cdv/dt turn on.

must be minimized to reduce the

gs1

Spice model for IRF7807V can be downloaded in

machine readable format at www.irf.com.

Figure 2: Q

Characteristic

oss

3.3V Supply : Q1=Q2= IRF7807V

93
92
91
90
89
88
87

Efficiency (%)

86
85
84
83

12345

Vin=24V
Vin=14V
Vin=10V

Load current (A)

95
94
93
92
91
90

Efficiency (%)

89
88
87
86

12345

5.0V Supply : Q1=Q2= IRF7807V

Vin=24V
Vin=14V
Vin=10V

Load current (A)

Figure 3 Figure 4

4 www.irf.com

IRF7807VD2

2.0

1.5

1.0

7.0A

I =



D

(Normalized)

0.5

DS(on)

R , Drain-to-Source On Resistance

0.0

-60 -40 -20 0 20 40 60 80 100 120 140 160

T , Junction Temperature ( C)

J

Fig 5. Normalized On-Resistance

Vs. Temperature

70

VGS
TOP 4.5V

60

3.5V

3.0V

2.5V

50

2.0V
BOTTOM 0.0V

40

V =

4.5V



GS

°

)

0.030

Ω

0.025

0.020

ID = 7.0A

0.015

, Drain-to -Source On Resistance (

DS(on)

0.010

R

2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0

V

Gate -to -Source Voltage (V)

GS,

Fig 7. On-Resistance Vs. Gate Voltage

70

VGS
TOP 4.5V

60

3.5V

3.0V

2.5V

50

2.0V
BOTTOM 0.0V

40

30

20

, Source-to-Drain Current (A)

S

I

10

380µs PULSE WIDTH

0.0 V

Tj = 25°C

0

0 0.2 0.4 0.6 0.8 1

VSD, Source-to-Drain Voltage (V)

Fig 7. Typical Reverse Output Characteristics

30

20

, Source-to-Drain Current (A)

S

I

10

O.OV

380µS PULSE WIDTH
Tj = 150°C

0

0 0.2 0.4 0.6 0.8 1

VSD, Source-to-Drain Voltage (V)

Fig 8. Typical Reverse Output Characteristics

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IRF7807VD2

100

D = 0.50

thJA

Thermal Response (Z )

0.20

10

0.10

0.05
P

0.02

1

0.01

SINGLE PULSE



(THERMAL RESPONSE)

0.1

0.00001 0.0001 0.001 0.01 0.1 1 10

t , Rectangular Pulse Duration (sec)

1

Notes:

1. Duty factor D = t / t



2. Peak T =P x Z + T

J DM thJA A

DM



1 2

Figure 9. Maximum Eff ectiv e Transient Thermal Impedance, J unction-to-Ambient

t

1

t

2

5

I =

7.0A

D



V = 16V

DS

4

3

2

1

GS

V , Gate-to-Source Voltage (V)

0

0 2 4 6 8 10 12



Q , Total Gate Charge (nC)

G

Fig 10. Typical Gate Charge Vs.

Gate-to-Source Voltage

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IRF7807VD2

MOSFET , Body Diode & Schottky Diode Characteristics

100

Tj = 125°C
Tj = 25°C

( A )

10

F

1

Instantaneous Forward Current - I

100

Tj = 150°C

10

( mA )

R

1

0.1

Reverse Current - I

0.01

0.001
0 5 10 15 20 25 30

125°C

100°C

75°C

50°C

25°C

Reverse Voltage - VR (V)

Fig. 12 - Typical Values of

Reverse Current Vs. Reverse Voltage

0.1

0.0 0.2 0.4 0.6 0.8 1.0 1.2
Forward Voltage Drop - V

SD

( V )

Fig. 11 - Typical Forward Voltage Drop

Characteristics

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IRF7807VD2

(

)

)

)

)

)

SO-8 Package Details

D

5

- B -

8 7 6 5

5

E

- A ­1 2 3 4

e

6X

- C -

0.25 (.01 0) M C A S B S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1982.

2. CONTROLLING DIMENSION : INCH.

3. DIMENS ION S A R E S HO W N IN MIL L IME T ERS (INCHES).

4. OUT L IN E C ON F ORMS TO J E DEC OU TLIN E M S -0 1 2A A.
DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS

5
MO L D PR OTRU S IONS NO T TO EXC E E D 0 .2 5 (.00 6).
DIMEN SIONS IS T HE L ENG TH OF LEA D FOR SOL D ERING TO A S UBSTRAT E..

6

B 8X

e1

A1

0.25

A

H

.010) M A M

0.10 (.00 4

θ

θ

L
8X

K x 45°

6

C
8X

IN CHE S M ILL IME TE RS

DIM

MIN MAX MIN MA X
A .0532 .0688 1 .35 1.75
A1 .0040 .0098 0 .10 0.25
B .014 .018 0 .36 0.46
C .00 7 5 .0 0 9 8 0 .1 9 0 . 2 5
D .18 9 .1 9 6 4.8 0 4 . 9 8
E .150 .157 3 .81 3.99
e .0 5 0 B AS IC 1 .27 BA S IC
e1 .0 2 5 B AS IC 0 .63 5 BA SIC
H .22 8 4 .2 4 4 0 5 .8 0 6 . 2 0
K .011 .019 0 .28 0.48
L 0.16 .050 0.41 1.27

θ

0 ° 8 ° 0° 8 °

RECOMMENDED FOOTPRINT

0.72 (.02 8
8X

6.46 ( .25 5

1.27 ( .05 0
3X

1.78 (.07 0
8X

SO-8 Part Marking

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SO-8 Tape and Reel

TERMINAL NUMBER 1

IRF7807VD2

12.3 ( .484 )

11.7 ( .461 )

8.1 ( .318 )

7.9 ( .312 )

NOTES:
1 . C O N T R O LLIN G D IM E NSIO N : M IL L IM ETE R.
2 . A LL D IM E N SIO N S AR E SHO W N IN M IL L IM E TE RS (IN CH ES ) .

3. OUTLINE CONFORM S TO EIA-481 & EIA-541.

330.00
(12.992)
MAX.

NOTES :

1. CONTROLLING DIMENSION : MILLIMETER.

2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

This product has been designed and qualified for the commercial market.

Qualification Standards can be found on IR’s Web site.

FEED DIRECTION

14.40 ( .566 )

12.40 ( .488 )

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

Visit us at www.irf.com for sales contact information.

Data and specifications subject to change without notice. 03/01

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