l Ultra Low Gate Charge
l Reduced Gate Drive Requirement
l Enhanced 30V V
l Reduced C
l Extremely High Frequency Operation
l Repetitive Avalanche Rated
ISS
, C
Rating
GS
OSS
, C
RSS
Description
G
D
V
= 500V
DSS
R
DS(on)
= 0.85Ω
ID = 8.0A
S
This new series of low charge HEXFET® power MOSFETs
achieve significant lower gate charge over conventional
MOSFETs. Utilizing the new LCDMOS (low charge
device MOSFETs) technology, the device improvements
are achieved without added product cost, allowing for
reduce gate drive requirements and total system savings.
In addition, reduced switching losses and improved
efficiency and achievable in a variety of high frequency
applications. Frequencies of a few MHz at high current
are possible using the new low charge MOSFETs.
These device improvements combined with the proven
ruggedness and reliability that characterize of HEXFET
power MOSFETs offer the designer a new power
D2Pak
IRF840LCS
TO-262
IRF840LCL
transistor standard for switching applications.
Absolute Maximum Ratings
ParameterMax.Units
ID @ TC = 25°CContinuous Drain Current, VGS @ 10V8.0
ID @ TC = 100°CContinuous Drain Current, VGS @ 10V5.1A
I
Fall Time–––19–––RD = 30Ω, See Fig. 10
Internal Source Inductance
––––––
7.5
Between lead,
nH
and center of die contact
Input Capacitance––– 1100 –––VGS = 0V
Output Capacitance–––170 –––pFVDS = 25V
Reverse Transfer Capacitance–––18–––ƒ = 1.0MHz, See Fig. 5
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com5
Page 6
IRF840LCS/LCL
A
15V
DRIVER
+
-
R
20V
V
DS
G
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
V
G
Q
GD
V
DD
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V
GS
3mA
.3µF
D.U.T.
+
V
DS
-
Charge
Fig 13a. Basic Gate Charge Waveform
I
G
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
I
D
6www.irf.com
Page 7
IRF840LCS/LCL
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
-
R
G
Driver Gate Drive
P.W.
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
• dv/dt controlled by R
• Driver same type as D.U.T.
G
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Period
D =
P.W.
Period
+
+
V
DD
-
VGS=10V
*
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
* V
= 5V for Logic Level Devices
GS
Fig 14. For N-Channel HEXFET
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
®
Power MOSFETs
V
DD
I
SD
www.irf.com7
Page 8
IRF840LCS/LCL
A
D2Pak Package Outline
10.54 (.415)
1.40 (.055)
MAX.
1.78 (.070)
1.27 (.050)
1.40 (.055)
3X
1.14 (.045)
5.08 (.200)
NOTE S:
1 DIMENSIONS AFTER SOLDER DIP.
2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
3 CONTROLLING DIMENSION : INCH.
4 HEATSINK & LEAD DIMENSIONS DO NOT INCLUDE BURRS.
10.29 (.405)
- A 2
1 3
15.49 (.610)
14.73 (.580)
0.93 (.037)
3X
0.69 (.027)
0.2 5 ( .0 10) M B A M
4.69 (.185)
4.20 (.165)
D2Pak Part Marking Information
5.28 (.208)
4.78 (.188)
0.55 (.022)
0.46 (.018)
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
LEAD ASSIGNMENTS
1 - G ATE
2 - D RAIN
3 - S OU R CE
10.16 (.400)
REF.
6.47 (.255)
6.18 (.243)
2.61 (.103)
2.32 (.091)
8.89 (.350)
REF.
MINIMUM RECOMMENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082)
2X
2.54 (.100)
2X
INTERNATIONAL
RE CTIFIE R
LO G O
A S SEMBLY
LO T CO D E
F530S
9246
9 B 1 M
PART NUM B ER
DATE CODE
(YYW W )
YY = YEAR
WW = WEEK
8www.irf.com
Page 9
TO-262 Package Outline
IRF840LCS/LCL
TO-262 Part Marking Information
www.irf.com9
Page 10
IRF840LCS/LCL
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
1.60 (.063)
1.50 (.059)
0.368 (.0145)
0.342 (.0135)
FEED D IRECTION
1.85 (.073)
1.65 (.065)
TRL
10.90 (.429)
10.70 (.421)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
NOTES :
1. COM FO R M S TO E IA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIO N MEASUR ED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
11.60 (.457)
11.40 (.449)
1.75 (.069)
1.25 (.049)
16.10 (.634)
15.90 (.626)
15.42 (.609)
15.22 (.601)
27.40 (1.079)
23.90 (.941)
4
26.4 0 (1.039)
24.40 (.961 )
3
24.30 (.957)
23.90 (.941)
4.72 (.136)
4.52 (.178)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX .
4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 838 4630
IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
Data and specifications subject to change without notice. 1/2000
10www.irf.com
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