Page 1
AUTOMOTIVE MOSFET
PD - 94591
IRF1302
Benefits
● Advanced Process Technology
● Ultra Low On-Resistance
● Dynamic dv/dt Rating
● 175°C Operating Temperature
● Fast Switching
● Repetitive Avalanche Allowed up to Tjmax
G
HEXFET® Power MOSFET
D
V
= 20V
DSS
R
DS(on)
= 4.0mΩ
ID = 180A
S
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this design are a 175°C junction operating
temperature, fast switching speed and improved repetitive avalanche
rating. These benefits combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide variety
of other applications.
Absolute Maximum Ratings
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 180
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 130 A
I
DM
PD @TC = 25°C Power Dissipation 230 W
V
GS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt TBD V/ns
T
J
T
STG
®
Power MOSFET utilizes the lastest processing
TO-220AB
Parameter Max. Units
Pulsed Drain Current 700
Linear Derating Factor 1.5 W/°C
Gate-to-Source Voltage ± 20 V
Single Pulse Avalanche Energy 350 mJ
Avalanche Current See Fig.12a, 12b, 15, 16 A
Repetitive Avalanche Energy mJ
Operating Junction and -55 to + 175
Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
Thermal Resistance
Parameter Typ. Max. Units
R
θJC
R
θCS
R
θJA
Junction-to-Case ––– 0.65
Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
Junction-to-Ambient (PCB mount) ––– 62
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10/31/02
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IRF1302
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V
(BR)DSS
∆V
(BR)DSS
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
D
L
S
C
iss
C
oss
C
rss
C
oss
C
oss
C
eff. Effective Output Capacitance ––– 3540 ––– VGS = 0V, VDS = 0V to 16V
oss
Drain-to-Source Breakdown Voltage 20 ––– ––– V VGS = 0V, ID = 250µA
/∆T
Breakdown Voltage Temp. Coefficient ––– 0.021 ––– V/°C Reference to 25°C, ID = 1mA
J
Static Drain-to-Source On-Resistance ––– 3.3 4.0 mΩ VGS = 10V, ID = 104A
Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
Forward Transconductance 59 ––– ––– S VDS = 15V, ID = 104A
Drain-to-Source Leakage Current
––– ––– 20
––– ––– 250 VDS = 16V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200
VDS = 20V, VGS = 0V
µA
nA
VGS = -20V
Total Gate Charge ––– 79 120 ID = 104A
Gate-to-Source Charge ––– 18 27 nC VDS = 16V
Gate-to-Drain ("Miller") Charge ––– 31 46 VGS = 10V
Turn-On Delay Time ––– 28 ––– VDD = 11V
Rise Time ––– 130 ––– ID = 104A
Turn-Off Delay Time ––– 47 ––– RG = 4.5Ω
ns
Fall Time ––– 16 ––– VGS = 10V
4.5
Internal Drain Inductance
Internal Source Inductance ––– –––
––– –––
7.5
Between lead,
6mm (0.25in.)
nH
from package
and center of die contact
Input Capacitance ––– 3600 ––– VGS = 0V
Output Capacitance ––– 2370 ––– pF VDS = 25V
Reverse Transfer Capacitance ––– 520 ––– ƒ = 1.0MHz, See Fig. 5
Output Capacitance ––– 5710 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Output Capacitance ––– 2370 ––– VGS = 0V, VDS = 16V, ƒ = 1.0MHz
D
G
S
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Continuous Source Current MOSFET symbol
(Body Diode)
Pulsed Source Current integral reverse
(Body Diode)
––– –––
––– –––
180
700
showing the
A
p-n junction diode.
G
Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 104A, VGS = 0V
Reverse Recovery Time ––– 66 100 ns TJ = 25°C, IF = 104A
Reverse RecoveryCharge ––– 130 200 nC di/dt = 100A/µs
Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2 www.irf.com
D
S
Page 3
IRF1302
10000
)
A
(
t
1000
n
e
r
r
u
C
e
c
r
u
o
S
o
t
n
i
a
r
D
,
D
I
100
10
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
20µs PULSE WIDTH
Tj = 25°C
1
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
1000.00
10000
)
A
(
t
1000
n
e
r
r
u
C
e
c
r
u
o
S
o
t
n
i
a
r
D
,
D
I
100
10
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.5V
20µs PULSE WIDTH
Tj = 175°C
1
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
2.0
174A
I =
D
)
Α
(
t
n
e
r
r
u
C
e
c
r
100.00
u
o
S
o
t
n
i
a
r
D
,
D
I
10.00
4.0 5.0 6.0 7.0
TJ = 25°C
V
= 15V
DS
20µs PULSE WIDTH
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
TJ = 175°C
1.5
1.0
(Normalized)
0.5
DS(on)
R , Drain-to-Source On Resistance
0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T , Junction Temperature ( C)
J
Fig 4. Normalized On-Resistance
V =
GS
°
10V
Vs. Temperature
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IRF1302
100000
)
F
10000
p
(
e
c
n
a
t
i
c
a
p
a
C
,
1000
C
100
1 10 100
V
= 0V, f = 1 MHZ
GS
C
= C
iss
rss
oss
= C
= C
gs
gd
ds
C
C
Ciss
Coss
Crss
+ Cgd, C
+ C
gd
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
°
T = 175 C
J
100
10
°
T = 25 C
1
SD
I , Reverse Drain Current (A)
0.1
0.2 0.7 1.2 1.7 2.2
V ,Source- to-Dr ain Voltage (V)
SD
J
SHORTED
ds
V = 0 V
GS
12
D
I =
104A
10
7
5
2
GS
V , Gate-to-Source Voltage (V)
0
0 20 40 60 80 100
Q , Total Gate Charge (nC)
G
V = 16V
DS
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
10000
)
A
(
t
1000
n
e
r
r
u
C
e
c
r
100
u
o
S
o
t
n
i
a
r
10
D
,
Tc = 25°C
D
I
Tj = 175°C
Single Pulse
1
1 10 100
V
OPERATION IN THIS AREA
LIMITED BY RDS(on)
, Drain-toSource Voltage (V)
DS
100µsec
1msec
10msec
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4 www.irf.com
Page 5
IRF1302
+
-
200
LIMITED BY PACKAGE
150
100
D
I , Drain Current (A)
50
0
25 50 75 100 125 150 175
TC, Case Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Case Temperature
1
R
V
DS
V
GS
R
G
D
D.U.T.
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS
t
d(on)tr
t
d(off)tf
Fig 10b. Switching Time Waveforms
V
DD
D = 0.50
thJC
0.20
0.1
0.10
P
1 2
DM
t
1
t
2
0.05
SINGLE PULSE
Thermal Response (Z )
0.02
0.01
0.01
0.00001 0.0001 0.001 0.01 0.1 1
(THERMAL RESPONSE)
t , Rectangular Pulse Duration (sec)
1
Not es:
1. Duty factor D = t / t
2. Peak T = P x Z + T
J DM thJC C
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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Page 6
IRF1302
A
15V
DRIVER
+
-
V
R
G
20V
V
DS
t
L
D.U.T
I
AS
0.01
p
Ω
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
I
AS
Fig 12b. Unclamped Inductive Waveforms
Q
G
10 V
Q
GS
Q
GD
DD
700
TOP
560
420
280
140
AS
E , Single Pulse Avalanche Energy (mJ)
0
25 50 75 100 125 150 175
Starting Tj, Junction Temperature ( C)
BOTTOM
°
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
4.0
I
D
43A
74A
104A
)
V
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
V
GS
.3µF
D.U.T.
3mA
I
I
G
Current Sampling Resistors
+
V
DS
-
D
Fig 13b. Gate Charge Test Circuit
(
e
g
a
t
l
o
3.0
V
d
l
o
h
s
e
r
h
t
e
t
a
2.0
G
)
h
t
(
S
G
V
1.0
-75 -50 -25 0 25 50 75 100 125 150 175
ID = 250µA
TJ , Temperature ( °C )
Fig 14. Threshold Voltage Vs. Temperature
6 www.irf.com
Page 7
1000
IRF1302
Duty Cycle = Single Pulse
0.01
)
A
(
100
t
n
e
r
r
u
C
e
h
c
n
a
l
10
a
v
A
1
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
0.05
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
410
TOP Single Pulse
360
)
J
m
310
(
y
g
r
e
260
n
E
e
h
210
c
n
a
l
a
160
v
A
,
R
110
A
E
60
10
25 50 75 100 125 150
BOTTOM 10% Duty Cycle
ID = 104A
Starting TJ , Junction Temperature (°C)
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T
. This is validated for
jmax
every part type.
2. Safe operation in Avalanche is allowed as long asT
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. P
= Average power dissipation per single
D (ave)
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. I
= Allowable avalanche current.
av
7. ∆T = Allowable rise in junction temperature, not to exceed
T
(assumed as 25°C in Figure 15, 16).
jmax
t
Average time in avalanche.
av =
D = Duty cycle in avalanche = t
Z
(D, tav) = Transient thermal resistance, see figure 11)
thJC
av
·f
jmax
is
D (ave)·tav
∆∆
∆T/ Z
∆∆
thJC
Fig 16. Maximum Avalanche Energy
Vs. Temperature
P
= 1/2 ( 1.3·BV·Iav) =
D (ave)
I
av =
E
AS (AR)
∆∆
2
∆T/ [1.3·BV·Zth]
∆∆
= P
www.irf.com 7
Page 8
IRF1302
+
-
Peak Diode Recovery dv/dt Test Circuit
D.U.T*
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
+
-
-
+
R
G
V
GS
• dv/dt controlled by R
• ISD controlled by Duty Factor "D"
G
• D.U.T. - Device Under Test
V
DD
* Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D =
P. W .
Period
VGS=10V
[ ] ***
D.U.T. ISDWaveform
Reverse
Recovery
Current
Re-Applied
Voltage
D.U.T. VDSWaveform
Inductor Curent
*** V
= 5.0V for Logic Level and 3V Drive Devices
GS
Fig 17. For N-channel HEXFET
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
Ripple ≤ 5%
®
power MOSFETs
V
DD
[ ]
I
[ ]
SD
8 www.irf.com
Page 9
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
10.54 (.415)
10.29 (.405)
1 2 3
6.47 (.255)
6.10 (.240)
4
3.78 (.149)
3.54 (.139)
1.15 (.045)
MIN
4.06 ( .160)
3.55 ( .140)
- A -
4.69 (.185)
4.20 (.165)
- B -
1.32 ( .052)
1.22 ( .048)
LEAD ASSIGNMENTS
1 - GAT E
2 - DRA IN
3 - S OURCE
4 - DRA IN
IRF1302
0.93 ( .037)
3X
1.40 (.055)
3X
1.15 (.045)
2.54 (.100)
NOTES:
1 DIMEN SIONING & TOLERANC ING PER ANSI Y14.5M, 1982. 3 OUTLINE CONF ORMS TO JEDEC OU TLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
2X
0.69 ( .027)
0.36 (.01 4) M B A M
TO-220AB Part Marking Information
L
P
M
X
A
E
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting T
RG = 25Ω, I
I
SD
= 25°C, L = 0.063mH
J
= 104A. (See Figure 12).
AS
≤ 104A, di/dt ≤ 100A/µs, V
TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
TO-220 package is not recommended for Surface Mount Application.
This product has been designed and qualified for the Automotive [Q101] market.
A
E
S
I
T
H
S
I
F
1
R
0
1
I
0
N
:
1
O
D
L
A
I
7
O
C
8
E
T
9
L
D
B
E
M
E
S
S
E
M
S
T
N
A
S
H
E
1
1
9
O
9
W
N
B
9
,
L
7
W
C
"
"
E
N
L
Y
I
C
time as C
N
O
A
T
T
E
N
R
I
N
I
E
C
R
T
E
R
F
I
I
L
O
G
O
E
S
S
A
L
B
M
L
O
C
T
O
D
eff. is a fixed capacitance that gives the same charging
oss
while V
oss
Calculated continuous current based on maximum allowable
DD
≤ V
(BR)DSS
junction temperature. Package limitation current is 75A.
,
Limited by T
Jmax
avalanche performance.
This is applied to D
4 or G-10 Material ). For recommended footprint and soldering
techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
0.55 (.022)
3X
0.46 (.018)
2.92 (.115)
2.64 (.104)
R
E
B
M
N
T
U
R
P
L
A
Y
E
is rising from 0 to 80% V
DS
A
O
D
C
E
D
T
A
E
1
9
9
=
7
7
A
R
Y
E
1
9
W
K
E
E
L
N
I
C
E
.
DSS
, see Fig.12a, 12b, 15, 16 for typical repetitive
2
Pak, when mounted on 1" square PCB ( FR-
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/02
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