Datasheet IRF1018ESPBF, IRF1018EPBF Datasheet (International Rectifier)

2/28/08

Benefits

l Improved Gate, Avalanche and Dynamic

dv/dt Ruggedness

l Fully Characterized Capacitance and

Avalanche SOA

l Enhanced body diode dV/dt and dI/dt

Capability

www.irf.com 1

Applications

l High Efficiency Synchronous Rectification in

SMPS

l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits

HEXFET® Power MOSFET

S

D

G

PD - 97125

D2Pak

IRF1018ESPbF

TO-220AB

IRF1018EPbF

TO-262

IRF1018ESLPbF

S

D

G

S

D

G

S

D

G

D

D

D

GDS

Gate Drain Source

IRF1018EPbF

IRF1018ESPbF

IRF1018ESLPbF

V

DSS

60V

R

DS(on)

typ.

7.1m

:

max.

8.4m

:

I

D

79A

Absolute Maximum Ratings

Symbol Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V

I

D

@ TC = 100°C Continuous Drain Current, VGS @ 10V

A

I

DM

Pulsed Drain Current

c

P

D

@TC = 25°C

Maximum Power Dissipation

W

Linear Derating Factor

W/°C

V

GS

Gate-to-Source Voltage

V

dv/dt

Peak Diode Recovery

e

V/ns

T

J

Operating Junction and

°C

T

STG

Storage Temperature Range

Soldering Temperature, for 10 seconds

(1.6mm from case)

Mounting torque, 6-32 or M3 screw

k

Avalanche Characteristics

E

AS (Thermally limited)

Single Pulse Avalanche Energy

d

mJ

I

AR

Avalanche Current

c

A

E

AR

Repetitive Avalanche Energy

f

mJ

Thermal Resistance

Symbol Parameter Typ. Max. Units

R

θ

JC

Junction-to-Case

j –––

1.32

R

θ

CS

Case-to-Sink, Flat Greased Surface , TO-220

0.50 –––

R

θ

JA

Junction-to-Ambient, TO-220

j ––– 62

R

θ

JA

Junction-to-Ambient (PCB Mount) , D2Pak

ij

––– 40

11

110

21

-55 to + 175

± 20

0.76

10lbxin (1.1Nxm)

°C/W

300

Max.

79

56

315

88

47

IRF1018E/S/SLPbF

2 www.irf.com

Notes:

 Repetitive rating; pulse width limited by max. junction

temperature.

 Limited by T

Jmax

, starting TJ = 25°C, L = 0.08mH

RG = 25Ω, I

AS

= 47A, VGS =10V. Part not recommended for

use above this value.

 I

SD

≤ 47A, di/dt ≤ 1668A/μs, V

DD

≤ V

(BR)DSS

, TJ ≤ 175°C.

 Pulse width ≤ 400μs; duty cycle ≤ 2%.

S

D

G

 C

oss

eff. (TR) is a fixed capacitance that gives the same charging time

as C

oss

while V

DS

is rising from 0 to 80% V

DSS

.

 C

oss

eff. (ER) is a fixed capacitance that gives the same energy as

C

oss

while V

DS

is rising from 0 to 80% V

DSS

.

 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom

mended footprint and soldering techniques refer to application note #AN-994.

 R

θ

is measured at TJ approximately 90°C.

 This is only applied to TO-220

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

V

(BR)DSS

Drain-to-Source Breakdown Voltage 60 ––– ––– V

ΔV

(BR)DSS

/ΔT

J

Breakdown Voltage Temp. Coefficient ––– 0.073 ––– V/°C

R

DS(on)

Static Drain-to-Source On-Resistance ––– 7.1 8.4

mΩ

V

GS(th)

Gate Threshold Voltage 2.0 ––– 4.0 V

I

DSS

Drain-to-Source Leakage Current ––– ––– 20 μA

––– ––– 250

I

GSS

Gate-to-Source Forward Leakage ––– ––– 100 nA
Gate-to-Source Reverse Leakage ––– ––– -100

Dynamic @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units

gfs Forward Transconductance 110 ––– ––– S
Q

g

Total Gate Charge ––– 46 69 nC

Q

gs

Gate-to-Source Charge ––– 10 –––

Q

gd

Gate-to-Drain ("Miller") Charge ––– 12 –––

Q

sync

Total Gate Charge Sync. (Qg - Qgd)

––– 34 –––

R

G(int)

Internal Gate Resistance

–––

0.73 ––– Ω

t

d(on)

Turn-On Delay Time ––– 13 ––– ns

t

r

Rise Time ––– 35 –––

t

d(off)

Turn-Off Delay Time ––– 55 –––

t

f

Fall Time ––– 46 –––

C

iss

Input Capacitance ––– 2290 –––

C

oss

Output Capacitance ––– 270 –––

C

rss

Reverse Transfer Capacitance ––– 130 ––– pF

C

oss

eff. (ER)

Effective Output Capacitance (Energy Related)

h

––– 390 –––

C

oss

eff. (TR)

Effective Output Capacitance (Time Related)

g

––– 630 –––

Diode Characteristics

Symbol Parameter Min. Typ. Max. Units

I

S

Continuous Source Current ––– –––

79

A

(Body Diode)

I

SM

Pulsed Source Current ––– ––– 315

(Body Diode)

c

V

SD

Diode Forward Voltage ––– ––– 1.3 V

t

rr

Reverse Recovery Time ––– 26 39 ns

TJ = 25°C VR = 51V,

––– 31 47

T

J

= 125°C IF = 47A

Q

rr

Reverse Recovery Charge ––– 24 36 nC

TJ = 25°C

di/dt = 100A/μs

f

––– 35 53

T

J

= 125°C

I

RRM

Reverse Recovery Current ––– 1.8 ––– A

TJ = 25°C

t

on

Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Conditions

VDS = 50V, ID = 47A
I

D

= 47A

V

GS

= 20V

V

GS

= -20V

MOSFET symbol

showing the

V

DS

= 30V

Conditions

VGS = 10V

f

V

GS

= 0V

V

DS

= 50V
ƒ = 1.0MHz
V

GS

= 0V, VDS = 0V to 60V

h

V

GS

= 0V, VDS = 0V to 60V

g

T

J

= 25°C, IS = 47A, VGS = 0V

f

integral reverse

p-n junction diode.

Conditions

VGS = 0V, ID = 250μA
Reference to 25°C, I

D

= 5mA

c

V

GS

= 10V, ID = 47A

f

V

DS

= VGS, ID = 100μA
V

DS

= 60V, VGS = 0V
V

DS

= 48V, VGS = 0V, TJ = 125°C

I

D

= 47A

R

G

= 10Ω

V

GS

= 10V

f

VDD = 39V

I

D

= 47A, VDS =0V, VGS = 10V

IRF1018E/S/SLPbF

www.irf.com 3

Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance vs. Temperature

Fig 2. Typical Output Characteristics

Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I

D

,

D

r

a

i

n

-

t

o

-

S

o

u

r

c

e

C

u

r

r

e

n

t

(

A

)

VGS

TOP 15V

10V

8.0V

6.0V

5.5V

5.0V

4.8V

BOTTOM 4.5V

≤60μs PULSE WIDTH

Tj = 25°C

4.5V

0.1 1 10 100

VDS, Drain-to-Source Voltage (V)

1

10

100

1000

I

D

,

D

r

a

i

n

-

t

o

-

S

o

u

r

c

e

C

u

r

r

e

n

t

(

A

)

VGS

TOP 15V

10V

8.0V

6.0V

5.5V

5.0V

4.8V

BOTTOM 4.5V

≤60μs PULSE WIDTH

Tj = 175°C

4.5V

2 3 4 5 6 7 8 9

VGS, Gate-to-Source Voltage (V)

0.1

1

10

100

1000

I

D

,

D

r

a

i

n

-

t

o

-

S

o

u

r

c

e

C

u

r

r

e

n

t

(

A

)

TJ = 25°C

TJ = 175°C

V

DS

= 25V

≤

60μs PULSE WIDTH

-60 -40 -20 0 20 40 60 80 100120 140160180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

2.5

R

D

S

(

o

n

)

,

D

r

a

i

n

-

t

o

-

S

o

u

r

c

e

O

n

R

e

s

i

s

t

a

n

c

e

(

N

o

r

m

a

l

i

z

e

d

)

ID = 47A

V

GS

= 10V

1 10 100

VDS, Drain-to-Source Voltage (V)

0

1000

2000

3000

4000

C

,

C

a

p

a

c

i

t

a

n

c

e

(

p

F

)

V

GS

= 0V, f = 1 MHZ

C

iss

= C

gs

+ Cgd, C

ds

SHORTED

C

rss

= C

gd

C

oss

= C

ds

+ C

gd

C

oss

C

rss

C

iss

0 102030405060

Q

G

Total Gate Charge (nC)

0

4

8

12

16

V

G

S

,

G

a

t

e

-

t

o

-

S

o

u

r

c

e

V

o

l

t

a

g

e

(

V

)

VDS= 48V

VDS= 30V

VDS= 12V

ID= 47A

IRF1018E/S/SLPbF

4 www.irf.com

Fig 8. Maximum Safe Operating Area

Fig 10. Drain-to-Source Breakdown Voltage

Fig 7. Typical Source-Drain Diode Forward Voltage

Fig 11. Typical C

OSS

Stored Energy

Fig 9. Maximum Drain Current vs. Case Temperature

Fig 12. Maximum Avalanche Energy vs. DrainCurrent

0.0 0.5 1.0 1.5 2.0

VSD, Source-to-Drain Voltage (V)

0.1

1

10

100

1000

I

S

D

,

R

e

v

e

r

s

e

D

r

a

i

n

C

u

r

r

e

n

t

(

A

)

TJ = 25°C

TJ = 175°C

V

GS

= 0V

0.1 1 10 100

VDS, Drain-toSource Voltage (V)

0.1

1

10

100

1000

10000

I

D

,

D

r

a

i

n

-

t

o

-

S

o

u

r

c

e

C

u

r

r

e

n

t

(

A

)

Tc = 25°C
Tj = 175°C
Single Pulse

1msec

10msec

OPERATION IN THIS AREA
LIMITED BY RDS(on)

100μsec

DC

0 10 20 30 40 50 60

V

DS,

Drain-to-Source Voltage (V)

0.0

0.2

0.4

0.6

0.8

E

n

e

r

g

y

(

μ

J

)

25 50 75 100 125 150 175

TC , CaseTemperature (°C)

0

20

40

60

80

I

D

,

D

r

a

i

n

C

u

r

r

e

n

t

(

A

)

-60 -40 -20 0 20 40 60 80 100120140160180

TJ , Temperature ( °C )

60

65

70

75

80

V

(

B

R

)

D

S

S

,

D

r

a

i

n

-

t

o

-

S

o

u

r

c

e

B

r

e

a

k

d

o

w

n

V

o

l

t

a

g

e

(

V

)

Id = 5mA

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

0

50

100

150

200

250

300

350

400

E

A

S

,

S

i

n

g

l

e

P

u

l

s

e

A

v

a

l

a

n

c

h

e

E

n

e

r

g

y

(

m

J

)

I

D

TOP

5.3A

11A

BOTTOM

47A

IRF1018E/S/SLPbF

www.irf.com 5

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 14. Typical Avalanche Current vs.Pulsewidth

Fig 15. Maximum Avalanche Energy vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T

jmax

. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT

jmax

is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.

4. P

D (ave)

= Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).

6. I

av

= Allowable avalanche current.

7. ΔT = Allowable rise in junction temperature, not to exceed T

jmax

(assumed as
25°C in Figure 14, 15).
t

av =

Average time in avalanche.

D = Duty cycle in avalanche = t

av

·f

Z

thJC

(D, tav) = Transient thermal resistance, see Figures 13)

P

D (ave)

= 1/2 ( 1.3·BV·Iav) = DT/ Z

thJC

I

av =

2DT/ [1.3·BV·Zth]

E

AS (AR)

= P

D (ave)·tav

1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.001

0.01

0.1

1

10

T

h

e

r

m

a

l

R

e

s

p

o

n

s

e

(

Z

t

h

J

C

)

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE
( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Ri (°C/W)

τι

(

sec

)

0.026741 0.000007

0.28078 0.000091

0.606685 0.000843

0.406128 0.005884

τ

J

τ

J

τ

1

τ

1

τ

2

τ

2

τ

3

τ

3

R

1

R

1

R

2

R

2

R

3

R

3

Ci= τi/Ri

τ

τ

C

τ

4

τ

4

R

4

R

4

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

0.1

1

10

100

A

v

a

l

a

n

c

h

e

C

u

r

r

e

n

t

(

A

)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤj = 25°C and

Tstart = 150°C.

0.01

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and

Tstart =25°C (Single Pulse)

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

0

20

40

60

80

100

E

A

R

,

A

v

a

l

a

n

c

h

e

E

n

e

r

g

y

(

m

J

)

TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 47A

IRF1018E/S/SLPbF

6 www.irf.com

Fig. 17 - Typical Recovery Current vs. dif/dt

Fig 16. Threshold Voltage vs. Temperature

Fig. 19 - Typical Stored Charge vs. dif/dtFig. 18 - Typical Recovery Current vs. dif/dt

Fig. 20 - Typical Stored Charge vs. dif/dt

-75 -50 -25 0 25 50 75 100 125 150 175

TJ , Temperature ( °C )

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V

G

S

(

t

h

)

G

a

t

e

t

h

r

e

s

h

o

l

d

V

o

l

t

a

g

e

(

V

)

ID = 1.0A

ID = 1.0mA

ID = 250μA

ID = 100μA

0 200 400 600 800 1000

diF /dt (A/μs)

0

2

4

6

8

10

12

14

I

R

R

(

A

)

IF = 32A

VR = 51V

TJ = 25°C

TJ = 125°C

0 200 400 600 800 1000

diF /dt (A/μs)

0

2

4

6

8

10

12

14

I

R

R

(

A

)

IF = 47A

VR = 51V

TJ = 25°C

TJ = 125°C

0 200 400 600 800 1000

diF /dt (A/μs)

0

40

80

120

160

200

240

280

320

Q

R

R

(

A

)

IF = 47A

VR = 51V

TJ = 25°C

TJ = 125°C

0 200 400 600 800 1000

diF /dt (A/μs)

0

40

80

120

160

200

240

280

320

Q

R

R

(

A

)

IF = 32A

VR = 51V

TJ = 25°C

TJ = 125°C

IRF1018E/S/SLPbF

www.irf.com 7

Fig 23a. Switching Time Test Circuit

Fig 23b. Switching Time Waveforms

V

GS

V

DS

90%

10%

t

d(on)

t

d(off)

t

r

t

f

Fig 22b. Unclamped Inductive Waveforms

Fig 22a. Unclamped Inductive Test Circuit

t

p

V

(BR)DSS

I

AS

R

G

I

AS

0.01

Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

DRIVER

A

15V

20V

V

GS

Fig 24a. Gate Charge Test Circuit

Fig 24b. Gate Charge Waveform

V

DS

Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

R

D

V

GS

R

G

D.U.T.

10V

+

-

V

DD

Vds

Vgs

Id

Vgs(th)

Qgs1

Qgs2QgdQgodr

1K

VCC

DUT

0

L

20K

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance
Current Transformer

P.W.

Period

di/dt

Diode Recovery

dv/dt

Ripple ≤ 5%

Body Diode Forward Drop

Re-Applied
Voltage

Reverse
Recovery
Current

Body Diode Forward

Current

VGS=10V

V

DD

I

SD

Driver Gate Drive

D.U.T. ISDWaveform

D.U.T. VDSWaveform

Inductor Curent

D =

P. W.

Period

*** V

GS

= 5V for Logic Level Devices

***

+

-

+

+

+

-

-

-







R

G

V

DD

• dv/dt controlled by R

G

• Driver same type as D.U.T.

• I

SD

controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



**

*

*

Use P-Channel Driver for P-Channel Measurements

** Reverse Polarity for P-Channel

Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs

IRF1018E/S/SLPbF

8 www.irf.com

TO-220AB packages are not recommended for Surface Mount Application.

TO-220AB Part Marking Information

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

LOT CODE 1789

EXAMPLE: T HIS IS AN IRF 1010

Note: "P" in assembly line position

indi cates "L ead - F r ee"

IN THE ASSEMBLY LINE "C"

ASS EMBLE D ON WW 19, 2000

INTE RNAT IONAL

PART NUMBER

RECTIFIER

LOT CODE

ASSEMBLY

LOGO

YEAR 0 = 2000

DAT E CODE

WEEK 19
LINE C

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

IRF1018E/S/SLPbF

www.irf.com 9

TO-262 Part Marking Information

LOGO

RECTIFIER

INTERNATIONAL

LOT CODE

ASSEMBLY

LOGO

RECTIFIER

INTERNATIONAL

DAT E CODE

WE E K 1 9

YEAR 7 = 1997

PART NUMBER

A = AS S E MBL Y S I T E CODE

OR

PRODUCT (OPTIONAL)

P = D E S IGN AT E S L EAD - F R E E

EXAMPLE : THIS IS AN IRL3103L

LOT CODE 1789

ASSEMBLY

PART NUMBER

DATE CODE

WEEK 19
LINE C

LOT CODE

YEAR 7 = 1997

ASS EMBL ED ON WW 19, 1997
IN THE ASS EMBLY LINE "C"

TO-262 Package Outline (Dimensions are shown in millimeters (inches))

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

IRF1018E/S/SLPbF

10 www.irf.com

D2Pak Part Marking Information

F530S

THIS IS AN IRF530S WITH

LOT CODE 8024
AS S E MBL ED ON WW 02, 2000
IN T HE AS SEMBLY LINE "L"

ASSEMBLY
LOT CODE

INTE RNATIONAL

RECT IF IER

LOGO

PART NUMBER

DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L

D2Pak Package Outline (Dimensions are shown in millimeters (inches))

DATE CODE

IN T HE AS SEMBLY LINE "L"

AS S E MBL ED ON WW 02, 2000

THIS IS AN IRF530S WITH

LOT CODE 8024

INTE RNATIONAL

LOGO

RECT IF IER

LOT CODE

PART NUMBER

F530S

For GB Production

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

IRF1018E/S/SLPbF

www.irf.com 11

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: [phone]

TAC Fax: [phone]

Visit us at www.irf.com for sales contact information.2/08

D2Pak Tape & Reel Information

3

4

4

TRR

FEED DIRECTION

1.85 (.073)

1.65 (.065)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

TRL

FEED DIRECTION

10.90 (.429)

10.70 (.421)

16.10 (.634)

15.90 (.626)

1.75 (.069)

1.25 (.049)

11.60 (.457)

11.40 (.449)

15.42 (.609)

15.22 (.601)

4.72 (.136)

4.52 (.178)

24.30 (.957)

23.90 (.941)

0.368 (.0145)

0.342 (.0135)

1.60 (.063)

1.50 (.059)

13.50 (.532)

12.80 (.504)

330.00
(14.173)
MAX.

27.40 (1.079)

23.90 (.941)

60.00 (2.362)
MIN.

30.40 (1.197)
MAX.

26.40 (1.039)

24.40 (.961)

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/