Datasheet IMP1233DZ-15T, IMP1233DZ-10T, IMP1233DZ-5T Datasheet (IMP)

Page 1
2000 © IMP, Inc. 408-432-9100/www.impweb.com 1
IMP1
IMP1
233D
233D
POWER MANAGEMENT
Key Features
Applications
Set-top boxes
Cellular phones
Energy management systems
Embedded control systems
Printers
Single board computers
Improved Dallas DS1233D replacement — Over 60% lower maximum supply current
Low Supply Current — 20µA maximum (5.5V) — 15µA maximum (3.6V)
Automatically restarts a microprocessor after power failure
350ms reset delay after VCCreturns to an in-tolerance condition
Active LOW power-up reset, 5kinternal pull-up
Precision temperature-compensated voltage reference and comparator
Eliminates external components
Motorola 68xxx and HC16 compatible
Compact surface mount SOT-223 package
Operating temperature –40°C to +85°C
Block Diagram
Lo
Lo
w P
w Poowwerer
, 5V
, 5V µµ
P R
P R
eset
eset
– A
– A
ctiv
ctiv
e L
e LOOWW
, Open-Dr
, Open-Dr
ain Output
ain Output
– 350ms R
– 350ms R
eset P
eset Perer
iod
iod
The IMP1233D supply voltage monitor is an improved, low-power replacement for the Dallas Semiconductor DS1233D. Maximum supply current over temperature is a low 20µA, representing over 60 percent lower power as compared to the DS1233D.
The IMP1233D issues an active LOW reset signal whenever the moni­tored supply is out-of-tolerance. A precision reference and comparator circuit monitor power supply (V
CC
) level. Tolerance level options are 5-, 10- and 15-percent. When an out-of-tolerance condition is detected, an internal power-fail signal is generated which forces an active LOW reset signal. After V
CC
returns to an in-tolerance condition, the reset signal remains active for 350ms to allow the power supply and system micro­processor to stabilize.
The IMP1233D is designed with a open-drain output stage and operates over the extended industrial temperature range. Devices are available in compact surface mount SOT-223 packages.
Other low power products in this family include the IMP1810/11/12/15/ 16/17 and IMP1233M.
Typical Application
IMP1233D
Microprocessor
RESET
RESET
1233D_02.eps
V
CC
GND
traP
egatloVTESER
)V(
emiTTESER
)sm(
tuptuO
egatS
TESER
ytiraloP
0181PMI021.4,073.4,026.4051lluP-hsuPWOL 1181PMI031.4,053.4,026.4051niarD-nepOWOL 2181PMI031.4,053.4,026.4051lluP-hsuPHGIH 5181PMI055.2,088.2,060.3051lluP-hsuPWOL 6181PMI055.2,088.2,060.3051niarD-nepOWOL 7181PMI055.2,088.2,060.3051lluP-hsuPHGIH
D3321PMI521.4,573.4,526.4053niarD-nepOWOL M3321PMI027.2,573.4,526.4053niarD-nepOWOL
Family Selection Guide
V
CC
Supply
Tolerance
Bias
+
Reference
IMP1233D
Delay
350ms Typical
GND
5.0k
W
RESET
1233D_01.eps
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Pin Configuration
IMP1
IMP1
233D
233D
2 408-432-9100/www.impweb.com 2000 © IMP, Inc.
!
Pin Descriptions
Package Marking Code
Ordering Information
SOT-223
1233D_05a.eps
1
24
3
A
B
C
D
egakcaP
edoCretteL
traP epyT
egakcaP
edoCretteL
teseR
ecnareloT
ABC D
33D D3321PMIA%5
B%01 C%51
yrammuSeciveD gnikraMegakcaP
**traP
rebmuN
TESER
tuptuO
egatloV
)V(
TESER
ecnareloT
)%(
TESER emiT )sm(
egatStuptuO
322-TOS egakcaP
TESER
ytiraloPABC
D
*
niarD-nepOlluP-hsuP
%5=A
%01=B %51=C
T/5-ZD3321PMI526.45053
""
WOL33DA
T/01-ZD3321PMI573.401053
""
WOL33DB
T/51-ZD3321PMI521.451053
""
WOL33DC
k5lanretnI* .pulluprotsiser
.leeRdnaepaTsetacidniT/**
spe.30t_D3321
srebmuNniP
emaNnoitcnuF
322-TOS29-OT
11 DNGdnuorG 22 TESERtuptuoteserWOLevitcA 33V
CC
tupniylppusrewoP
4 DNG)ylnO322-TOS(dnuorG
RESET
GND
2
IMP1233D-X
4
V
3
CC
1
GND
1233D_03.eps
Page 3
Absolute Maximum Ratings
IMP1
IMP1
233D
233D
2000 © IMP, Inc. Microprocessor Supervisor 3
Electrical Characteristics
Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V
Voltage on RESET . . . . . . . . . . . . . . . . . . . . . –0.5V to V
CC
+ 0.5V
Operating Temperature Range . . . . . . . . . . . –40°C to 85°C
Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Voltages measured with respect to ground. These are stress ratings only and functional operation is not implied.
Parameter Symbol Conditions Min Typ Max Units
Supply Voltage V
CC
1.2 5.5 V
Output Voltage V
OH
I
OUT
< 500µAV
CC
– 0.5V VCC– 0.1V V
Output Current I
OL
Output = 0.4V, VCC≥ 2.7V +8 mA
Operating Current I
CC
VCC< 5.5V, RESET output open 8 20 µA
Operating Current I
CC
VCC≤ 3.6V, RESET output open 6 15 µA
VCCTrip Point (IMP1233D-5) V
CCTP
4.50 4.625 4.74 V
VCCTrip Point (IMP1233D-10) V
CCTP
4.25 4.375 4.49 V
VCCTrip Point (IMP1233D-15) V
CCTP
4.00 4.125 4.24 V
Internal Pull-Up Resistor R
P
3.5 5.0 7.5 k
Output Capacitance C
OUT
10 pF
RESET Active Time t
RESET
250 350 450 ms
VCCDetect to RESET Low t
RPD
25µs
VCCSlew Rate t
F
300 µs
(V
HTL
- V
LTL
)
VCCSlew Rate t
R
0ns
(V
LTL
- V
HTL
)
V
CC
Detect to RESET High t
RPU
tR= 5µs 250 350 450 ms
Unless otherwise noted, VCC= 1.2V to 5.5V and specifications are over the operating temperature range of –40°C to +85°C. All voltages are referenced to ground.
Page 4
IMP1
IMP1
233D
233D
4 408-432-9100/www.impweb.com 2000 © IMP, Inc.
!
Operation – Power Monitor
The IMP1233D detects out-of-tolerance power supply conditions. It resets a processor during power-up and issues a reset to the sys­tem processor when the monitored power supply voltage is below the reset threshold (power-down). When an out-of-tolerance V
CC
voltage is detected, the RESET signal is asserted. On power-up, RESET is kept active (LOW) for approximately 350ms after the power supply voltage has reached the selected tolerance. This allows the power supply and microprocessor to stabilize before RESET is released.
Figure 1. Timing Diagram: Power-Up
Figure 2. Timing Diagram: Power-Down
V
CCTP
(MAX)
V
CCTP
V
CCTP
(MIN)
V
CC
RESET
t
R
t
RPU
V
OH
1233D_06.eps
V
CCTP
(MAX)
V
CCTP
V
CCTP
(MIN)
V
CC
RESET
t
F
V
OL
t
RPD
1233D_07.eps
Application Information
Page 5
Package Dimensions
IMP1
IMP1
233D
233D
2000 © IMP, Inc. Microprocessor Supervisor 5
Plastic SOT-223 (4-Pin)
E
A
e1
A1
C
H
e
D
S
B1
B
Q2
Q1
Q
SOT-223 (4-Pin).eps
sehcnIsretemilliM
niMxaMniMxaM
)niP-4(*322-TOScitsalP
A760.0060.007.105.1
1A400.08000.001.020.0
B421.0611.051.359.2
1B330.0620.058.056.0 C410.0010.053.052.0 D462.0842.007.603.6
eMON5090.0MON03.2
1eMON181.0MON05.4 E641.0031.007.303.3
h782.0462.003.707.6
S140.0330.050.158.0
t150.0340.003.101.1
QXAM°01XAM°01
1Q °61 °01 °61 °01 2Q °61 °01 °61 °01
*.dradnatserasdaeldemroF
spe.50t_D3321
Page 6
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134-2071 Tel: 408-432-9100 Tel: 800-438-3722 Fax: 408-434-0335 e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
2000 ©IMP, Inc. Printed in USA Publication #: 1012 Revision: B Issue Date: 06/01/00 Type: Preliminary
IMP1
IMP1
233D
233D
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