Datasheet HV9105P, HV9105PJ, HV9108P, HV9108PJ Datasheet (Supertex)

High-Voltage Switchmode Controllers with MOSFET

Ordering Information

HV9105
HV9108

IN

BV

DSS

200V 5.0Ω 10V 120V ±1% 49% HV9105P HV9105PJ

200V 5.0Ω 10V 120V ±1% 99% HV9108P HV9108PJ

Standard temperature range for all parts is industrial (-40° to +85°C).

R

DS(ON)

Min Max Voltage Duty Cycle 14 Pin Plastic DIP 20 Pin Plastic PLCC

Features

❏ 10 to 120V input range

❏ 200V, 5Ω output MOSFET

❏ Current-Mode Control

❏ High Efficiency

❏ CCITT Compatible

❏ Internal Start-up Circuit

Applications

❏ DC/DC Converters

❏ Distributed Power Systems

❏ ISDN Equipment

❏ PBX Systems

❏ Modems

Feedback Max

General Description

The Supertex HV9105 and HV9108 are high-efficiency high
voltage SMPS ICs intended for use in power converters requiring
extreme efficiency at output power levels of 5.0W or less. The low
supply current (0.5mA max) allows them to be used to build
supplies which meet CCITT I.430 performance recommenda­tions (60% efficiency at .025W out).

The HV9105/08 provides all the functions necessary to build a
single-switch current-mode converter of any common topology,
with a minimum of external parts.

In addition to high efficiency, because it uses Supertex’s propri­etary high voltage BiCMOS/DMOS technology, the HV9105/08
offers numerous performance advantages when compared to
conventional PWM ICs. Dynamic range is approximately 8 times
wider than with bipolar ICs, both response speed and maximum
clock rate are faster, and no external power resistors or zeners are
necessary for high voltage starting.

Accessory circuits are included to provide either latching or
nonlatching shutdown. When shut down, device dissipation is
less than 4mW.

The HV9105/08 is intended for operation with input voltages from
10 to 120VDC.

Package OutlinesMOSFET Switch +V

Absolute Maximum Ratings

+VIN, Input Voltage 120V

V

DS

VDD, Logic Voltage 15.0V

Control Inputs -0.3V to VDD+0.3V

ID (Peak) 2.5A

Storage Temperature -65°C to 150°C

Power Dissipation, Plastic DIP 750mW

Power Dissipation, PLCC 1400mW

11/12/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

200V

For detailed circuit and application information, please refer
to application notes AN-H13 and AN-H21 to AN-H24.

1

Electrical Characteristics

(V

= 10V, +V

DD

Symbol Parameters Min Typ Max Unit Conditions

Reference

= 48V, Discharge = -V

IN

= 0V, R

IN

= 820KΩ, R

BIAS

= 910KΩ,TA = 25°C, unless otherwise specified)

OSC

HV9105/HV9108

V

REF

Z

OUT

I

SHORT

∆V

Output Voltage 3.92 4.00 4.08 V RL = 10MΩ

Output Impedance

Short Circuit Current 100 130 µAV

Change in V

REF

Oscillator

f

MAX

f

OSC

Maximum Oscillator Frequency 1.0 3.0 MHz R

Initial Accuracy

Voltage Stability

Temperature Coefficient

PWM

D

MAX

D

MIN

Maximum Duty Cycle

Deadtime

Minimum Duty Cycle 0 %

Minimum Pulse Width 110 175 nsec
Before Pulse Drops Out

Error Amplifier

V

FB

Feedback Voltage 3.96 4.00 4.04 V VFB Shorted to Comp

1

with Temperature 0.25 mV/°C

REF

2

1

1

1

HV9105 49.0 49.4 49.6 %

15 30 45 KΩ

32 40 48 KHz

15 % 9.5V < V

170 ppm/°C

HV9108 99.0 99.4 99.6

1

HV9108 100 nsec

1

REF

OSC

= -V

= 0Ω

IN

< 13.5V

DD

I

IN

V

OS

A

VOL

gbw Unity Gain Bandwidth

Z

OUT

I

SOURCE

I

SINK

PSRR Power Supply Rejection

Input Bias Current 25 500 nA V

Input Offset Voltage nulled at trim mV

Open Loop Voltage Gain

Output Impedance

1

1

1

Output Source Current -1.3 -1.0 mA V

Output Sink Current 50 80 µAV

1

Current Limit

V

SOURCE

t

d

Threshold Voltage 1.0 1.2 1.4 V V

Delay to Output

1

Pre-Regulator/Startup

+V

V

TH

V

LOCK

Notes:

1. Guaranteed by design. Not subject to production test.

2. Stray capacitance on OSC IN pin ≤5pF.

Allowable Input Voltage 120 V I

IN

Input Leakage Current 10 µAV

VDD Pre-regulator Turn-off 7.8 8.6 9.4 V I
Threshold Voltage

Undervoltage Lockout 7.0 8.1 8.9 V RL = 100Ω from Drain to V

60 80 dB

0.5 0.8 MHz

See Fig. 2 Ω

See Fig. 1

150 200 ns V

= 4.0V

FB

= 3.4V

FB

= 4.5V

FB

= 0V, RL = 100Ω

FB

= 1.5V, RL = 100Ω

SOURCE

= 10µA

IN

> 9.4V

DD

= 10µA

PREREG

DD

2

Electrical Characteristics (Continued)

(V

= 10V, +V

DD

Symbol Parameters Min Typ Max Unit Conditions

Supply

= 48V, Discharge = -V

IN

= 0V, R

IN

= 820KΩ, R

BIAS

= 910KΩ,TA = 25°C, unless otherwise specified)

OSC

HV9105/HV9108

I

DD

I

BIAS

V

DD

Supply Current 0.6 mA

Bias Current 7.5 µA

Operating Range 9.0 13.5 V

Logic

t

SD

t

SW

t

RW

t

LW

V

IL

V

IH

I

IH

I

IL

Shutdown Delay Time

Shutdown Pulse Width

RESET Pulse Width

Latching Pulse Width

Input Low Voltage 2.0 V

Input High Voltage 7.0 V

Input High Current 1.0 5.0 µAVIN = 10V

Input Low Current -25 -35 µAVIN = 0V

1

1

1

1

MOSFET Switch

BV

R

DS(ON)

I

DSS

C

DS

Note:

1. Guaranteed by design. Not subject to production test.

Breakdown Voltage 200 240 V V

DSS

Drain-to-Source On-resistance 3.5 5.0 Ω V

OFF State Drain Leakage Current 10 µAV

Drain Capacitance 35 pF V

0.35 mA Shutdown = -V

50 100 ns V

50 ns

50 ns

25 ns

IN

= -V

SOURCE

SOURCE

I

= 100µA

D

SOURCE

SOURCE

V

DRAIN

= 25V, Shutdown = 0V

DS

IN

= Shutdown = 0V,

= 0V, ID = 100mA

= Shutdown = 0V,

= 100V

Truth Table

Shutdown Reset Output

H H Normal Operation

HH → L Normal Operation, No Change

L H Off, Not Latched

L L Off, Latched

L → H L Off, Latched, No Change

3

Switching Waveforms

1.5V

Source

Drain

Shutdown

Reset

V

DD

50%

0

t

d

0

V

DD

50%

0

V

DD

0

t

≤ 10ns

R

50%

HV9105/HV9108

t

V

DD

SHUTDOWN

50%

0

t

SD

V

DD

Drain

0

t

SW

90%90%

50%

t

LW

50%

t

RW

50%

≤ 10ns

F

, tF ≤ 10ns

t

R

Functional Block Diagram

COMP Discharge

Error
Amplifier

–

+

4V

To
Internal
Circuits

–

+

8.6V

BIAS

+V

FB

14

(20)

V

10 (14)

REF

REF
GEN

1 (2)

Current

Sources

6 (9)

V

DD

2 (3)

IN

Pre-regulator/Startup

13

(18)9(12)

2V

1.2V

8.1V

–

+

+

–

–

+

OSC

8

(11)

Current-mode

Comparator

C/L

Comparator

Undervoltage
Comparator

In

OSC

OSC

Out

(10)

R

S

7

TQ

9108

Q

V

DD

9105

(5) 3

Drain

(8) 5

-V

IN

V

DD

S

Q

R

(7) 4

(16) 11

(17) 12

Source

Shutdown

Reset

Pin numbers in parentheses are for PLCC package.

4

+

–

Reference

V

1

V

2

0.1V swept 10Hz – 1MHz

0.1µF

10.0V

4.00V

100K1%

100K1%

PSRR

Typical Performance Curves

HV9105/HV9108

Fig. 1

Fig. 2

PSRR – Error Amplifier and Reference

0

-10

-20

-30

-40

(dB)(Ω)

-50

-60

-70

-80

100KHz1KHz10Hz 100Hz 10KHz 1MHz

Fig. 3

80

70

60

50

40

30

Gain (dB)

20

10

0

-10

100Hz 1KHz 10KHz

Error Amplifier

Open Loop Gain/Phase

100KHz 1MHz

240°

180°

120°

60°

-60°

-120°

-180°

0°

Phase

Frequency

Error Amplifier Output Impedance (Z0)

6

10

5

10

4

10

3

10

Fig. 4

1M

Output Switching Frequency

vs. Oscillator Resistance

HV9105

HV9108

Test Circuits

+10V

(V

)

DD

(FB)

GND

(–V

)

IN

2

10

10

1.0

0.1

.01

100Hz 1KHz 10KHz

Error Amp Z

Reference

0.1µF

100k

OUT

f (Hz)

100KHz

OUT

1MHz

10MHz

10k

10k

100 k

R

OSC

1M

(Ω)

1.0V swept 100Hz – 2.2MHz

60.4K

–

+

Tektronix

P6021
(1 turn

V

1

secondary)

V

2

40.2K

NOTE: Set Feedback Voltage so that
V

COMP

= V

± 1mV before connecting transformer

DIVIDE

5

Technical Description

HV9105/HV9108

Preregulator

The preregulator/startup circuit for the HV9105/08 consists of a
high-voltage N-channel depletion-mode DMOS transistor driven
by an error amplifier to form a controlled current path between the

terminal and the VDD terminal of the HV9105/08. Maximum

V

IN

current (about 20 mA) occurs when V

rises. This path shuts off altogether when VDD rises to

as V

DD

somewhere between 7.8 and 9.4V, so that if V

= 0, with current reducing

DD

is held at 10 or

DD

12V by an external source (generally the supply the chip is
controlling) no current other than leakage is drawn through the
high voltage transistor. This minimizes dissipation.

An external capacitor between VDD and VSS is generally required
to store energy used by the chip during the time between shutoff
of the high voltage path and the V

supply’s output rising enough

DD

to take over the powering of the chip. This capacitor generally also
serves as the output filter capacitor for that output from the supply.

1.0µF is generally sufficient to assure against double-starting.
Capacitors as small as 0.1µF can work when faster response from
the V

line is required. The chosen capacitor should have very

DD

good high frequency characteristics and be mounted so that the
sum of the lead length between capacitor and IC for both leads is
less than 2.5 cm. Stacked polyester or ceramic capacitors work
well. Electrolytic capacitors are generally not suitable.

A common resistor divider string is used to monitor V

for both

DD

the undervoltage lockout circuit and the shutoff circuit of the high
voltage FET. Setting the undervoltage sense point about 0.6V
lower on the string than the FET shutoff point guarantees that the
undervoltage lockout always releases before the FET shuts off.

Bias Circuit

An external bias resistor, connected between the bias pin and V
is required by the HV9105/08 to set currents in a series of current
mirrors used by the analog sections of the chip. Nominal external
bias current requirement is 7.5µA, which can be set by a 820KΩ
to 1.3MΩ resistor if a 10V V
resistor if a 12V V

is used. A precision resistor is NOT required;

DD

is used, or a 1.2MΩ to 2.0MΩ

DD

± 5% is fine.

For extremely low power operation, the value of bias current can
be reduced to as low as 4.0µA by further increases in the value of
the bias resistor.

SS

Clock Oscillator

The clock oscillator of the HV9105/08 consists of a ring of CMOS
inverters, timing capacitors, a capacitor discharge FET, and, in
the 50% maximum duty cycle version, a frequency dividing flip­flop. A single external resistor between the OSC In and OSC Out
pins is required to set oscillator frequency (see Fig. 4). For the
50% maximum duty cycle versions the ‘Discharge’ pin is internally
connected to GND. For the 99% duty cycle version, ‘Discharge’
can either be connected to V
through a resistor used to set a deadtime.

One difference exists between the Supertex HV9105/08 and
competitive 9105 parts. The oscillator of the Supertex HV9105/08
is shut off when a shutoff command is received. This saves about
100µA of quiescent current, which aids in the construction of
power supplies to meet CCITT specification I.430, and in other
situations where an absolute minimum of quiescent power dissi­pation is required.

directly or connected to V

SS

SS

Reference

The reference section of the HV9105/08 consists of a stable
bandgap reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of the
reference buffer amplifier are trimmed during manufacture so that
the output of the error amplifier when connected in a gain of -1
configuration is as close to 4.000V as possible. This nulls out any
input offset of the error amplifier. As a consequence, even though
the observed reference voltage of a specific part may not be
exactly 4.0V, the feedback voltage required for proper regulation
will be 4.0V.

A resistor of approximately 50KΩ is placed internally between the
output of the reference buffer amplifier and the circuitry it feeds
(reference output pin and non-inverting input to the error ampli­fier). This allows overriding the internal reference with a low­impedance voltage source ≤6.0V. In general, because the refer­ence voltage of the Supertex HV9105/08 is not noisy, as some
previous devices have been, overriding the reference should
seldom be necessary.

Because the reference is a high impedance node, and usually
there will be significant electrical noise near it, a bypass capacitor
between the reference pin and V

is strongly recommended. The

SS

reference buffer amplifier is intentionally compensated to be
stable with a capacitive load of 0.01 to 0.1µF.

Error Amplifier

The error amplifier is a true low-power differential input opera­tional amplifier intended for around-the-amplifier compensation.
It is of mixed CMOS-bipolar construction: a PMOS input stage is
used so the common-mode range includes ground and the input
impedance is very high. This is followed by bipolar gain stages
which provide high gain without the electrical noise of all-MOS
amplifiers. The amplifier is unity-gain stable.

Current Sense Comparators

The HV9105/08 uses a true dual comparator system with inde­pendent comparators for modulation and current limiting. This
allows the designer greater latitude in compensation design, as
there are no clamps (except ESD protection) on the compensa­tion pin. Like the error amplifier, the comparators are of low-noise
BiCMOS construction.

Remote Shutdown

The shutdown and reset pins can be used to perform either
latching or non-latching shutdown of a converter as required.
These pins have internal current source pull-ups so they can be
driven from open-drain logic. When not used, they should be left
open, or connected to V

DD

.

Main Switch

The main switch is a normal N-channel power MOSFET. Unlike
the situation with competitive devices, the body diode can be used
if desired without destroying the chip.

6

Pinout

HV9105/HV9108

BIAS

+V

Drain

Source

–V

V

DD

OSC Out

1

2

IN

3

4

5

IN

6

7

14 Pin DIP Package

14

13

12

11

10

9

8

Feedback

COMP

Reset

Shutdown

V

REF

Discharge

OSC In

NC

Feedback

NC

BIAS

+V

COMP

Reset

Shutdown

18 17 16

19

20

1

•

2

3

IN

4 5 6

NC

15 14

NC

Drain

NC

7 8

Source

–V

REF

V

IN

NC

13

Discharge

12

OSC In

11

OSC Out

10

V

9

DD

20-pin PJ Package

top view

©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.

11/12/01

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: [phone] • FAX: [phone]

7

www.supertex.com