Datasheet HT1650 Datasheet (Holtek Semiconductor Inc)

64´32 LCD Controller for I/O MCU

Technical Document

·

FAQs

·

Application Note

Features

·

Operating voltage: 2.7V~5.2V

·

Built-in 32kHz RC oscillator

·

External 32.768kHz crystal oscillator or 32kHz fre quency source input

·

Standby current: <1mA at 3V, <2mAat5V

·

Internal resistor type: 1/6 bias or 1/5 bias, 1/32 duty, and 1/16 duty

·

Three selectable LCD frame frequencies: 64Hz, 89Hz or 170Hz

·

Max. of 64´32 patterns, 64 segments and 32 com mons

·

80 segments and 16 commons selectable by com mand method

·

Built-in bit-map display RAM: 2048 bits (=64´32 bits)

·

Built-in internal resistor type bias generator

HT1650

·

Six-wire interface (four data wires)

·

Eight kinds of time base or WDT selection

·

-

Time base or WDT overflow output

·

R/W address auto increment

·

Built-in buzzer driver (2kHz/4kHz)

·

Power down command reduces power consumption

·

Software configuration feature

·

Data mode and Command mode instructions

·

Three data accessing modes

·

Provides VLCD pin to adjust LCD operating voltage and max. VLCD voltage up to 7V

·

Provides three kinds of bias current programming

·

Control of TN-type and STN-type LCDs

·

128-pin QFP package

Applications

·

Leisure products

·

Games

·

Personal digital assistant

General Description

HT1650 is a peripheral device specially designed for I/O type MCUs which are used to expand the display capa bility. The max. display segment of the device are 2048 patterns (64 segments and 32 commons). It also sup ports four data bits interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1650 is a memory mapping and multi-function LCD controller. It

·

Cellular phone

·

Global positioning system

·

Consumer electronics

can control TN-type (Twisted Nematic) or STN-type

-

(Super Twisted Nematic) LCDs. The software configu ration feature of the HT1650 make it suitable for multiple

-

LCD applications including LCD modules and display subsystems. Only six lines (CS

,WR, DB0~DB3) are re quired for the interface between the host controller and the HT1650.

-

Rev. 1.20 1 November 10, 2005

Block Diagram

HT1650

Pin Assignment

C O M 1 8 C O M 1 7 C O M 1 6

D B 0 D B 1 D B 2 D B 3 V S S

O S C I

O S C O

V D D

V L C D

I R Q

T 0 0 0

V L C D

C O M 0 C O M 1 C O M 2

O S C O

O S C I

C S

R D

W R

C o n t r o l

& T i m i n g C i r c u i t

D B 0

D B 3

V D D

V S S

B Z

C O M 1 9

1 2 8

1

2

3

4

N C

5

N C

6

N C

7

N C

8

N C

9

N C

1 0

C S

1 1

R D

1 2

W R

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

B Z

2 4

B Z

2 5

T 1

2 6

T 2

2 7

T 3

2 8

T 4

2 9

3 0

3 1

N C

3 2

N C

3 3

N C

3 4

N C

3 5

N C

3 6

3 7

3 8

3 9 5 4

C O M 3

T o n e F r e q u e n c y

G e n e r a t o r

N o t e : C S : C h i p s e l e c t i o n

B Z , B Z : T o n e o u t p u t s W R , R D : W R I T E c l o c k , R E A D c l o c k D B 0 ~ D B 3 : D a t a b u s C O M 0 ~ C O M 3 1 , S E G 0 ~ S E G 6 3 : L C D o u t p u t s I R Q : T i m e b a s e o r W D T o v e r f l o w o u t p u t

C O M 2 6

C O M 2 5

C O M 2 4

C O M 2 3

C O M 2 2

C O M 2 1

C O M 2 0

1 2 5

1 2 4 1 2 1

1 2 61 2 7

4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 04 0 5 1 5 2 5 3

C O M 5

C O M 4

1 2 21 2 3

C O M 1 0

C O M 9

C O M 8

C O M 7

C O M 6

C O M 2 9

C O M 2 8

C O M 2 7

1 2 0 1 1 9

1 1 8 1 1 7 1 1 6

1 2 8 Q F P - A

C O M 1 3

C O M 1 2

C O M 1 1

D i s p l a y R A M

L C D D r i v e r / B i a s C i r c u i t

W a t c h d o g T i m e r

&

T i m e B a s e G e n e r a t o r

C O M 3 1

C O M 3 0

S E G 6 3

1 1 5 1 1 4

S E G 6 0

S E G 6 1

S E G 6 2

1 1 2 1 1 1

1 1 3

H T 1 6 5 0

5 5 5 6 5 7 5 8 5 9

S E G 3

S E G 2

S E G 1

S E G 0

C O M 1 5

C O M 1 4

C O M 0

C O M 3 1

S E G 0

S E G 6 3

V L C D

I R Q

S E G 5 1

S E G 5 2

S E G 5 3

S E G 5 4

S E G 5 5

S E G 5 6

S E G 5 7

S E G 5 8

S E G 5 9

1 0 9

1 1 0

1 0 8 1 0 7

S E G 7

S E G 6

S E G 5

S E G 4

1 0 4 1 0 3

1 0 6 1 0 5

6 0 6 1 6 2 6 3 6 4

S E G 1 1

S E G 1 0

S E G 9

S E G 8

1 0 2

S E G 5 0

1 0 1

S E G 4 9

1 0 0

S E G 4 8

9 9

S E G 4 7

9 8

S E G 4 6

9 7

S E G 4 5

9 6

S E G 4 4

9 5

S E G 4 3

9 4

S E G 4 2

9 3

S E G 4 1

9 2

S E G 4 0

9 1

S E G 3 9

9 0

S E G 3 8

8 9

S E G 3 7

8 8

S E G 3 6

8 7

S E G 3 5

8 6

S E G 3 4

8 5

S E G 3 3

8 4

S E G 3 2

8 3

S E G 3 1

8 2

S E G 3 0

8 1

S E G 2 9

8 0

S E G 2 8

7 9

S E G 2 7

7 8

S E G 2 6

7 7

S E G 2 5

7 6

S E G 2 4

7 5

S E G 2 3

7 4

S E G 2 2

7 3

S E G 2 1

7 2

S E G 2 0

7 1

S E G 1 9

7 0

S E G 1 8

6 9

S E G 1 7

6 8

S E G 1 6

6 7

S E G 1 5

6 6

S E G 1 4

6 5

S E G 1 3

S E G 1 2

Rev. 1.20 2 November 10, 2005

Pad Assignment

1

S E G 4 7

2

S E G 4 8

3

S E G 4 9 S E G 5 0

4

S E G 5 1

5

S E G 5 2

6

S E G 5 3

7

S E G 5 4

8

S E G 5 5

9

S E G 5 6

1 0

S E G 5 7

1 1

S E G 5 8

1 2

S E G 5 9

1 3

S E G 6 0

1 4

S E G 6 1

1 5

S E G 6 2

1 6 1 7

S E G 6 3

1 8

C O M 3 1

1 9

C O M 3 0

2 0

C O M 2 9 C O M 2 8

2 1 2 2

C O M 2 7 C O M 2 6

2 3

C O M 2 5

2 4

2 5

C O M 2 4

2 6

C O M 2 3 C O M 2 2

2 7

C O M 2 1

2 8 2 9

C O M 2 0 C O M 1 9

3 0

3 1

C O M 1 8

S E G 4 4

S E G 4 5

S E G 4 6

1 1 5

1 1 4

1 1 7

1 1 6

3 4 3 5 3 6 3 7 3 8 3 9

3 3

3 2

C O M 1 7

C O M 1 6

C S

HT1650

S E G 1 7

S E G 1 8

S E G 1 9

S E G 2 0

S E G 2 1

S E G 2 2

S E G 2 3

S E G 2 4

S E G 2 5

S E G 2 6

S E G 2 7

S E G 2 8

S E G 2 9

S E G 3 0

S E G 3 1

S E G 3 2

S E G 3 3

S E G 3 4

S E G 3 5

S E G 3 6

S E G 3 7

S E G 3 8

S E G 3 9

S E G 4 0

S E G 4 1

S E G 4 2

S E G 4 3

1 0 3

1 0 6

1 0 9

1 1 2

1 1 1

1 1 3

1 1 0

W R

R D

D B 0

D B 1

1 0 5

1 0 8

1 0 7

4 0 4 1

D B 2

D B 3

V S S

1 0 4

4 2 4 3

O S C I

1 0 1

1 0 2

1 0 0

9 9

( 0 , 0 )

4 5

4 6

4 4

O S C O

I R Q

V L C D

V D D

9 5

9 69 79 8

9 39 4

5 0

4 9

4 8

4 7

T 2

T 1

B Z

8 9

9 1

9 0

9 2

8 8

8 7

S E G 1 6

8 6

S E G 1 5 S E G 1 4

8 5

S E G 1 3

8 4

S E G 1 2

8 3

S E G 1 1

8 2

S E G 1 0

8 1

S E G 9

8 0

S E G 8

7 9

S E G 7

7 8

S E G 6

7 7

S E G 5

7 6

S E G 4

7 5 7 4

S E G 3

7 3

S E G 2

7 2

S E G 1

7 1

S E G 0

7 0

C O M 1 5

6 9

C O M 1 4

6 8

C O M 1 3

6 7

C O M 1 2

6 6

C O M 1 1

6 5

C O M 1 0

6 4

C O M 9

6 3

C O M 8

6 2

C O M 7

6 1

C O M 6

6 0

C O M 5 C O M 4

5 9

C O M 3

5 8

5 2

5 1

5 3

5 4

T 0 0 0

T 4

T 3

5 7

5 5 5 6

V L C D

C O M 0

C O M 1

C O M 2

Chip size: 4105´3840 (mm)

2

* The IC substrate should be connected to VSS in the PCB layout artwork.

Pad Coordinates

Unit: mm

Pad No. X Y Pad No. X Y Pad No. X Y

10 11 12 13 14 15 16 17

1 2 3 4 5 6 7 8 9

-1921.00

1635.35 40

1535.35 41

1435.35 42

1335.35 43

-417.35 -1639.80

-276.25 -1639.80

-141.75 -1644.30

-3.55 -1644.30

1235.35 44 137.25

1135.35 45 212.30

1035.35 46 393.90

935.35 47 540.40

835.35 48 675.80

735.35 49 835.40

635.35 50 983.60

535.35 51 1130.60

435.35 52 1278.80

335.35 53 1425.80

235.35 54 1577.90

135.35 55 1714.90

35.35 56 1814.90

-1711.95

-1576.95

-1598.20

-1639.90

-1701.15

-1751.90

79 1918.10 639.60 80 1918.10 739.60 81 1918.10 839.60 82 1918.10 939.60 83 1918.10 1039.60 84 1918.10 1139.60 85 1918.10 1239.60 86 1918.10 1339.60 87 1918.10 1439.60 88 1454.90 1760.40 89 1354.90 1760.40 90 1254.90 1760.40 91 1154.90 1760.40 92 1054.90 1760.40 93 954.90 1760.40 94 854.90 1760.40 95 754.90 1760.40

Rev. 1.20 3 November 10, 2005

HT1650

Pad No. X Y Pad No. X Y Pad No. X Y

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

-1921.00 -64.65

-1921.00 -164.65

-1921.00 -264.65

-1921.00 -364.65

-1921.00 -464.65

-1921.00 -564.65

-1921.00 -664.65

-1921.00 -764.65

-1921.00 -864.65

-1921.00 -964.65

-1921.00 -1064.65

-1921.00 -1164.65

-1921.00 -1264.65

-1612.45 -1747.70

-1512.45 -1747.70

-1412.45 -1747.70

-1258.55 -1639.80

-1115.95 -1639.80

-980.55 -1639.80

-833.65 -1639.80

-698.25 -1639.80

-552.95 -1639.80

57 1914.90 58 1918.10 59 1918.10 60 1918.10 61 1918.10 62 1918.10 63 1918.10 64 1918.10 65 1918.10 66 1918.10 67 1918.10 68 1918.10 69 1918.10 70 1918.10 71 1918.10 72 1918.10 73 1918.10 39.60 112 74 1918.10 139.60 113 75 1918.10 239.60 114 76 1918.10 339.60 115 77 1918.10 439.60 116 78 1918.10 539.60 117

-1751.90

-1465.70

-1365.70

-1265.70

-1165.70

-1065.70

-965.70

-865.70

-765.70

-665.70

-565.70

-465.70

-365.70

-265.70

-160.40

-60.40

96 654.90 1760.40 97 554.90 1760.40 98 454.90 1760.40

99 354.90 1760.40 100 254.90 1760.40 101 154.90 1760.40 102 54.90 1760.40 103 104 105 106 107 108 109 110 111

-45.10

-145.10

-245.10

-345.10

-445.10

-545.10

-645.10

-745.10

-845.10

-945.10

-1045.10

-1145.10

-1245.10

-1345.10

-1445.10

1760.40

Pad Description

Pad No. Pad Name I/O Description

1~17 71~117

18~33 55~70

34 CS

35 RD

36 WR

37~40 DB0~DB3 I/O Parallel data input/output with pull-high resistor

41 VSS

42 43

44 VDD

45 VLCD I Power supply for LCD driver circuit

46 IRQ

47, 48 BZ, BZ

49~53 T1~T4, T000 I

SEG47~SEG63 SEG0~SEG46

COM31~COM16 COM0~COM15

OSCI OSCO

O LCD segment outputs

LCD common outputs, under 80´16 command mode, COM16~COM31 will

O

be shared with SEG64~SEG79. COM31/SEG64, COM30/SEG65,

COM29/SEG66....., COM18/SEG77, COM17/SEG78, COM16/SEG79

Chip selection input with pull-high resistor. When the CS data and command read from or write to the HT1650 are disabled. The serial interface circuit is also reset. But if the CS

I

the CS

pad, the data and command transmission between the host controller

and the HT1650 are all enabled.

READ clock input with pull-high resistor. Data in the RAM of the HT1650 are clocked out on the falling edge of the RD

I

pear on the data line. The host controller can use the next rising edge to latch the clocked out data.

WRITE clock input with pull-high resistor. Data on the DATA line are latched

I

into the HT1650 on the rising edge of the WR

Negative power supply for logic circuit, ground

¾

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock

I

source, the external clock source should be connected to the OSCI pad. But

O

if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left open.

Positive power supply for logic circuit

¾

O Time base or Watchdog Timer overflow flag, NMOS open drain output.

O 2kHz or 4kHz frequency output pair (tristate output buffer)

Vary bias current pin It is usually not connected

is at a logic low level and is input to

signal. The clocked out data will ap

is logic high, the

-

signal.

Rev. 1.20 4 November 10, 2005

HT1650

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+5.5V

Input Voltage.............................V

-0.3V to VDD+0.3V

SS

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil ity.

Storage Temperature ............................-50°Cto125°C

Operating Temperature...........................-25°Cto75°C

-

D.C. Characteristics

Symbol Parameter

V

DD

I

DD1

I

DD2

I

DD11

I

DD22

I

STB

V

IL

V

IH

I

OL1

I

OH1

I

OL2

I

OH2

I

OL3

I

OH3

I

OL4

I

OH4

R

PH

Operating Voltage

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

BZ, BZ, IRQ Sink Current

BZ, BZ Source Current

DB0~DB3 Sink Current

DB0~DB3 Source Current

LCD Common Sink Current

LCD Common Source Current

LCD Segment Sink Current

LCD Segment Source Current

Pull-high Resistor

Test Conditions

V

DD

Conditions

¾¾

3V

No load/LCD ON On-chip RC oscillator

5V

3V

No load/LCD ON Crystal oscillator

5V

3V

No load/LCD OFF On-chip RC oscillator

5V

3V

No load/LCD OFF Crystal oscillator

5V

3V

No load, Power down mode

5V

3V

DB0~DB3, WR,CS,RD

5V 0

3V

DB0~DB3, WR,CS,RD

5V 4.0

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V 60 125 210

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

=4.5V

V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

=4.5V

V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

=4.5V

V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

=4.5V

V

OH

DB0~DB3, WR,CS,RD

Min. Typ. Max. Unit

2.7

¾

5.2 V

¾

150 250

250 370

135 200

200 300

15 30

50 70

210

310

¾¾

0

2.4

¾

0.6 V

1.0 V

¾

1.2 2.5

36

-0.9 -1.8 ¾

-2 -4 ¾

1.2 2.5

36

-0.9 -1.8 ¾

-2 -4 ¾

80 160

180 360

-40 -80 ¾mA

-90 -180 ¾mA

50 100

120 240

-30 -60 ¾mA

-70 -140 ¾mA

150 250 410

Ta=25°C

mA

A

m

mA

1

mA

2

mA

3V

5V

mA

¾

mA

¾

mA

¾

mA

¾

mA

¾mA

kW

Rev. 1.20 5 November 10, 2005

HT1650

A.C. Characteristics

Symbol Parameter

f

t

f

t

System Clock

SYS1

System Clock

SYS2

System Clock

SYS3

LCD Frame Frequency

LCD1

LCD Frame Frequency

LCD2

LCD Frame Frequency

LCD3

LCD Common Period

COM

4-Bit Data Clock (WR Pin)

CLK1

4-Bit Data Clock (RD Pin)

CLK2

4-Bit Interface Reset Pulse Width

CS

(Figure 3)

WR,RDInput Pulse Width (Figure 1)

CLK

Rise/Fall Time Serial Data Clock

r,tf

Width (Figure 1)

Setup Time for DB to WR,RDClock

su

Width (Figure 2)

Hold Time for DB to WR,RDClock

h

Width (Figure 2)

Setup Time for CS to WR,RDClock

su1

Width (Figure 3)

Hold Time for CS to WR,RDClock

h1

Width (Figure 3)

Ta=25°C

Test Conditions

V

DD

3V

5V 24 32 40 kHz

Conditions

On-chip RC oscillator

3V

Crystal oscillator

5V

3V

External clock source

5V

3V

On-chip RC oscillator

5V 61/117 89/170 111/213 Hz

3V

Crystal oscillator

5V

3V

External clock source

5V

n: Number of COM

¾

3V

Duty cycle 50%

5V

3V

Duty cycle 50%

5V

CS

¾

Write mode 3.34

3V

Read mode 6.67

Write mode 1.67

5V

Read mode 3.34

3V

5V

¾¾

3V

5V

¾¾

3V

5V

¾¾

3V

5V

¾¾

3V

5V

¾¾

Min. Typ. Max. Unit

22 32 40 kHz

32.768

¾

32.768

¾

32

¾

kHz

61/117 89/170 111/213 Hz

n/f

64

LCD

250

¾

sec

150 kHz

300 kHz

75 kHz

150 kHz

¾

¾¾

¾

¾¾ms

120

100

¾

Hz

ns

Rev. 1.20 6 November 10, 2005

HT1650

W R , R D C l o c k

t

9 0 %

f

5 0 %

1 0 %

t

C L K

t

r

t

C L K

Figure 1

t

W R , R D C l o c k

C S

5 0 %

t

5 0 %

F i r s t

C l o c k

t

s u 1

L a s t

C l o c k

h 1

V

G N D

V

G N D

Figure 3

Functional Description

System Oscillator

The HT1650 system clock is used to generate the time base or Watchdog Timer (WDT) clock frequency, LCD driving clock, and tone frequency. The clock source may be from an on-chip RC oscillator (32kHz), a crystal oscil lator (32.768kHz), or an external 32kHz clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn off. That command is available only for the on-chip RC oscillator or for the crystal oscillator. Once the system clock stops, the LCD display will become blank, and the time base/WDT loses its function as well.

V a l i d D a t a

5 0 %

t

s u

t

h

5 0 %

V

G N D

D B

D D

W R , R D C l o c k

Figure 2

D D

The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by issuing the LCD OFF command, using the SYS DIS command reduces power consumption, thus serving as a system power down command. But if the external

clock source is chosen as the system clock, using the

SYS DIS command can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the case of the external 32kHz clock source operation. At the initial system power on, the HT1650 is at the SYS DIS state.

V

G N D

D D

O S C I

O S C O

C r y s t a l O s c i l l a t o r

3 2 7 6 8 H z

E x t e r n a l C l o c k S o u r c e

3 2 k H z

S y s t e m C l o c k

O n - c h i p R C O s c i l l a t o r

3 2 k H z

System Oscillator Configuration

Rev. 1.20 7 November 10, 2005

HT1650

Display Memory - RAM Structure

The static display RAM is organized into 512´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.

00H 08H 10H 18H

COM0 Bit0 Bit0 Bit0 Bit0 Bit0

COM1 Bit1 Bit1 Bit1 Bit1 Bit1

COM2 Bit2 Bit2 Bit2 Bit2 Bit2

COM3 Bit3 Bit3 Bit3 Bit3 Bit3

01H 09H 11H 19H

COM4 Bit0 Bit0 Bit0 Bit0 Bit0

COM5 Bit1 Bit1 Bit1 Bit1 Bit1

COM6 Bit2 Bit2 Bit2 Bit2 Bit2

COM7 Bit3 Bit3 Bit3 Bit3 Bit3

02H 0AH 12H 1AH

COM8 Bit0 Bit0 Bit0 Bit0 Bit0

COM9 Bit1 Bit1 Bit1 Bit1 Bit1

COM10 Bit2 Bit2 Bit2 Bit2 Bit2

COM11 Bit3 Bit3 Bit3 Bit3 Bit3

03H 0BH 13H 1BH

COM12 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0

COM13 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1

COM14 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2

COM15 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3

04H 0CH 14H 1CH

COM16 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0

COM17 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1

COM18 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2

COM19 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3

05H 0DH 15H 1DH

COM20 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0

COM21 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1

COM22 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2

COM23 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3

06H 0EH 16H 1EH

COM24 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0

COM25 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1

COM26 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2

COM27 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3

07H 0FH 17H 1FH

COM28 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0

COM29 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1

COM30 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2

COM31 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3

SEG0 SEG1 SEG2 SEG3 SEG60 SEG61 SEG62 SEG63

64´32 Selection Mode RAM Mapping Table

20H---------1D8H

21H---------1D9H

22H---------1DAH

23H---------1DBH

24H---------1DCH

25H---------1DDH

26H---------1DEH

27H---------1DFH

1E0H 1E8H 1F0H 1F8H

1E1H 1E9H 1F1H 1F9H

1E2H 1EAH 1F2H 1FAH

1E3H 1EBH 1F3H 1FBH

1E4H 1ECH 1F4H 1FCH

1E5H 1EDH 1F5H 1FDH

1E6H 1EEH 1F6H 1FEH

1E7H 1EFH 1F7H 1FFH

Rev. 1.20 8 November 10, 2005

HT1650

00H 04H 08H 0CH

COM0 Bit0 Bit0 Bit0 Bit0 Bit0

COM1 Bit1 Bit1 Bit1 Bit1 Bit1

COM2 Bit2 Bit2 Bit2 Bit2 Bit2

COM3 Bit3 Bit3 Bit3 Bit3 Bit3

01H 05H 09H 0DH

COM4 Bit0 Bit0 Bit0 Bit0 Bit0

COM5 Bit1 Bit1 Bit1 Bit1 Bit1

COM6 Bit2 Bit2 Bit2 Bit2 Bit2

COM7 Bit3 Bit3 Bit3 Bit3 Bit3

02H 06H 0AH 0EH

COM8 Bit0 Bit0 Bit0 Bit0 Bit0

COM9 Bit1 Bit1 Bit1 Bit1 Bit1

COM10 Bit2 Bit2 Bit2 Bit2 Bit2

COM11 Bit3 Bit3 Bit3 Bit3 Bit3

03H 07H 0BH 0FH

COM12 Bit0 Bit0 Bit0 Bit0 Bit0 Bit0

COM13 Bit1 Bit1 Bit1 Bit1 Bit1 Bit1

COM14 Bit2 Bit2 Bit2 Bit2 Bit2 Bit2

COM15 Bit3 Bit3 Bit3 Bit3 Bit3 Bit3

SEG0 SEG1 SEG2 SEG3 SEG76 SEG77 SEG78 SEG79

10H-------12CH

11H---------12DH

12H---------12EH

13H---------12FH

130H 134H 138H 13CH

131H 135H 139H 13DH

132H 136H 13AH 13EH

133H 137H 13BH 13FH

80´16 Selection Mode RAM Mapping Table

Name Command Code Function

80´16 Mode

The default value after power ON reset is 64´32 mode, set ²Normal² command will change 80´16 mode to 64´32 mode.

Frame Frequency

The HT1650 provides three kinds of frame frequency options by command code; 64Hz, 89Hz and 170Hz respectively. FRAME 64Hz provides 64Hz frame frequency. FRAME 89Hz provides 89Hz frame frequency. FRAME 170Hz provides 170Hz frame frequency.

Name Command Code Function

FRAME 170Hz X100-0001-1000-XXXX Select 170Hz frame frequency

FRAME 89Hz X100-0001-1101-XXXX Select 89Hz frame frequency

FRAME 64Hz X100-0001-1110-XXXX Select 64Hz frame frequency

Time Base and Watchdog Timer - WDT

The time base generator and WDT share the same counter which is divided by 256. The IRQ

1Hz, 2Hz, ...., 128Hz output. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ

Once the WDT time-out occurs, the IRQ is issued.

If an external clock is selected as the system frequency source, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed.

X100-0001-1111-XXXX Change segment from 64 to 80 and common from 32 to 16

Frame Frequency Selection Command Code

clock can be programmed as

EN/DIS are independent from each other.

pin will remain at a logic low level until the CLR WDT or the IRQ DIS command

Rev. 1.20 9 November 10, 2005

HT1650

Buzzer Tone Output

A simple tone generator is implemented in the HT1650. The tone generator can output a pair of differential driv ing signalson the BZ and BZ

which areused to generate

a single tone.

By executing the TONE 4K and TONE 2K commands there are two tone frequency outputs selectable that can turn on the tone output. The TONE 4K and TONE 2K commands set the tone frequency to 4kHz and 2kHz, re spectively. The tone output can be turned off by invoking the TONE OFF command. The tone outputs, namely, BZ and BZ

, are a pair of differential driving outputs used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the BZ

outputs

will remain at low level.

Command Format

The HT1650 can be configured by software setting. There are two mode commands to configure the HT1650 resource and to transfer the LCD display data.

The configuration mode of the HT1650 is called com mand mode, and its command mode ID is 100. The command mode consists of a system configuration

T i m e B a s e

C l o c k S o u r c e

2 5 6

¸

command, a system frequency selection command, an LCD configuration command, a tone frequency selec tion command, a bias current selection command, a

timer/WDT setting command, and an operating com

mand. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE opera tions.

The following are the data mode ID and the command mode ID:

-

Operation Mode ID

READ Data 110

WRITE Data 101

READ-MODIFY-WRITE Data 101

COMMAND Command 100

If successive commands have been issued, the com mand mode ID can be omitted. While the system is op erating in the non-successive command or the non-successive address data mode, the CS

be set to ²1² and the previous operation mode will also

be reset. The CS

pin returns to ²0², so a new operation

mode ID should be issued first.

T I M E R E N / D I S

W D T E N / D I S

V

D D

I R Q

-

pin should

C L R T i m e r

W D T

4

¸

C L R W D T

Q

D

C K

R

I R Q E N / D I S

Time Base and WDT Configurations

Name Command Code Function

TONE OFF X100-0000-1000-XXXX Turn-off the tone output

TONE 4K X100-0001-0000-XXXX Turn-on the tone output, the tone frequency is 4kHz

TONE 2K X100-0001-0001-XXXX Turn-on the tone output, the tone frequency is 2kHz

Buzzer Tone Output Command Code

The following are the data mode ID and the command ID:

Operation Mode ID

READ Data 110

WRITE Data 101

READ-MODIFY-WRITE Data 101

COMMAND Command 100

If successivecommands have been issued, the command mode ID can be omitted. While the system isoperating in the

non-successive address data mode, the CS

The CS

pin returns to ²0², so a new operation mode ID should be issued first.

pin should be set to ²1² and the previous operation mode will also be reset.

Rev. 1.20 10 November 10, 2005

HT1650

Bias Generator

The HT1650 bias voltage belongs to the internal resistor type. It provides two kinds of bias options, namely 1/6 bias and 1/5 bias respectively. It also provides three kinds of bias current options by programming to suitably drive an LCD panel. The three kinds of bias current are large, middle, and small, respectively. Usually, large panel LCD can be excellently displayed by large bias current. Relatively, it consumes large current when LCD ON command is used. Small bias current provides low power consumption during on condition when the LCD is normally displayed. The following are the reference value table.

When the bias current for LCD is more than Large Bias Current setting. It is recommended to add external cir cuit to increase driving current.

Interfacing

Only six lines are required to interface with the HT1650. The CS

line is used to initialize the serial interface circuit and to terminate the communication between the host controller and the HT1650. If the CS

pin is set to 1, the

data and command issued between the host controller and the HT1650 are first disabled and then initialized. Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial inter face of the HT1650. The DB0~DB3 are the 4-bit parallel data input/output lines. Data to be read or written or commands to be written have to pass through the DB0~DB3 lines. The RD

line is the READ clock input. Data in the RAM areclocked out on the falling edge of the RD

signal, and the clocked out data will then appear on the DB0~DB3 lines. It is recommended that the host controller read correct data during the interval between the rising edge and the next falling edge of the RD The WR dress, and command on the DB0~DB3 lines are all

clocked into the HT1650 on the rising edge of the WR

line is the WRITE clock input. The data, ad

signal. There is an optional IRQ line to be used as an in terface between the host controller and the HT1650. The IRQ

pin can be selected as a timer output or a WDT overflow flag output by the S/W setting. The host con troller can perform the time base or the WDT function by connecting with the IRQ

pin of the HT1650.

Bias VLCD Large Bias Current Middle Bias Current Small Bias Current

3V

1/5

5V

3V

1/6

5V

165mA70mA30mA

270mA 110mA50mA

140mA55mA25mA

225mA90mA40mA

-

signal.

-

P o w e r

V L C D

( T 1 ) V 1

( T 2 ) V 2

V 3

V 4

( T 3 ) V 5

( T 4 ) V 6

V S S

1 / 5 B i a s

V R

R

V

L C D

R

Internal Resistor Type Bias Generator Configurations

Note: The voltage applied to VLCD pin must be lower than 7V

Adjust VR to fit LCD display

( T 1 ) V 1

( T 2 ) V 2

( T 3 ) V 5

( T 4 ) V 6

V S S

1 / 6 B i a s

P o w e r

V L C D

V 3

V 4

V R

R

V

L C D

R

Rev. 1.20 11 November 10, 2005

HT1650

V

L C D

V

L C D

R

T 1

R

C

T 2

B i a s

B l o c k

R

C

T 3

R

C

B i a s

B l o c k

T 4

C

R

T 0 0 0

1 / 5 B i a s

1 / 6 B i a s

Increase Driver Current Configurations

Note: The external resistors are used to increment the driving current.

And the external capacitors are used to keep the bias voltage stable.

Timing Diagrams

READ Mode (Command ID Code:110)

C S

V

T 1

T 2

T 3

T 4

T 0 0 0

V

L C D

R

2 R

R

C

W R

R D

A 3

D B 3

D B 2

D B 1

D B 0

A 8 A 7

1

0

C o m m a n d I D c o d e

( S i n g l e a d d r e s s r e a d i n g ) ( S u c c e s s i v e a d d r e s s r e a d i n g )

A 6 A 2 D 2

A 1

A 5

A 4 A 0 D 0

M e m o r y

A d d r e s s ( M A )

D 3

D 1

D a t a ( M A )

A 7 A 3 D 3 D 3

A 8

A 6 A 2 D 2 D 21D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2

A 5 A 1 D 1 D 11D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1

A 4 A 0 D 0 D 00D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0

M e m o r y

A d d r e s s ( M A )

C o m m a n d I D c o d e

D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3

D a t a ( M A + 1 0 )

D a t a ( M A + 9 )

D a t a ( M A + 8 )

D a t a ( M A + 7 )

D a t a ( M A + 6 )

D a t a ( M A + 5 )

D a t a ( M A + 4 )

D a t a ( M A + 3 )

D a t a ( M A + 2 )

D a t a ( M A + 1 )

D a t a ( M A )

D a t a ( M A + 1 2 )

D a t a ( M A + 1 1 )

D a t a ( M A + 1 5 )

D a t a ( M A + 1 4 )

D a t a ( M A + 1 3 )

Rev. 1.20 12 November 10, 2005

WRITE Mode (Command ID Code:101)

C S

W R

R D

A 8 A 7

A 3

D B 3

D 3

HT1650

A 7 A 3 D 3 D 3A 8 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3

D B 2

D B 1

D B 0

A 6 A 2 D 2

0 A 5 A 1

1 A 4 A 0 D 0

C o m m a n d I D c o d e

( S i n g l e a d d r e s s w r i t i n g ) ( S u c c e s s i v e a d d r e s s w r i t i n g )

D 1

D a t a ( M A )

M e m o r y

A d d r e s s ( M A )

A 6 A 2 D 2 D 21D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 21

A 5 A 1 D 1 D 10D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1

A 4 A 0 D 0 D 01D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0

M e m o r y

A d d r e s s ( M A )

C o m m a n d I D c o d e

READ-MODIFY-WRITE Mode (Command ID Code:101)

C S

W R

R D

D B 3

D B 2

A 8 A 7 A 3

1 A 6 A 2 D 2

D 3

D 2

A 7 A 3

A 8

A 6 A 2 D 21D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2 D 2

D a t a ( M A + 1 0 )

D a t a ( M A + 9 )

D a t a ( M A + 8 )

D a t a ( M A + 7 )

D a t a ( M A + 6 )

D a t a ( M A + 5 )

D a t a ( M A + 4 )

D a t a ( M A + 3 )

D a t a ( M A + 2 )

D a t a ( M A + 1 )

D a t a ( M A )

D 3

D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3 D 3

D a t a ( M A + 1 5 )

D a t a ( M A + 1 4 )

D a t a ( M A + 1 3 )

D a t a ( M A + 1 2 )

D a t a ( M A + 1 1 )

D B 1

D B 0

0 A 5 A 1 D 1

1 A 4 A 0 D 0

C o m m a n d I D c o d e

A d d r e s s ( M A )

D 1

D 0

D a t a ( M A )

M e m o r y

D a t a ( M A )

A 5 A 1 D 10D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1 D 1

A 4 A 0 D 01D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0 D 0

M e m o r y

A d d r e s s ( M A )

C o m m a n d I D c o d e

D a t a ( M A + 1 )

D a t a ( M A )

D a t a ( M A + 3 )

D a t a ( M A + 2 )

D a t a ( M A + 4 )

D a t a ( M A + 5 )

D a t a ( M A + 4 )

D a t a ( M A + 3 )

D a t a ( M A + 5 )

D a t a ( M A + 6 )

( S i n g l e a d d r e s s a c c e s s i n g ) ( S u c c e s s i v e a d d r e s s a c c e s s i n g )

Rev. 1.20 13 November 10, 2005

Command Mode (Command ID Code:100)

C S

W R

R D

HT1650

D B 3

D B 2

D B 1

D B 0

X C 7 C 3 C 0

1 C 6 C 2 X

0 C 5 C 1 X

C 4 C 0 X

0

C o m m a n d I D c o d e

C o m m a n d

( S i n g l e c o m m a n d )

Note: ²X² stands for don¢t care

Application Circuits

Host Controller With an HT1650 Display System

*

M C U

*

R

C l o c k O u t

C 7 C 3 X C 7 C 3 X

X

C 6 C 2 X C 6 C 2 X

1

C 5 C 1 X C 5 C 1 X

0

C 4 C 0 X C 4 C 0 X

0

C o m m a n d 1

C o m m a n d I D c o d e

C S

R D

W R

D B 0 ~ D B 3

I R Q

O S C I

O S C O

C 7 C 3 X C 7 C 3 X C 7 C 3 X C 7 C 3

C 6 C 2 X C 6 C 2 X C 6 C 2 X C 6 C 2

C 5 C 1 X C 5 C 1 X C 5 C 1 X C 5 C 1

C 4 C 0 X C 4 C 0 X C 4 C 0 X C 4 C 0

C o m m a n d 2

( S u c c e s s i v e c o m m a n d )

C o m m a n d 3

C o m m a n d 4

H T 1 6 5 0

C O M 0 ~ C O M 3 1 S E G 0 ~ S E G 6 3

C o m m a n d 5

V L C D

X

C o m m a n d 6

M a x .

7 V

*

V R

B Z

P i e z o

B Z

E x t e r n a l C l o c k 1 ( 3 2 k H z )

E x t e r n a l C l o c k 2 ( 3 2 k H z )

O n - c h i p O S C

* 1 / 6 B i a s o r 1 / 5 B i a s ,

1 / 3 2 D u t y o r 1 / 1 6 D u t y

* L C D P a n e l

C r y s t a l

3 2 7 6 8 H z

The connection of IRQ

*Note:

Adjust VR to fit LCD display

Adjust R (external pull-high resistance) to fit user¢s time base clock.

It is recommended that the internal equivalent capacitance between SEG and COM of LCD panel should be lower than 10pF. (LCR meter test condition: frequency in 1KHz)

Rev. 1.20 14 November 10, 2005

and RD pin can be selected depending on the MCU.

HT1650

Instruction Set Summary

Name Command Code D/C Function Def.

READ A8110-A7A6A5A4A3A2A1A0D3D2D1D0 D Read data from the RAM

WRITE A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D Write data to the RAM

READ-MODIFYWRITE

SYS DIS X100-0000-0000-XXXX C

SYS EN X100-0000-0001-XXXX C Turn On system oscillator

LCD OFF X100-0000-0010-XXXX C Turn Off LCD display Yes

LCD ON X100-0000-0011-XXXX C Turn On LCD display

TIMER DIS X100-0000-0100-XXXX C Disable time base output Yes

WDT DIS X100-0000-0101-XXXX C Disable WDT time-out flag output Yes

TIMER EN X100-0000-0110-XXXX C Enable time base output

WDT EN X100-0000-0111-XXXX C Enable WDT time-out flag output

TONE OFF X100-0000-1000-XXXX C Turn Off tone outputs Yes

CLR TIMER X100-0000-1101-XXXX C Clear the contents of the time base generator

CLR WDT X100-0000-1111-XXXX C Clear the contents of the WDT stage

TONE 4K X100-0001-0000-XXXX C

TONE 2K X100-0001-0001-XXXX C

IRQ DIS X100-0001-0010-XXXX C Disable IRQ

IRQ EN X100-0001-0011-XXXX C Enable IRQ

RC 32K X100-0001-0100-XXXX C System clock source, on-chip RC oscillator Yes

EXT (X¢TAL)

LARGE BIAS X100-0001-0110-XXXX C Large bias current option Yes

MIDDLE BIAS X100-0001-0111-XXXX C Middle bias current option

SMALL BIAS X100-0001-1000-XXXX C Small bias current option

BIAS 1/6 X100-0001-1010-XXXX C LCD 1/6 bias option Yes

BIAS 1/5 X100-0001-1001-XXXX C LCD 1/5 bias option

FRAME 170Hz X100-0001-1100-XXXX C Selects 170Hz frame frequency

FRAME 89Hz X100-0001-1101-XXXX C Selects 89Hz frame frequency

FRAME 64Hz X100-0001-1110-XXXX C Selects 64Hz frame frequency Yes

Select 80´16

F1 X100-1010-0000-XXXX C

F2 X100-1010-0001-XXXX C

F4 X100-1010-0010-XXXX C

A8101-A7A6A5A4A3A2A1A0D3D2D1D0 D Read from and Write data to the RAM

Turn Off both system oscillator and LCD bias generator

Turn on tone output, tone frequency output: 4kHz

Turn on tone output, tone frequency output: 2kHz

output Yes

output

X100-0001-0101-XXXX C

X100-0001-1111-XXXX C

System clock source, external 32kHz clock source or crystal oscillator 32.768kHz

This command will change segment from 64 to 80 and command from 32 to 16

Time base clock output: 1Hz The WDT time-out flag after 4s

Time base clock output: 2Hz The WDT time-out flag after 2s

Time base clock output: 4Hz The WDT time-out flag after 1s

Yes

Rev. 1.20 15 November 10, 2005

Name Command Code D/C Function Def.

F8 X100-1010-0011-XXXX C

F16 X100-1010-0100-XXXX C

F32 X100-1010-0101-XXXX C

F64 X100-1010-0110-XXXX C

F128 X100-1010-0111-XXXX C

TEST X100-1111-1111-XXXX C Test mode, not for use by the user

NORMAL X100-1111-1110-XXXX C

Note:

²X² stands for don¢t care

A8~A0: RAM address

D3~D0: RAM data

D/C: Data/Command mode

Def.: Power-on reset default

All the bold forms, namely, 110, 101, and 100, are mode commands. Of these, 100indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The tone frequency source and the time base or WDT clock frequency source can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1650 after power-on reset, otherwise, power on reset may fail, which in turn leads to the malfunctioning of the HT1650.

Time base clock output: 8Hz The WDT time-out flag after 1/2s

Time base clock output: 16Hz The WDT time-out flag after 1/4s

Time base clock output: 32Hz The WDT time-out flag after 1/8s

Time base clock output: 64Hz The WDT time-out flag after 1/16s

Time base clock output: 128Hz The WDT time-out flag after 1/32s

Normal mode, 64´32 mode will be set

HT1650

Yes

Rev. 1.20 16 November 10, 2005

Package Information

128-pin QFP (14´20) Outline Dimensions

1 0 2

1 0 3

A

B

HT1650

C

D

6 5

6 4

F

E

H G

I

1 2 8

1

Symbol

A 18.80

B 13.90

C 24.80

D 19.90

E

F

G 2.50

H

I

J 0.65

K 0.10

3 8

Dimensions in mm

Min. Nom. Max.

¾

0.50

0.20

¾

¾¾

¾

0.10

¾

3 9

a 0°¾7°

K

19.20

14.10

25.20

20.10

¾

3.10

3.40

¾

0.95

0.20

a

J

Rev. 1.20 17 November 10, 2005

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw

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4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline)

HT1650

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533

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The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

-

Rev. 1.20 18 November 10, 2005