Datasheet HT1627 Datasheet (Holtek Semiconductor Inc)

RAM Mapping 64´16 LCD Controller for I/O mC

Features

Operating voltage: 2.7V~5.2V

·

Built-in RC oscillator

·

1/5 bias, 1/16 duty, frame frequency is 64Hz

·

Max. 64´16 patterns, 16 commons,

·

64 segments Built-in internal resistor type bias generator

·

3-wire serial interface

·

8 kinds of time base /WDT selection

·

Time base or WDT overflow output

·

Built-in LCD display RAM

·

General Description

HT1627 is a peripheral device specially de signed for I/O type mC used to expand the dis play capability. The max. display segment of the device are 1024 patterns (64´16). It also supports serial interface, buzzer sound, Watch dog Timer or time base timer functions. The HT1627 is a memory mapping and multi-func tion LCD controller. The software configuration

HT1627

R/W address auto increment

·

Two selection buzzer frequencies

·

(2kHz/4kHz) Power down command reduces power

·

consumption Software configuration feature

·

Data mode and Command mode instructions

·

Three data accessing modes

·

VLCD pin to adjust LCD operating voltage

·

Cascade application

·

feature of the HT1627 make it suitable for mul

tiple LCD applications including LCD modules

and display subsystems. Only three lines are required for the interface between the host con troller and the HT1627. The HT162X series

have many kinds of products that match vari ous applications.

-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270

COM 448 8 8816

SEG 32 32 32 32 48 64 48

Built-in Osc.

Crystal Osc.

ÖÖ Ö ÖÖÖ Ö

ÖÖ ÖÖÖ Ö

1 April 21, 2000

16

64

16

64

Block Diagram

OSCI

CS

RD

WR

DATA

C ontrol

and Tim ing Circuit

D isplay R A M

LCD Driver/ Bias Circuit

HT1627

COM 0

COM 15

SEG 0

Pin Assignment

VDD

VSS

BZ

CS RD

WR

DATA

VSS

OSCI

VDD

VLCD

IR Q

COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8

COM 9 COM 10 COM 11 COM 12

NC NC

BZ BZ T1 T2 T3

T4

Tone Frequency

G enerator

SEG 61

SEG 60

SEG 59

SEG 63

SEG 62

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

COM 13

COM 14

SEG 58

SEG 2

SEG 0

SEG 1

COM 15

W atchdog Tim er

Tim e Base G enerator

SEG 56

SEG 55

SEG 54

SEG 57

SEG 53

H T1627

100 Q FP

SEG 3

SEG 6

SEG 4

SEG 5

SEG 7

SEG 8

and

SEG 52

SEG 48

SEG 51

SEG 50

SEG 49

SEG 9

SEG 10

SEG 11

SEG 12

SEG 63

VLCD

IR Q

SEG 47

SEG 46

SEG 45

SEG 44

81828384858687888990919293949596979899

SEG 43

80

SEG 42

79 78

NC

77

SEG 41 SEG 40

76 75

SEG 39

74

SEG 38

73

SEG 37

72

SEG 36

71

SEG 35

70

SEG 34

69

SEG 33

68

SEG 32

67

SEG 31

66

SEG 30

65

SEG 29

64

SEG 28

63

SEG 27

62

SEG 26

61

SEG 25

60

SEG 24

59

SEG 23

58

SEG 22

57

SEG 21

56

SEG 20

55

SEG 19

54

NC

53

NC

52

SEG 18

51

SEG 17

SEG 13

SEG 14

SEG 15

SEG 16

2 April 21, 2000

Pad Assignment

WR

RD

CS

HT1627

SEG 42

SEG 44

SEG 46

SEG 48

SEG 50

SEG 52

SEG 54

SEG 56

SEG 58

SEG 60

SEG 62

SEG 63

SEG 59

SEG 61

SEG 55

SEG 57

SEG 51

SEG 53

SEG 47

SEG 49

SEG 43

SEG 45

DATA

VSS

OSCI

VDD

VLCD

IR Q

BZ

T1

T2 T3

T4

COM 0

COM 1 COM 2

COM 3 COM 4

COM 5 COM 6

COM 7 COM 8

COM 9

91

90

92

9495

93

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

24

23

22

25

COM 11

COM 10

COM 12

89

88

28 29

26

27

COM 14

COM 13

COM 15

SEG 0

85

86

84

87

82

83

798081

78

(0 ,0 )

32

33

34

363738

30

31

SEG 1

SEG 2

SEG 3

35

SEG 4

SEG 5

SEG 6

SEG 7

SEG 8

40

39

SEG 9

SEG 10

SEG 11

74

73

75

7677

43 44 45

41

42

SEG 12

SEG 13

SEG 14

71

72

SEG 41

70

SEG 40

69

68

SEG 39

SEG 38

67

66

SEG 37

SEG 36

65

64

SEG 35

63

SEG 34

62

SEG 33

61

SEG 32

60

SEG 31

SEG 30

59

SEG 29

58

SEG 28

57

SEG 27

56

55

SEG 26

54

SEG 25

53

SEG 24

52

SEG 23

51

SEG 22

50

SEG 21

49

SEG 20

48

SEG 19

47

SEG 18

46

SEG 15

SEG 16

SEG 17

Chip size: 245 ´ 237 (mil)

2

* The IC substrate should be connected to VDD in the PCB layout artwork.

3 April 21, 2000

HT1627

Pad Coordinates Unit: mil

Pad No. X Y Pad No. X Y Pad No. X Y

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

-116.62

-116.71

-115.94

-116.71

-115.94

-115.94 -0.60

-115.94 -7.22

-115.94 -19.21

-115.94 -25.84

-115.94 -37.83

-115.94 -44.46

-115.94 -56.44

-115.94 -63.07

-115.94 -75.06

-115.94 -81.68

-115.94 -93.67

-115.94 -100.30

-115.94 -112.29

-108.04 -112.03

-96.05 -112.03

-89.42 -112.03

-77.43 -112.03

-70.81 -112.03

-58.82 -112.03

-52.19 -112.03

-40.21 -112.03

-33.58 -112.03

-21.59 -112.03

99.88 33

86.32 34

78.75 35 3.65

72.12 36 15.64

65.49 37 22.27

55.97 38 34.26

41.44 39 40.88

21.84 40 52.87

11.39 41 59.50 42 71.49 43 78.11 44 90.10 45 96.73 46 108.71 47 116.15 48 116.15 9.83 80 25.58 112.24 49 116.15 50 116.15 51 116.15 52 116.15 53 116.15 54 116.15 55 116.15 56 116.15 57 116.15 58 116.15 59 116.15 60 116.15 11.86 92 61 116.15 18.49 93 62 116.15 30.47 94 63 116.15 37.10 95 64 116.15 49.09

-14.96 -112.03

-2.97 -112.03

-112.03

-111.82

-93.20

-81.22

-74.59

-62.60

-55.97

-43.99

-37.36

-25.37

-18.74

-6.76

-0.13

65 116.15 55.72 66 116.15 67.70 67 116.15 74.33 68 116.15 86.32 69 116.15 92.95 70 116.15 104.93 71 112.03 112.24 72 100.04 112.24 73 93.42 112.24 74 81.43 112.24 75 74.80 112.24 76 62.81 112.24 77 56.19 112.24 78 44.20 112.24 79 37.57 112.24

81 18.95 112.24 82 6.97 112.24 83 0.34 112.24 84 85 86 87 88 89 90 91

-11.65

-18.27

-30.26

-36.89

-48.88

-55.51

-67.49

-74.12

-86.11

-92.74

-104.72

-114.24

112.24

4 April 21, 2000

Pad Description

Pad No. Pad Name I/O Description

1 DATA I/O Serial data input/output with pull-high resistor

2 VSS

3 OSCI I

4 VDD

5 VLCD I LCD operating voltage input pad.

6 IRQ

7, 8 BZ, BZ

9~12 T1~T4 I Not connected

13~28 COM0~COM15 O LCD common outputs

29~92 SEG0~SEG63 O LCD segment outputs

93 CS

94 RD

95 WR

Negative power supply, Ground

¾

If the system clock comes from an external clock source, the ex ternal clock source should be connected to the OSCI pad.

Positive power supply

¾

Time base or Watchdog Timer overflow flag, NMOS open drain

O

output

2kHz or 4kHz tone frequency output pair (Tri-state output

O

buffer)

Chip selection input with pull-high resistor. When the CS logic high, the data and command read from or write to the HT1627 are disabled. The serial interface circuit is also reset.

I

But if the CS data and command transmission between the host controller and the HT1627 are all enabled.

READ clock input with pull-high resistor. Data in the RAM of the HT1627 are clocked out on the rising edge of the RD

I

The clocked out data will appear on the data line. The host controller can use the next falling edge to latch the clocked out data.

WRITE clock input with pull-high resistor. Data on the DATA

I

line are latched into the HT1627 on the rising edge of the WR signal.

is at logic low level and is input to the CS pad, the

HT1627

-

is

signal.

Absolute Maximum Ratings

Supply Voltage..............................-0.3V to 5.5V

Input Voltage ................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this de vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

SS

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto75°C

5 April 21, 2000

-

HT1627

D.C. Characteristics

Symbol Parameter

V

I

V

I

R

DD

DD1

DD2

STB

IL

IH

OL1

OH1

OL2

OH2

OL3

OH3

OL4

OH4

PH

Operating Voltage

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

BZ, BZ, IRQ

BZ, BZ

DATA

LCD Common Sink Current

LCD Common Source Current

LCD Segment Sink Current

LCD Segment Source Current

Pull-high Resistor

Test Conditions

Min. Typ. Max. Unit

V

DD

¾¾

3V

5V

3V

5V

3V

5V

3V

Conditions

No load/LCD ON On-chip RC oscillator

No load/LCD OFF On-chip RC oscillator

No load Power down mode

2.7

¾

0

¾

200 315

300 425

15 55

30 85

214

428

¾

DATA, WR,CS,RD

5V 0

3V

2.4

¾

DATA, WR,CS,RD

5V 4.0

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

-0.9 -1.8 ¾

-1.7 -3 ¾

-0.9 -1.8 ¾

-1.7 -3 ¾

180 360

-40 -80 ¾mA

-90 -180 ¾mA

120 240

-30 -60 ¾mA

-70 -140 ¾mA

100 200 300

¾

0.9 1.8

1.7 3

0.9 1.8

1.7 3

80 160

50 100

DATA, WR,CS,RD

5V 50 100 150

Ta=25°C

5.2 V

mA

0.6 V

1.0 V

3V

5V

mA

¾

mA

¾

mA

¾

mA

¾

mA

¾mA

kW

6 April 21, 2000

HT1627

A.C. Characteristics

Symbol Parameter

f

SYS1

f

SYS2

f

LCD1

f

LCD2

t

COM

f

CLK1

f

CLK2

t

CS

t

CLK

t

r,tf

t

su

t

h

t

su1

t

h1

System Clock 3V On-chip RC oscillator 22 32 40 kHz

System Clock

LCD Frame Frequency

LCD Common Period

Serial Data Clock (WR Pin)

Serial Data Clock (RD Pin)

Serial Interface Reset Pulse Width (Figure 3)

WR,RDInput Pulse Width

Rise/Fall Time Serial Data Clock Width (Figure 1)

Setup Time for DATA to WR, RD

Clock Width (Figure 2)

Hold Time for DATA to WR, RD

Clock Width (Figure 2)

Setup Time for CS to WR,

RD

Clock Width (Figure 3)

Hold Time for CS to WR,RD Clock Width (Figure 3)

(Figure 1)

Ta=25°C

Test Conditions

Min. Typ. Max. Unit

V

DD

Conditions

5V 24 32 40 kHz

3V

¾

32

¾

kHz

External clock source

5V

3V

44 64 80 Hz

¾

32

¾

kHz

On-chip RC oscillator

5V 48 64 80 Hz

3V

¾

64

¾

External clock source

5V

n: Number of COM

¾

3V

64

¾

n/f

¾

LCD

¾¾

¾

150 kHz

Duty cycle 50%

5V

3V

¾¾

300 kHz

75 kHz

Duty cycle 50%

5V

CS

¾

Write mode 3.34

¾¾

¾

150 kHz

250

¾

¾¾

3V

Read mode 6.67

Write mode 1.67

¾¾

5V

Read mode 3.34

¾¾

3V

¾¾

120

¾

5V

3V

¾¾

120

¾

5V

3V

¾¾

120

¾

5V

3V

¾¾

100

¾

5V

3V

¾¾

100

¾

5V

Hz

sec

ns

ms

ns

7 April 21, 2000

HT1627

W R , R D Clock

90%

50%

10%

t

f

t

CLK

t

r

t

CLK

Figure 1

t

CS

W R , R D Clock

50%

FIR ST

Clock

50%

t

LAS T Clock

h1

t

su1

Figure 3

Functional Description

Display memory - RAM structure

The static display RAM is organized into 256*4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns.

COM 12COM 13COM 14COM 15

VALID DATA

V

DD

GND

DB

W R , R D Clock

50%

t

h

t

su

Figure 2

V

DD

GND

V

DD

GND

Time base and Watchdog Timer - WDT

The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR , WDT DIS/EN/CLR and IRQ

EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ

pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued.

COM 0COM 1COM 2COM 3

V

DD

GND

V

DD

GND

SEG 0

SEG 1

SEG 2

SEG 3

SEG 63

D3 D2 D1 D0

3

7

11

15

255

Addr

Data

D a ta 4 B its

(D 3, D 2, D 1, D 0)

RAM mapping

0

4

8

Address 8 B its

12

(A 7 , A 6 , ...., A 0 )

252

D3 D2 D1 D0

Addr

Data

8 April 21, 2000

HT1627

Tim e B ase

C lock S o urce

/256

CLR Tim er

WDT

/4

CLR W DT

Timer and WDT configurations

If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is re moved.

Buzzer tone output

A simple tone generator is implemented in the HT1627. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone.

Command format

The HT1627 can be configured by the software setting. There are two mode commands to configure the HT1627 resource and to transfer the LCD display data.

T IM E R E N /D IS

WDT EN/DIS

V

DD

D

CK

Q

IR Q E N /D IS

R

IR Q

The following are the data mode ID and the command mode ID:

-

Operation Mode ID

READ Data 1 1 0

WRITE Data 1 0 1

READ-MODIFY-WRITE Data 1 0 1

COMMAND Command 1 0 0

If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode,

pin should be set to ²1² and the previous

the CS operation mode will be reset also. The CS returns to ²0², a new operation mode ID should be issued first.

Name Command Code Function

TONE OFF 0000-1000-X Turn-off tone output

TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz

TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz

9 April 21, 2000

Timing Diagrams

READ mode (command code:110)

CS

WR

RD

HT1627

DATA

0A7

1

A5A4A3

A6 A1 A0 D0 D1

M em ory A ddress 1 (M A1) Data (M A2)

A2

D ata (M A 1) M em ory A ddress 2 (M A2)

READ mode (successive address reading)

CS

WR

RD

0

DATA

1

A7A6A5A4A3

1

M em ory A ddress (M A )

A1 A0 D 0 D1

A2

D2 D3

Data (MA)

0

A7

A5A4A3

1

D2 D3

1

D0 D1

A6

D2 D3

D0 D1

D ata (M A+ 1) D ata (M A +2) D ata (M A +3)

A1 A0 D 0 D1

A2

D2 D3

D0 D1

D2 D3

D0

10 April 21, 2000

WRITE mode (command code:101)

CS

WR

HT1627

DATA

1A7

1

0

A5A4A3

A6 A1 A0 D0 D1

M em ory A ddress 1 (M A 1)

A2

WRITE mode (successive address writing)

CS

WR

1

DATA

1

A7A6A5A4A3

0

M em ory A ddress (M A )

A1 A0 D 0 D1

A2

D2 D3

Data (M A1)

D2 D3

Data (MA)

1

A7

0

D0 D1

Data (MA+1)

A5A4A3

A6

M em ory A ddress 2 (M A 2)

D2 D3

D0 D1

Data (MA+2)

D2 D3

A1 A0 D 0 D1

A2

D0 D1

Data (M A2)

D2 D3

Data (MA+3)

D2 D3

D0

11 April 21, 2000

READ-MODIFY-WRITE mode (command code;101)

CS

WR

RD

HT1627

DATA

1

0

1A6

A7 A1 A0 D0 D1

A4A5A2

M em ory A ddress 1 (M A1) D ata (M A 1)

A3

D2 D3

D0 D1

Data (M A1)

D2 D3

READ-MODIFY-WRITE mode (successive address accessing)

CS

WR

RD

DATA

1

0

A6A7A4A5A2

M em ory A ddress (M A) D ata (M A )

A3

A1 A0 D0 D1

D2 D3

D0 D1

D ata (M A ) D ata (M A +1) Data (M A+1)

1

D0 D1

A6

A7

1

0

M em ory A ddress 2 (M A2) Data (M A 2)

D2 D3

D0 D1

D2 D3

A1 A0 D0 D1

D0

D2 D3

D1

Data (MA+2)

D2 D3

D0

12 April 21, 2000

Command mode (command code:100)

CS

WR

HT1627

DATA

1

0

0C8C7C6 C5

C4 C3 C2 C1

C om m and 1

Mode (data and command mode)

CS

WR

DATA

RD

C om m and

or

D ata M ode

Address and D ata

C0

C om m and

or

D ata M ode

C8C7C6 C5

C om m and iC om m and... C om m and

Address and D ata

C4 C3 C2 C1

C0

C om m and

or

D ata M ode

or

D ata M ode

Address and D ata

13 April 21, 2000

Application Circuits

HT1627

*Note:

CS

*

RD

m

C

WR

DATA

*

R

IR Q

COM 0~COM15

H T1627

SEG0~SEG63

1 /5 B ia s , 1 /1 6 D u ty

VDD

VLCD

BZ

LC D Panel

The connection of IRQ

The voltage applied to V

Adjust VR to fit LCD display, at V

and RD pin can be selected depending on the requirement of the mC.

pin must be lower than VDD.

LCD

DD

=5V, V

=4V, VR=15kW±20%.

LCD

Adjust R (external pull-high resistance) to fit user¢s time base clock.

*

VR

Piezo

14 April 21, 2000

Instruction Set Summary

Name ID Command Code D/C Function Def.

READ

WRITE

READMODIFYWRITE

SYS DIS

SYS EN

LCD OFF

LCD ON

TIMER DIS

WDT DIS

TIMER EN

WDT EN

TONE OFF

CLR TIMER

CLR WDT

RC 32K

EXT 32K

TONE 4K

TONE 2K

DIS

IRQ

EN

IRQ

F1

F2

F4

A7A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM

110

A7A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM

101

A7A6A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM

101

0000-0000-X C

100

0000-0001-X C Turn on system oscillator

100

0000-0010-X C Turn off LCD display Yes

100

0000-0011-X C Turn on LCD display

100

0000-0100-X C Disable time base output Yes

100

0000-0101-X C Disable WDT time-out flag output Yes

100

0000-0110-X C Enable time base output

100

0000-0111-X C Enable WDT time-out flag output

100

0000-1000-X C Turn off tone outputs Yes

100

0000-1101-X C

100

0000-1111-X C Clear the contents of the WDT stage

100

0001-10XX-X C

100

0001-11XX-X C

100

010X-XXXX-X C Tone frequency output: 4kHz

100

0110-XXXX-X C Tone frequency output: 2kHz

100

100X-0XXX-X C Disable IRQ output Yes

100

100X-1XXX-X C Enable IRQ output

100

101X-0000-X C

100

101X-0001-X C

100

101X-0010-X C

100

Turn off both system oscillator

and LCD bias generator

Clear the contents of the time base generator

System clock source, on-chip RC oscillator

System clock source, external clock source

Time base clock output: 1Hz The WDT time-out flag after: 4s

Time base clock output: 2Hz The WDT time-out flag after: 2s

Time base clock output: 4Hz The WDT time-out flag after: 1s

HT1627

Yes

15 April 21, 2000

Name ID Command Code D/C Function Def.

F8

F16

F32

F64

F128

TEST

NORMAL

Note:

X : Don¢t care

A7~A0 : RAM address

D3~D0 : RAM data

D/C : Data/Command mode

Def. : Power on reset default

All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1627 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1627.

101X-0011-X C

100

101X-0100-X C

100

101X-0101-X C

100

101X-0110-X C

100

101X-0111-X C

100

1110-0000-X C

100

1110-0011-X C Normal mode Yes

100

Time base clock output: 8Hz The WDT time-out flag after: 1/2 s

Time base clock output: 16Hz The WDT time-out flag after: 1/4 s

Time base clock output: 32Hz The WDT time-out flag after: 1/8 s

Time base clock output: 64Hz The WDT time-out flag after: 1/16 s

Time base clock output: 128Hz The WDT time-out flag after: 1/32 s

Test mode, user don¢t use.

HT1627

Yes

16 April 21, 2000

HT1627

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

17 April 21, 2000

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