Datasheet HD74ACT374, HD74AC374 Datasheet (HIT)

Page 1
HD74AC374/HD74ACT374
Octal D-Type Flip-Flops with 3-State Output
Description
The HD74AC374/HD74ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D­type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
Buffered Positive Edge-Triggered Clock
Outputs Source/Sink 24 mA
See HD74AC273/HD74ACT273 for Reset Version
See HD74AC373/HD74ACT373 for Transparent Latch Version
See HD74AC574/HD74ACT574 for Broadside Pinout Version
See HD74AC564/HD74ACT564 for Broadside
Pinout Version with Inverted Outputs
HD74ACT374 has TTL-Compatible Inputs
Page 2
HD74AC374/HD74ACT374
Pin Arrangement
1
OE
20
V
CC
Logic Symbol
2
0
O
D0
3
D1
4
O1
5
O2
6
7
D2
D3
8
O3
9
10 11
Gnd
(Top view)
19
18
17
16
15
14
13
12
O7
D7
D6
O6
O5
D
D4
O4
CP
5
Pin Names
D0 – D7Data Inputs CP Clock Pulse Input OE 3-State Output Enable Input O0 – O73-State Outputs
2
D
0 D2
CP OE
O0 O2
D1
O1
D3
D4 D6
O3
O4 O6
D5 D7
O5 O7
Page 3
HD74AC374/HD74ACT374
Functional Description
The HD74AC374/HD74ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the Low-to-High Clock (CP) transition. With the Output Enable (OE) Low, the contents of the eight flip-flops are available at the outputs. When the OE is High, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Truth Table
Inputs Outputs D
n
H LH L LL XX H Z
H : High Voltage Level L : Low Voltage Level X : Immaterial Z : High Impedance
: Low-to-High Transition
CP OE O
n
Logic Diagram
D6
CP
D
QQ
O6
CP
OE
D0
CP
D
QQ
O0
D1
CP
D
QQ
O1
D2
CP
D
QQ
O2
D3
CP
D
QQ
O3
D4
CP
D
QQ
O4
D5
CP
D
QQ
O5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
D7
CP
D
QQ
O7
3
Page 4
HD74AC374/HD74ACT374
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
Maximum ICC/input (HD74ACT374) I
CC
CC
CCT
AC Characteristics: HD74AC374
80 µAV
8.0 µAV
1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V,
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
Item Symbol V
Maximum clock f
max
Ta = +25°C C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
3.3 60 110 60 MHz
Ta = –40°C to +85°C CL = 50 pF
frequency 5.0 100 155 100 — Propagation delay t CP to O
n
Propagation delay t CP to O
n
Output enable time t
PLH
PHL
PZH
3.3 1.0 11.0 13.5 1.0 15.5 ns
5.0 1.0 8.0 9.5 1.0 10.5
3.3 1.0 10.0 12.5 1.0 14.0 ns
5.0 1.0 7.0 9.0 1.0 10.0
3.3 1.0 9.5 11.5 1.0 13.0 ns
5.0 1.0 7.0 8.5 1.0 9.5
Output enable time t
PZL
3.3 1.0 9.0 11.5 1.0 13.0 ns
5.0 1.0 6.5 8.5 1.0 9.5
Output disable time t
PHZ
3.3 1.0 10.5 12.5 1.0 14.5 ns
5.0 1.0 8.0 11.0 1.0 12.5
Output disable time t
PLZ
3.3 1.0 8.0 11.5 1.0 12.5 ns
5.0 1.0 6.5 8.5 1.0 10.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
4
Page 5
HD74AC374/HD74ACT374
AC Operating Requirements: HD74AC374
Ta = –40°C
Ta = +25°C C
= 50 pF
L
Item Symbol V
Setup time, HIGH or LOW t
su
(V)*1Typ Guaranteed Minimum Unit
CC
3.3 2.0 5.5 6.0 ns Dn to CP 5.0 1.0 4.0 4.5 Hold time, HIGH or LOW t
h
3.3 –1.0 1.0 1.0 ns Dn to CP 5.0 –4.0 1.5 1.5 CP pulse width, HIGH or LOW t
w
3.3 4.0 5.5 6.0 ns
5.0 2.5 4.0 4.5 Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT374
to +85°C CL = 50 pF
Item Symbol V
Maximum clock
f
max
(V)*1Min Typ Max Min Max Unit
CC
5.0 100 160 90 MHz
frequency Propagation delay
CP to O
n
Propagation delay CP to O
n
Output enable time t Output enable time t Output disable time t Output disable time t
t
PLH
t
PHL
PZH
PZL
PHZ
PLZ
5.0 1.0 8.5 10.0 1.0 11.5 ns
5.0 1.0 8.0 9.5 1.0 11.0 ns
5.0 1.0 8.0 9.5 1.0 10.5 ns
5.0 1.0 8.0 9.0 1.0 10.5 ns
5.0 1.0 8.5 11.5 1.0 12.5 ns
5.0 1.0 7.0 8.5 1.0 10.0 ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = +25°C C
= 50 pF
L
Ta = –40°C to +85°C CL = 50 pF
5
Page 6
HD74AC374/HD74ACT374
AC Operating Requirements: HD74ACT374
Ta = –40°C
Ta = +25°C C
= 50 pF
L
Item Symbol V
Setup time, HIGH or LOW D
to CP
n
Hold time, HIGH or LOW D
to CP
n
CP pulse width, HIGH or LOW t
t
su
t
h
w
(V)*1Typ Guaranteed Minimum Unit
CC
5.0 1.0 7.0 5.5 ns
5.0 0.0 1.5 1.5 ns
5.0 2.0 7.0 5.0 ns Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitance C Power dissipation capacitance C
IN
PD
4.5 pF VCC = 5.5 V
80.0 pF VCC = 5.0 V
to +85°C CL = 50 pF
6
Page 7
24.50
25.40 Max
Unit: mm
1120
6.30
1
0.89
1.27 Max
2.54 ± 0.25
1.30
10
0.48 ± 0.10
7.00 Max
0.51 Min
2.54 Min 5.08 Max
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.11
0.25
– 0.05
0° – 15°
(reference value)
DP-20N — Conforms
1.26 g
Page 8
20
Unit: mm
12.6
13 Max
11
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
10
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code JEDEC EIAJ Weight
(reference value)
+ 0.20 – 0.30
1.15
0° – 8°
FP-20DA — Conforms
0.31 g
Page 9
20
Unit: mm
12.8
13.2 Max 11
7.50
1
0.935 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
10
0.12
0.20 ± 0.10
0.15
2.65 Max
M
10.40
0.25 ± 0.04
*0.27 ± 0.05
0.70
Hitachi Code JEDEC EIAJ Weight
+ 0.25 – 0.40
1.45
+ 0.57 – 0.30
(reference value)
0° – 8°
FP-20DB Conforms —
0.52 g
Page 10
20 11
110
+0.08
*0.22
–0.07
0.20 ± 0.06
6.50
6.80 Max
0.65 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code JEDEC EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-20DA — —
0.07 g
Page 11
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