Page 1
HD74AC182/HD74ACT182
Carry Lookhead Generator
Description
The HD74AC182/HD74ACT182 is a high-speed carry lookahead generator. It is generally used with the
HD74AC181 or HD74AC381 4-bit arithmetic logic unit to provide high-speed lookahead over word
lengths of more than four bits.
Features
• Outputs Source/Sink 24 mA
• HD74ACT182 has TTL-Compatible Inputs
Pin Arrangement
G
P1
G0
P0
G3
P
GND
1
1
2
3
4
5
3
6
7
P
8
(Top view)
16
15
14
13
12
11
10
CC
V
P2
G2
Cn
Cn+X
Cn+y
G
9
n+z
C
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HD74AC182/HD74ACT182
Logic Symbol
P
0
G0 P1 G1
Cn
Cn+x Cn+y Cn+z
Pin Names
Cn Carry Input
G0, G
2
G
1
G
3
P0, P
1
P
2
P
3
C
to C
n + x
n + z
G Carry Generate Output (Active Low)
P Carry Propagate Output (Active Low)
Carry Generate Inputs (Active Low)
Carry Generate Input (Active Low)
Carry Generate Input (Active Low)
Carry Propagate Inputs (Active Low)
Carry Propagate Input (Active Low)
Carry Propagate Input (Active Low)
Carry Outputs
P2 G2
P3 G3
G
P
2
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Logic Diagram
Cn
G0 P0 G1
HD74AC182/HD74ACT182
P1 G2P2 G3P3
Cn+x Cn+y Cn+z
GP
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Functional Description
The HD74AC182/HD74ACT182 carry lookahead generator accepts up to four pairs of Active Low Carry
Propagate (P0 to P3) and Carry Generate (G0 to G3) signals and an Active High Carry input (Cn) and
provides anticipated Active High carries (C
HD74AC182/HD74ACT182 also has Active Low Carry Propagate ( P) and Carry Generate (G) outputs
which may be used for further level of lookahead. The logic equations provided at the outputs are:
C
= G0 + P0C
n + x
C
= G1 + P1G0 + P1P0C
n + y
C
= G2 + P2G1 + P2P1G0 + P2P1P0C
n + z
G= G3 + P3G2 + P3P2G1 + P3P2P1G
P= P3P2P1P
n
n
n
0
0
Also, the HD74AC182/HD74ACT182 can be used with binary ALUs in an active Low or active High input
operand mode. The connections (Figure a) to and from the ALU to the carry lookahead generator are
identical in both cases. Carries are rippled between lookahead blocks. The critical speed path follows the
circled numbers. There are several possible arrangements for the carry interconnects, but all achieve about
the same speed. A 28-bit ALU is formed by dropping the last HD74AC182/HD74ACT182.
n + x
, C
n + y
, C
) across four groups of binary adders. The
n + z
3
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HD74AC182/HD74ACT182
Truth Table
Inputs Outputs
G
C
n
XH H L
LH X L
XL X H
HX L H
XXXHH L
XHHHX L
LH X H X L
XXXLX H
XL X X L H
HX L X L H
XXXXXHH L
XXXHHHX L
XHHHXHX L
LHXHXHX L
XXXXXLX H
XXXLXXL H
XL X X L X L H
HXLXLXL H
X XXXXHH H
XXXHHHX H
X HHHXHX H
HHXHXHX H
X XXXXLX L
XXXLXXL L
X LXXLXL L
LXLXLXL L
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
P
0
G
0
P
1
G
1
P
2
G
2
P
3
C
3
n + xCn + y
C
GP
n + z
HXXX H
XHXX H
XXHX H
XXXH H
LLLL L
4
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HD74AC182/HD74ACT182
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
Maximum ICC/input (HD74ACT182) I
CC
CC
CCT
AC Characteristics: HD74AC182
80 µAV
8.0 µAV
1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V,
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
Item Symbol V
Propagation delay t
PLH
Ta = +25°C
C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
3.3 1.0 8.0 10.5 1.0 11.5 ns
Ta = –40°C to +85°C
CL = 50 pF
Pn to P 5.0 1.0 5.5 8.0 1.0 9.0
Propagation delay t
PHL
3.3 1.0 8.0 10.5 1.0 11.5 ns
Pn to P 5.0 1.0 5.5 8.0 1.0 9.0
Propagation delay t
Cn to C
n + x, y, z
Propagation delay t
Cn to C
n + x, y, z
Propagation delay t
Pn or Gn to C
n + x, y, z
Propagation delay t
Pn or Gn to C
n + x, y, z
PLH
PHL
PLH
PHL
3.3 1.0 9.5 12.0 1.0 13.0 ns
5.0 1.0 7.5 10.0 1.0 11.0
3.3 1.0 9.0 12.0 1.0 13.0 ns
5.0 1.0 7.0 10.0 1.0 11.0
3.3 1.0 10.5 13.0 1.0 14.0 ns
5.0 1.0 8.0 10.5 1.0 11.5
3.3 1.0 11.5 14.0 1.0 15.5 ns
5.0 1.0 9.0 11.5 1.0 12.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
5
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HD74AC182/HD74ACT182
AC Characteristics: HD74ACT182
Item Symbol V
Propagation delay
P
to P
n
Propagation delay
P
to P
n
Propagation delay
C
to C
n
n + x, y, z
Propagation delay
C
to C
n
n + x, y, z
Propagation delay
P
or Gn to C
n
n + x, y, z
Propagation delay
P
or Gn to C
n
n + x, y, z
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Ta = +25°C
C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
5.0 1.0 7.0 9.0 1.0 10.0 ns
5.0 1.0 8.0 10.0 1.0 11.0 ns
5.0 1.0 9.0 11.0 1.0 12.0 ns
5.0 1.0 9.0 11.0 1.0 12.0 ns
5.0 1.0 9.0 11.0 1.0 12.0 ns
5.0 1.0 10.0 12.5 1.0 13.5 ns
Ta = –40°C to +85°C
CL = 50 pF
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitance C
Power dissipation capacitance C
IN
PD
4.5 pF VCC = 5.5 V
50.0 pF VCC = 5.0 V
6
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19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code
JEDEC
EIAJ
Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16
Conforms
Conforms
1.07 g
Page 8
16
Unit: mm
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
+ 0.20
– 0.30
1.15
0° – 8°
FP-16DA
—
Conforms
0.24 g
Page 9
16
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Page 10
16 9
18
+ 0.08
*0.22
– 0.07
0.20 ± 0.06
5.00
5.30 Max
0.65 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
Page 11
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
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products.
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