Page 1
HD74AC165/HD74ACT165
Parallel-Load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from QA to QH when clocked, Parallel inputs to each stage are
enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
• Outputs Source/Sink 24 mA
• HD74ACT165 has TTL-Compatible Inputs
Page 2
HD74AC165/HD74ACT165
Pin Arrangement
L
S
CP
1
2
16
15
V
CC
Clock
Inhibit
Logic Symbol
Parallel
Inputs
1
2
10
3
E
4
F
5
G
H
6
H
Q
7
89
GND
(Top view)
15 11 12 13 14 3 4
Clock
Inhibit
S
L
CP
SI
A
BCDEFGH
14
13
12
11
10
H QH
Q
D
C
B
A
SI
QH
56
Parallel
Inputs
Pin Names
A to H Parallel Inputs
S
I
CP Clock Input
S
L
Clock Inhibit Clock Inhibit
QH, Q
H
2
Serial Input
Shift Load
Outputs
97
Page 3
HD74AC165/HD74ACT165
Truth Table
Inputs
Clock Parallel Internal Outputs Outputs
S
L
L X X X a ······ h a b h
HLLXXQ
HL HXHQAnQ
HL LXLQAnQ
HHXXXQ
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
: Low-to-High Clock Transition
Inhibit CP S
I
A ······ H Q
A
AD
AD
Q
B
Q
BO
Q
BO
Q
H
Q
HO
Gn
Cn
Q
HO
3
Page 4
HD74AC165/HD74ACT165
Logic Diagram
Parallel
Inputs
A
Preset
Q
A
S
Clock
QA
R
Clear
SI SL CP Clock
Preset
S
Clock
R
Clear
B
Preset
Q
B
S
Clock
QB
R
Clear
Inhibit
C
Q
C
QC
Preset
S
Clock
R
Clear
D
Q
D
QD
Preset
S
Clock
R
Clear
E
Q
E
QE
Preset
S
Clock
R
Clear
F
Q
F
QF
Preset
S
Clock
R
Clear
G
Q
G
QG
Preset
S
Clock
R
Clear
H
Q
QH
H
Output
H
Q
Output
H
Q
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
Maximum additional ICC/input
(HD74ACT165)
4
CC
CC
I
CCT
80 µAV
8.0 µAV
1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V,
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
Page 5
AC Characteristics: HD74AC165
HD74AC165/HD74ACT165
Item Symbol V
Maximum count f
max
Ta = +25°C
C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
3.3 85 — — 70 — MHz
Ta = –40°C to +85°C
CL = 50 pF
frequency 5.0 100 — — 90 —
Propagation delay t
CP to QH or Q
H
Propagation delay t
CP to QH or Q
H
Propagation delay t
H to QH or Q
H
Propagation delay t
H to QH or Q
H
Propagation delay t
SL to QH or Q
H
Propagation delay t
SL to QH or Q
H
PLH
PHL
PLH
PHL
PLH
PHL
3.3 1.0 11.0 17.5 1.0 20.5 ns
5.0 1.0 8.0 11.5 1.0 13.5
3.3 1.0 12.0 18.0 1.0 21.5 ns
5.0 1.0 8.5 12.5 1.0 14.5
3.3 1.0 13.5 19.5 1.0 22.5 ns
5.0 1.0 9.5 13.5 1.0 15.5
3.3 1.0 9.0 14.0 1.0 16.5 ns
5.0 1.0 6.5 9.5 1.0 11.0
3.3 1.0 11.5 20.5 1.0 23.5 ns
5.0 1.0 8.5 14.0 1.0 16.0
3.3 1.0 10.0 16.5 1.0 19.5 ns
5.0 1.0 7.5 11.0 1.0 12.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
5
Page 6
HD74AC165/HD74ACT165
AC Operating Requirements: HD74AC165
Ta = –40°C
Ta = +25°C
C
= 50 pF
L
Item Symbol V
Setup time, HIGH or LOW t
H to S
L
Hold time, HIGH or LOW t
H to S
L
Setup time, HIGH or LOW t
su
h
su
(V)*1Typ Guaranteed Minimum Unit
CC
3.3 3.5 5.0 6.0 ns
5.0 2.5 4.0 4.5
3.3 –1.0 0.5 0.5 ns
5.0 –0.5 0.5 0.5
3.3 1.0 3.5 4.0 ns
Sin to CP 5.0 0.5 3.0 3.5
Hold time, HIGH or LOW t
h
3.3 1.5 2.0 2.0 ns
Sin to CP 5.0 1.0 2.0 2.0
Setup time, HIGH or LOW t
su
3.3 3.0 5.0 6.0 ns
SL to CP 5.0 2.0 4.0 4.5
Hold time, HIGH or LOW t
h
3.3 –2.0 0.0 0.0 ns
SL to CP 5.0 –1.0 0.0 0.0
Recovery time clock inhibit t
rec
3.3 2.5 3.5 3.5 ns
to CP 5.0 2.0 3.0 3.0
Clock pulse width t
w
3.3 3.0 5.5 7.0 ns
5.0 3.0 4.5 5.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
to +85°C
CL = 50 pF
6
Page 7
AC Characteristics: HD74ACT165
HD74AC165/HD74ACT165
Item Symbol V
Maximum count
f
max
(V)*1Min Typ Max Min Max Unit
CC
5.0 7.0 — — 60 — MHz
frequency
Propagation delay
CP to Q
or Q
H
H
Propagation delay
CP to Q
or Q
H
H
Propagation delay
H to Q
or Q
H
H
Propagation delay
H to Q
or Q
H
H
Propagation delay
S
to QH or Q
L
H
Propagation delay
S
to QH or Q
L
H
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
5.0 1.0 8.5 13.5 1.0 15.5 ns
5.0 1.0 9.5 14.0 1.0 16.5 ns
5.0 1.0 10.5 13.5 1.0 15.5 ns
5.0 1.0 7.5 11.0 1.0 12.5 ns
5.0 1.0 9.5 15.0 1.0 18.0 ns
5.0 1.0 8.5 13.0 1.0 15.5 ns
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = +25°C
C
= 50 pF
L
Ta = –40°C to +85°C
CL = 50 pF
7
Page 8
HD74AC165/HD74ACT165
AC Operating Requirements: HD74ACT165
Ta = +25°C
C
L
Item Symbol V
Setup time, HIGH or LOW
H to S
L
Hold time, HIGH or LOW
H to S
L
Setup time, HIGH or LOW
S
to CP
in
Hold time, HIGH or LOW
S
to CP
in
Setup time, HIGH or LOW
S
to CP
L
Hold time, HIGH or LOW
S
to CP
L
Recovery time clock inhibit
t
su
t
h
t
su
t
h
t
su
t
h
t
rec
to CP
Clock pulse width t
w
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
(V)*1Typ Guaranteed Minimum Unit
CC
5.0 3.0 4.0 4.5 ns
5.0 –1.0 0.0 0.0 ns
5.0 0.5 3.0 3.5 ns
5.0 0.5 2.0 2.0 ns
5.0 2.0 4.0 4.5 ns
5.0 –1.5 0.0 0.0 ns
5.0 2.0 3.0 3.0 ns
5.0 3.5 7.0 8.0 ns
= 50 pF
Ta = –40°C
to +85°C
CL = 50 pF
Capacitance
Item Symbol Typ Unit Condition
Input capacitance C
Power dissipation capacitance C
IN
PD
4.5 pF VCC = 5.5 V
5.0 pF VCC = 5.0 V
8
Page 9
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code
JEDEC
EIAJ
Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16
Conforms
Conforms
1.07 g
Page 10
16
Unit: mm
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
+ 0.20
– 0.30
1.15
0° – 8°
FP-16DA
—
Conforms
0.24 g
Page 11
16
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Page 12
16 9
18
+ 0.08
*0.22
– 0.07
0.20 ± 0.06
5.00
5.30 Max
0.65 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
Page 13
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