Datasheet HD74AC166 Datasheet (HIT)

Page 1
HD74AC166/HD74ACT166
8-bit Shift Register
Description
The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other.
Features
HD74ACT166 has TTL-Compatible Inputs
Pin Arrangement
D
P0
P1
P2
P3
CP2
CP1
GND
1
S
2
3
4
5
6
7
8
(Top view)
16
15
14
13
12
11
10
CC
V
PE
7
P
Q7
P6
P5
P4
9
MR
Page 2
HD74AC166/HD74ACT166
Logic Symbol
15
2 3 4 5 10 11 12 14
P
0
PE P
1 P2 P3 P4 P5 P6 P7
1
71 6
2
DS
CP
MR
913
V
CC=Pin16
GND=Pin8
7
Q
Pin Names
CP1, CP2Clock Pulse Inputs (Active Rising Edge) D
S
Serial Data Input PE Parallel Enable Input (Active Low) P0 to P
Parallel Data Inputs
7
MR Asynchronous Master Reset Input (Active Low) Q
7
Last Stage Output
Functional Description
Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should attain the High state while the other clock is still in the High state following the previous operation. When the Parallel Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 Q1, Q Q2, etc.) on the rising edge of the clock.
1
2
Page 3
HD74AC166/HD74ACT166
Truth Table
Inputs
Parallel Internal Outputs Output
MR PE CP
2
LXXXXXL LL HXLLXXQA0Q HL L X a ··· h a b h
HH L HXHQAnQ HH L LXLQAnQ HX H XXQA0Q
H : High Voltage Level L : Low Voltage Level X : Immaterial
: Low-to-High Clock Transition
Logic Diagram
CP
1
D
S
P0 to P
Q
7
0
Q
6
B0
B0
Q
7
Q
H0
Gn
Gn
Q
H0
P
0 P1 P2 P3 P4 P5 P6 P7
RCP C
D
S
S
Q
MR PED
RCPS C
D
Q
Q
CP 12
7
3
Page 4
HD74AC166/HD74ACT166
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
Maximum additional ICC/input
CC
CC
I
CCT
(HD74ACT166)
AC Characteristics: HD74AC166
80 µAV
8.0 µAV
1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V,
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
Item Symbol V
Maximum clock f
max
Ta = +25°C C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
3.3 75 65 MHz
Ta = –40°C to +85°C CL = 50 pF
frequency 5.0 100 80 — Propagation delay t CP1 or CP2 to Q
7
Propagation delay t CP1 or CP2 to Q
7
Propagation delay t MR to Q
7
PLH
PHL
PHL
3.3 1.0 11.0 14.5 1.0 15.5 ns
5.0 1.0 9.5 11.5 1.0 12.5
3.3 1.0 10.5 14.0 1.0 15.0
5.0 1.0 9.0 11.0 1.0 12.0
3.3 1.0 9.5 12.0 1.0 13.0
5.0 1.0 6.5 9.0 1.0 10.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
4
Page 5
HD74AC166/HD74ACT166
AC Operating Requirements: HD74AC166
Ta = –40°C
Ta = +25°C C
= 50 pF
L
Item Symbol V
Setup time t PE or Pn or DS to CP
n
Hold time t CPn to PE or Pn or D
S
Pulse width t
su
h
w
(V)*1Typ Guaranteed Minimum Unit
CC
3.3 3.0 5.5 6.0 ns
5.0 2.0 4.0 4.5
3.3 –1.5 3.0 3.0
5.0 –0.5 3.0 3.0
3.3 2.0 5.5 7.0 CPn or MR 5.0 2.0 4.5 5.0 Recovery time t MR to CP
n
rec
3.3 –2.5 0.0 0.0
5.0 –1.5 0.0 0.0 Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Characteristics: HD74ACT166
to +85°C CL = 50 pF
Item Symbol V
Maximum clock
f
max
(V)*1Min Typ Max Min Max Unit
CC
5.0 100 80 MHz
frequency Propagation delay
CP
to Q
n
7
Propagation delay CP
to Q
n
7
Propagation delay MR to Q
7
t
PLH
t
PHL
t
PHL
5.0 1.0 10.0 12.5 1.0 13.5 ns
5.0 1.0 9.5 12.0 1.0 13.0
5.0 1.0 8.5 11.0 1.0 12.0
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = +25°C C
= 50 pF
L
Ta = –40°C to +85°C CL = 50 pF
5
Page 6
HD74AC166/HD74ACT166
AC Operating Requirements: HD74ACT166
Ta = –40°C
Ta = +25°C C
= 50 pF
L
Item Symbol V
Setup time PE or P
or DS to CP
n
n
Hold time CP
to PE or Pn or D
n
S
Pulse width CPn or MR t Recovery time MR to CP
t
su
t
h
w
t
n
rec
(V)*1Typ Guaranteed Minimum Unit
CC
5.0 2.5 7.0 8.0 ns
5.0 0.0 1.5 1.5
5.0 4.5 7.0 8.0
5.0 –2.5 0.5 0.5 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitance C Power dissipation capacitance C
IN
PD
4.5 pF VCC = 5.5 V
35.0 pF VCC = 5.0 V
to +85°C CL = 50 pF
6
Page 7
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16 Conforms Conforms
1.07 g
Page 8
16
Unit: mm
10.06
10.5 Max 9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code JEDEC EIAJ
(reference value)
Weight
+ 0.20 – 0.30
1.15
0° – 8°
FP-16DA — Conforms
0.24 g
Page 9
16
Unit: mm
9.9
10.3 Max 9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code JEDEC EIAJ Weight
+ 0.10 – 0.30
0° – 8°
(reference value)
FP-16DN Conforms Conforms
0.15 g
Page 10
16 9
18
+ 0.08
*0.22
– 0.07
0.20 ± 0.06
5.00
5.30 Max
0.65 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code JEDEC EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-16DA — —
0.05 g
Page 11
Cautions
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