Datasheet HCPL-2631, HCPL-2630, HCPL-4661, HCPL-2611, HCPL-2601 Datasheet (HP)

1-146

H

High CMR, High Speed TTL Compatible Optocouplers

Technical Data

6N137 HCNW137 HCNW2601 HCNW2611 HCPL-0600 HCPL-0601 HCPL-0611 HCPL-0630

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

Features

• 5 kV/µs Minimum Common

Mode Rejection (CMR) at VCM= 50 V for HCPL-X601/ X631, HCNW2601 and 10 kV/µs Minimum CMR at VCM = 1000 V for HCPLX611/X661, HCNW2611

• High Speed: 10 MBd Typical

• LSTTL/TTL Compatible

• Low Input Current Capability: 5 mA

• Guaranteed ac and dc Performance over Temperature: -40°C to +85°C

• Available in 8-Pin DIP, SOIC-8, Widebody Packages

• Strobable Output (Single Channel Products Only)

• Safety Approval

UL Recognized - 2500 V rms

for 1 minute and 5000 V rms*

for 1 minute per UL1577 CSA Approved VDE 0884 Approved with

V

IORM

= 630 V peak for HCPL-2611 Option 060 and V

IORM

= 1414 V peak for HCNW137/26X1

BSI Certified

(HCNW137/26X1 Only)

• MIL-STD-1772 Version Available (HCPL-56XX/ 66XX)

Functional Diagram

*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only.

HCPL-0631 HCPL-0661 HCPL-2601 HCPL-2611 HCPL-2630 HCPL-2631 HCPL-4661

Applications

• Isolated Line Receiver

• Computer-Peripheral Interfaces

• Microprocessor System Interfaces

• Digital Isolation for A/D,

D/A Conversion

• Switching Power Supply

• Instrument Input/Output Isolation

• Ground Loop Elimination

• Pulse Transformer Replacement

• Power Transistor Isolation in Motor Drives

• Isolation of High Speed Logic Systems

Description

The 6N137, HCPL-26XX/06XX/ 4661, HCNW137/26X1 are optically coupled gates that combine a GaAsP light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed. The output of the detector IC is

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

1

2

3

4

8

7

6

5

CATHODE

ANODE

GND

V

CC

O

1

2

3

4

8

7

6

5

ANODE

2

CATHODE

2

CATHODE

1

ANODE

1

GND

V

CC

O2

V

E

V

O1

6N137, HCPL-2601/2611

HCPL-0600/0601/0611

HCNW137/2601/2611

HCPL-2630/2631/4661 HCPL-0630/0631/0661

NC

LED ON

OFF ON OFF ON OFF

ENABLE

H H L

L NC NC

OUTPUT

L H H H L H

TRUTH TABLE

(POSITIVE LOGIC)

LED ON

OFF

OUTPUT

L H

TRUTH TABLE

(POSITIVE LOGIC)

SHIELD SHIELD

5965-3594E

1-147

an open collector Schottkyclamped transistor. The internal shield provides a guaranteed common mode transient immunity specification of 5,000 V/µs for the HCPL-X601/X631 and HCNW2601, and 10,000 V/µs for the HCPL-X611/X661 and HCNW2611.

This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. The optocoupler ac and dc operational parameters are guaranteed from -40°C to +85°C allowing troublefree system performance.

The 6N137, HCPL-26XX, HCPL06XX, HCPL-4661, HCNW137, and HCNW26X1 are suitable for high speed logic interfacing, input/output buffering, as line receivers in environments that conventional line receivers cannot tolerate and are recommended for use in extremely high ground or induced noise environments.

Selection Guide

Widebody

Minimum CMR 8-Pin DIP (300 Mil) Small-Outline SO-8 (400 Mil) Hermetic

Input Single

On- Single Dual Single Dual Single and Dual

dV/dt VCMCurrent Output Channel Channel Channel Channel Channel Channel

(V/µs) (V) (mA) Enable Package Package Package Package Package Packages

NA NA 5 YES 6N137 HCPL-0600 HCNW137

NO HCPL-2630 HCPL-0630

5,000 50 YES HCPL-2601 HCPL-0601 HCNW2601

NO HCPL-2631 HCPL-0631

10,000 1,000 YES HCPL-2611 HCPL-0611 HCNW2611

NO HCPL-4661 HCPL-0661

1,000 50 YES HCPL-2602

[1]

3, 500 300 YES HCPL-2612

[1]

1,000 50 3 YES HCPL-261A

[1]

HCPL-061A

[1]

NO HCPL-263A

[1]

HCPL-063A

[1]

1,000

[2]

1,000 YES HCPL-261N

[1]

HCPL-061N

[1]

NO HCPL-263N

[1]

HCPL-063N

[1]

1,000 50 12.5

[3]

HCPL-193X

[1]

HCPL-56XX

[1]

HCPL-66XX

[1]

Notes:

1. Technical data are on separate HP publications.

2. 15 kV/µs with VCM = 1 kV can be achieved using HP application circuit.

3. Enable is available for single channel products only, except for HCPL-193X devices.

1-148

Ordering Information

Specify Part Number followed by Option Number (if desired).

Example:

HCPL-2611#XXX

020 = 5000 V rms/1 minute UL Rating Option* 060 = VDE 0884 V

IORM

= 630 Vpeak Option** 300 = Gull Wing Surface Mount Option† 500 = Tape and Reel Packaging Option

Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor for information.

*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only. **For HCPL-2611 only. Combination of Option 020 and Option 060 is not available. †Gull wing surface mount option applies to through hole parts only.

Schematic

SHIELD

8

6

5

2+

3

V

F

USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).

–

I

F

I

CC

V

CC

V

O

GND

I

O

V

E

I

E

7

6N137, HCPL-2601/2611

HCPL-0600/0601/0611

HCNW137, HCNW2601/2611

SHIELD

8

7

+

2

V

F1

–

I

F1

I

CC

V

CC

V

O1

I

O1

1

SHIELD

6

5

–

4

V

F2

+

I

F2

V

O2

GND

I

O2

3

HCPL-2630/2631/4661 HCPL-0630/0631/0661

1-149

1.080 ± 0.320

(0.043 ± 0.013)

2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

5° TYP.

0.254

+ 0.076

- 0.051

(0.010

+ 0.003)

- 0.002)

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

9.65 ± 0.25

(0.380 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

HP XXXXZ

YYWW

DATE CODE

DIMENSIONS IN MILLIMETERS AND (INCHES).

5678

4321

OPTION CODE*

UL RECOGNITION

UR

TYPE NUMBER

*MARKING CODE LETTER FOR OPTION NUMBERS "L" = OPTION 020 "V" = OPTION 060 OPTION NUMBERS 300 AND 500 NOT MARKED.

Package Outline Drawings

8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)

8-pin DIP Package with Gull Wing Surface Mount Option 300 (6N137, HCPL-2601/11/30/31, HCPL-4661)

**JEDEC Registered Data (for 6N137 only).

0.635 ± 0.25

(0.025 ± 0.010)

12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.635 ± 0.130

(0.025 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

5

6

7

8

4

3

2

1

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.016 (0.040)

1.194 (0.047)

1.194 (0.047)

1.778 (0.070)

9.398 (0.370)

9.906 (0.390)

4.826

(0.190)



TYP.

0.381 (0.015)

0.635 (0.025)

PAD LOCATION (FOR REFERENCE ONLY)

1.080 ± 0.320

(0.043 ± 0.013)

4.19

(0.165)

MAX.

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.54

(0.100)

BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.254

+ 0.076

- 0.051

(0.010

+ 0.003)

- 0.002)

1-150

Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)

8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)

XXX

YWW

8765

4321

5.842 ± 0.203

(0.236 ± 0.008)

3.937 ± 0.127

(0.155 ± 0.005)

0.381 ± 0.076

(0.016 ± 0.003)

1.270

(0.050)

BSG

5.080 ± 0.127

(0.200 ± 0.005)

3.175 ± 0.127

(0.125 ± 0.005)

1.524

(0.060)

45° X

0.432

(0.017)

0.228 ± 0.025

(0.009 ± 0.001)

TYPE NUMBER (LAST 3 DIGITS)

DATE CODE

0.305

(0.012)

MIN.

DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.152 ± 0.051

(0.006 ± 0.002)

7°

5

6

7

8

4

3

2

1

11.15 ± 0.15

(0.442 ± 0.006)

1.78 ± 0.15

(0.070 ± 0.006)

5.10

(0.201)

MAX.

1.55

(0.061)

MAX.

2.54 (0.100) TYP.

DIMENSIONS IN MILLIMETERS (INCHES).

7° TYP.

0.254

+ 0.076

- 0.0051

(0.010

+ 0.003)

- 0.002)

11.00

(0.433)

9.00 ± 0.15

(0.354 ± 0.006)

MAX.

10.16 (0.400) TYP.

HP 

HCNWXXXX



YYWW

DATE CODE

TYPE NUMBER

0.51 (0.021) MIN.

0.40 (0.016)

0.56 (0.022)

3.10 (0.122)

3.90 (0.154)

1-151

8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW137, HCNW2601/11)

Note: Use of nonchlorine activated fluxes is highly recommended.

Solder Reflow Temperature Profile (HCPL-06XX and Gull Wing Surface Mount Option 300 Parts)

240

∆T = 115°C, 0.3°C/SEC

0

∆T = 100°C, 1.5°C/SEC

∆T = 145°C, 1°C/SEC

TIME – MINUTES

TEMPERATURE – °C

220 200 180 160 140 120 100

80 60 40 20

0

260

123456789101112

1.00 ± 0.15

(0.039 ± 0.006)

7° NOM.

12.30 ± 0.30

(0.484 ± 0.012)

0.75 ± 0.25

(0.030 ± 0.010)

11.00

(0.433)

5

6

7

8

4

3

2

1

11.15 ± 0.15

(0.442 ± 0.006)

9.00 ± 0.15

(0.354 ± 0.006)

1.3

(0.051)

12.30 ± 0.30

(0.484 ± 0.012)

6.15

(0.242)



TYP.

0.9

(0.035)

PAD LOCATION (FOR REFERENCE ONLY)

1.78 ± 0.15

(0.070 ± 0.006)

4.00

(0.158)

MAX.

1.55

(0.061)

MAX.

2.54

(0.100)

BSC

DIMENSIONS IN MILLIMETERS (INCHES).  LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.254

+ 0.076

- 0.0051

(0.010

+ 0.003)

- 0.002)

MAX.

1-152

Regulatory Information

The 6N137, HCPL-26XX/06XX/ 46XX, and HCNW137/26XX have been approved by the following organizations:

UL

Recognized under UL 1577, Component Recognition Program, File E55361.

CSA

Approved under CSA Component Acceptance Notice #5, File CA

88324.

VDE

Approved according to VDE 0884/06.92. (HCPL-2611 Option 060 and HCNW137/26X1 only)

BSI

Certification according to BS415:1994 (BS EN60065:1994), BS7002:1992 (BS EN60950:1992) and EN41003:1993 for Class II applications. (HCNW137/26X1 only)

Insulation and Safety Related Specifications

8-pin DIP Widebody

(300 Mil) SO-8 (400 Mil)

Parameter Symbol Value Value Value Units Conditions

Minimum External L(101) 7.1 4.9 9.6 mm Measured from input terminals Air Gap (External to output terminals, shortest Clearance) distance through air.

Minimum External L(102) 7.4 4.8 10.0 mm Measured from input terminals Tracking (External to output terminals, shortest Creepage) distance path along body.

Minimum Internal 0.08 0.08 1.0 mm Through insulation distance, Plastic Gap conductor to conductor, usually (Internal Clearance) the direct distance between the

photoemitter and photodetector inside the optocoupler cavity.

Minimum Internal NA NA 4.0 mm Measured from input terminals Tracking (Internal to output terminals, along Creepage) internal cavity.

Tracking Resistance CTI 200 200 200 Volts DIN IEC 112/VDE 0303 Part 1 (Comparative Tracking Index)

Isolation Group IIIa IIIa IIIa Material Group

(DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

1-153

VDE 0884 Insulation Related Characteristics (HCPL-2611 Option 060 Only)

Description Symbol Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 300 V rms I-IV for rated mains voltage ≤ 450 V rms I-III

Climatic Classification 55/85/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage V

IORM

630 V

peak

Input to Output Test Voltage, Method b*

V

IORM

x 1.875 = VPR, 100% Production Test with tm = 1 sec, V

PR

1181 V

peak

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

V

IORM

x 1.5 = VPR, Type and sample test, V

PR

945 V

peak

tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage* (Transient Overvoltage, t

ini

= 10 sec) V

IOTM

6000 V

peak

Safety Limiting Values

(Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.)

Case Temperature T

S

175 °C

Input Current I

S,INPUT

230 mA

Output Power P

S,OUTPUT

600 mW

Insulation Resistance at TS, VIO = 500 V R

S

≥ 10

9

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

VDE 0884 Insulation Related Characteristics (HCNW137/2601/2611 Only)

Description Symbol Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 600 V rms I-IV for rated mains voltage ≤ 1000 V rms I-III

Climatic Classification (DIN IEC 68 part 1) 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage V

IORM

1414 V

peak

Input to Output Test Voltage, Method b*

V

IORM

x 1.875 = VPR, 100% Production Test with tm = 1 sec, V

PR

2651 V

peak

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

V

IORM

x 1.5 = VPR, Type and sample test, V

PR

2121 V

peak

tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage* (Transient Overvoltage, t

ini

= 10 sec) V

IOTM

8000 V

peak

Safety Limiting Values

(Maximum values allowed in the event of a failure, also see Figure 16, Thermal Derating curve.)

Case Temperature T

S

150 °C

Input Current I

S,INPUT

400 mA

Output Power P

S,OUTPUT

700 mW

Insulation Resistance at TS, VIO = 500 V R

S

≥ 10

9

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884), for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.

1-154

Absolute Maximum Ratings* (No Derating Required up to 85°C)

Parameter Symbol Package** Min. Max. Units Note

Storage Temperature T

S

-55 125 °C

Operating Temperature† T

A

-40 85 °C

Average Forward Input Current I

F

Single 8-Pin DIP 20 mA 2

Single SO-8

Widebody

Dual 8-Pin DIP 15 1, 3

Dual SO-8

Reverse Input Voltage V

R

8-Pin DIP, SO-8 5 V 1

Widebody 3

Input Power Dissipation P

I

Widebody 40 mW

Supply Voltage V

CC

7V

(1 Minute Maximum) Enable Input Voltage (Not to V

E

Single 8-Pin DIP VCC + 0.5 V Exceed VCC by more than Single SO-8 500 mV) Widebody

Enable Input Current I

E

5mA

Output Collector Current I

O

50 mA 1

Output Collector Voltage V

O

7V1 (Selection for Higher Output Voltages up to 20 V is Available.)

Output Collector Power P

O

Single 8-Pin DIP 85 mW

Dissipation Single SO-8

Widebody

Dual 8-Pin DIP 60 1, 4

Dual SO-8

Lead Solder Temperature T

LS

8-Pin DIP 260°C for 10 sec.,

(Through Hole Parts Only) 1.6 mm below seating plane

Widebody 260°C for 10 sec.,

up to seating plane

Solder Reflow Temperature SO-8 and See Package Outline Profile (Surface Mount Parts Only) Option 300 Drawings section

*JEDEC Registered Data (for 6N137 only). **Ratings apply to all devices except otherwise noted in the Package column. †0°C to 70°C on JEDEC Registration.

Recommended Operating Conditions

Parameter Symbol Min. Max. Units

Input Current, Low Level IFL* 0 250 µA Input Current, High Level

[1]

IFH** 5 15 mA

Power Supply Voltage V

CC

4.5 5.5 V

Low Level Enable Voltage† V

EL

0 0.8 V

High Level Enable Voltage† V

EH

2.0 V

CC

V

Operating Temperature T

A

-40 85 °C

Fan Out (at RL = 1 kΩ)

[1]

N 5 TTL Loads

Output Pull-up Resistor R

L

330 4 k Ω

*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts. **The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit at least a 20% LED degradation guardband. †For single channel products only.

1-155

Electrical Specifications

Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. All Typicals at VCC = 5 V, TA = 25°C. All enable test conditions apply to single channel products only. See note 5.

Parameter Sym. Package Min. Typ. Max. Units Test Conditions Fig. Note

High Level Output IOH* All 5.5 100 µAVCC = 5.5 V, VE = 2.0 V, 1 1, 6, Current V

O

= 5.5 V, IF = 250 µA19

Input Threshold I

TH

Single Channel 2.0 5.0 mA VCC = 5.5 V, VE = 2.0 V, 2, 3 19

Current Widebody V

O

= 0.6 V,

Dual Channel 2.5 I

OL

(Sinking) = 13 mA

Low Level Output VOL* 8-Pin DIP 0.35 0.6 V VCC = 5.5 V, VE = 2.0 V, 2, 3, 1, 19 Voltage SO-8 I

F

= 5 mA, 4, 5

Widebody 0.4 I

OL

(Sinking) = 13 mA

High Level Supply I

CCH

Single Channel 7.0 10.0* mA VE = 0.5 V VCC = 5.5 V 7

Current 6.5 V

E

= V

CCIF

= 0 mA

Dual Channel 10 15 Both

Channels

Low Level Supply I

CCL

Single Channel 9.0 13.0* mA VE = 0.5 V VCC = 5.5 V 8

Current 8.5 V

E

= V

CCIF

= 10 mA

Dual Channel 13 21 Both

Channels

High Level Enable I

EH

Single Channel -0.7 -1.6 mA VCC = 5.5 V, VE = 2.0 V

Current Low Level Enable IEL* -0.9 -1.6 mA VCC = 5.5 V, VE = 0.5 V 9

Current High Level Enable V

EH

2.0 V 19

Voltage Low Level Enable V

EL

0.8 V

Voltage Input Forward V

F

8-Pin DIP 1.4 1.5 1.75* V TA = 25°CIF = 10 mA 6, 7 1

Voltage SO-8 1.3 1.80

Widebody 1.25 1.64 1.85 T

A

= 25°C

1.2 2.05

Input Reverse BVR* 8-Pin DIP 5 V IR = 10 µA1 Breakdown SO-8 Voltage Widebody 3 IR = 100 µA, TA = 25°C

Input Diode ∆VF/ 8-Pin DIP -1.6 mV/°C IF = 10 mA 7 1 Temperature ∆T

A

SO-8

Coefficient Widebody -1.9 Input Capacitance C

IN

8-Pin DIP 60 pF f = 1 MHz, VF = 0 V 1

SO-8

Widebody 70

*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.

1-156

Switching Specifications (AC)

Over Recommended Temperature (TA = -40°C to +85°C), VCC = 5 V, I

F

= 7.5 mA unless otherwise specified.

All Typicals at TA = 25°C, VCC = 5 V.

Parameter Sym. Package** Min. Typ. Max. Units Test Conditions Fig. Note

Propagation Delay t

PLH

20 48 75* ns TA = 25°CRL = 350 Ω 8, 9, 1, 10,

Time to High 100 C

L

= 15 pF 10 19

Output Level Propagation Delay t

PHL

25 50 75* ns TA = 25°C 1, 11, Time to Low 100 19 Output Level

Pulse Width |t

PHL

- t

PLH

| 8-Pin DIP 3.5 35 ns 8, 9, 13, 19

Distortion SO-8 10,

Widebody 40 11

Propagation Delay t

PSK

40 ns 12, 13,

Skew 19 Output Rise t

r

24 ns 12 1, 19

Time (10-90%) Output Fall t

f

10 ns 12 1, 19

Time (90-10%) Propagation Delay t

ELH

Single Channel 30 ns RL = 350 Ω, 13, 14

Time of Enable C

L

= 15 pF, 14

from V

EH

to V

EL

VEL = 0 V, VEH = 3 V

Propagation Delay t

EHL

Single Channel 20 ns 15 Time of Enable from V

EL

to V

EH

*JEDEC registered data for the 6N137. **Ratings apply to all devices except otherwise noted in the Package column.

Parameter Sym. Device Min. Typ. Units Test Conditions Fig. Note

Logic High |CMH| 6N137 10,000 V/µs|VCM| = 10 V VCC = 5 V, IF = 0 mA, 15 1, 16, Common HCPL-2630 V

O(MIN)

= 2 V, 18, 19

Mode HCPL-0600/0630 R

L

= 350 Ω, TA = 25°C

Transient HCNW137 Immunity HCPL-2601/2631 5,000 10,000 |V

CM

| = 50 V HCPL-0601/0631 HCNW2601 HCPL-2611/4661 10,000 15,000 |V

CM

| = 1 kV HCPL-0611/0661 HCNW2611

Logic Low |CML| 6N137 10,000 V/µs|VCM| = 10 V VCC = 5 V, IF = 7.5 mA, 15 1, 17, Common HCPL-2630 V

O(MAX)

= 0.8 V, 18, 19

Mode HCPL-0600/0630 R

L

= 350 Ω, TA = 25°C

Transient HCNW137 Immunity HCPL-2601/2631 5,000 10,000 |V

CM

| = 50 V HCPL-0601/0631 HCNW2601 HCPL-2611/4661 10,000 15,000 |V

CM

| = 1 kV HCPL-0611/0661 HCNW2611

1-157

Package Characteristics

All Typicals at TA = 25°C.

Parameter Sym. Package Min. Typ. Max. Units Test Conditions Fig. Note

Input-Output I

I-O

* Single 8-Pin DIP 1 µA 45% RH, t = 5 s, 20, 21

Insulation Single SO-8 V

I-O

= 3 kV dc, TA = 25°C

Input-Output V

ISO

8-Pin DIP, SO-8 2500 V rms RH ≤ 50%, t = 1 min, 20, 21

Momentary With- Widebody 5000 T

A

= 25°C 20, 22

stand Voltage** OPT 020† 5000 Input-Output R

I-O

8-Pin DIP, SO-8 10

12

Ω V

I-O

= 500 V dc 1, 20,

Resistance Widebody 10

12

10

13

TA = 25°C23

10

11

TA = 100°C

Input-Output C

I-O

8-Pin DIP, SO-8 0.6 pF f = 1 MHz, TA = 25°C 1, 20,

Capacitance Widebody 0.5 0.6 23 Input-Input I

I-I

Dual Channel 0.005 µA RH ≤ 45%, t = 5 s, 24

Insulation V

I-I

= 500 V

Leakage Current Resistance R

I-I

Dual Channel 10

11

Ω 24

(Input-Input) Capacitance C

I-I

Dual 8-Pin DIP 0.03 pF f = 1 MHz 24

(Input-Input) Dual SO-8 0.25

*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. HP specifies -40°C to 85°C. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” †For 6N137, HCPL-2601/2611/2630/2631/4661 only.

Notes:

1. Each channel.

2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA.

3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA.

4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.

5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.

6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 µA. HP guarantees a maximum IOH of 100 µA.

7. The JEDEC registration for the 6N137 specifies a maximum I

CCH

of 15 mA. HP guarantees a maximum I

CCH

of 10 mA.

8. The JEDEC registration for the 6N137 specifies a maximum I

CCL

of 18 mA. HP guarantees a maximum I

CCL

of 13 mA.

9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. HP guarantees a maximum IEL of -1.6 mA.

10. The t

PLH

propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the

rising edge of the output pulse.

11. The t

PHL

propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the

falling edge of the output pulse.

12. t

PSK

is equal to the worst case difference in t

PHL

and/or t

PLH

that will be seen between units at any given temperature and specified

test conditions.

13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.

14. The t

ELH

enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V

point on the rising edge of the output pulse.

15. The t

EHL

enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point

on the falling edge of the output pulse.

16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state (i.e., VO > 2.0 V).

17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state (i.e., VO < 0.8 V).

18. For sinusoidal voltages, (|dVCM | / dt)

max

= πfCMVCM(p-p).

1-158

I

OH

– HIGH LEVEL OUTPUT CURRENT – µA

-60

0

TA – TEMPERATURE – °C

100

10

15

-20

5

20

V

CC

= 5.5 V

V

O

= 5.5 V

V

E

= 2.0 V*

I

F

= 250 µA

60

-40 0 40 80

* FOR SINGLE CHANNEL PRODUCTS ONLY

19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in improved CMR performance. For single channel products only.

20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for one second (leakage detection current limit, I

I-O

≤ 5 µA). This test is performed before the 100% production test for partial discharge

(Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.

22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage detection current limit, I

I-O

≤ 5 µA). This test is performed before the 100% production test for partial discharge

(Method b) shown in the VDE 0884 Insulation Characteristics Table, if applicable.

23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.

24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.

Figure 2. Typical Output Voltage vs. Forward Input Current.

Figure 3. Typical Input Threshold Current vs. Temperature.

Figure 1. Typical High Level Output Current vs. Temperature.

1

6

2

3

4

5

123456

I

F

– FORWARD INPUT CURRENT – mA

RL = 350 Ω

RL = 1 KΩ

RL = 4 KΩ

0

VCC = 5 V

T

A

= 25 °C

V

O

– OUTPUT VOLTAGE – V

8-PIN DIP, SO-8

1

6

2

3

4

5

123456

I

F

– FORWARD INPUT CURRENT – mA

RL = 350 Ω

RL = 1 KΩ

RL = 4 KΩ

0

VCC = 5 V

T

A

= 25 °C

V

O

– OUTPUT VOLTAGE – V

WIDEBODY

VCC = 5.0 V V

O

= 0.6 V

6

3

-60 -20 20

60

100

T

A

– TEMPERATURE – °C

2

80400-40

0

I

TH

– INPUT THRESHOLD CURRENT – mA

RL = 350 KΩ

1

4

5

RL = 1 KΩ

RL = 4 KΩ

8-PIN DIP, SO-8

VCC = 5.0 V V

O

= 0.6 V

6

3

-60 -20 20

60

100

T

A

– TEMPERATURE – °C

2

80400-40

0

I

TH

– INPUT THRESHOLD CURRENT – mA

RL = 350 Ω

1

4

5

RL = 1 KΩ

RL = 4 KΩ

WIDEBODY

1-159

VCC = 5.0 V V

E

= 2.0 V*

V

OL

= 0.6 V

70

60

-60 -20 20

60

100

T

A

– TEMPERATURE – °C

50

80400-40

20

I

OL

– LOW LEVEL OUTPUT CURRENT – mA

40

IF = 10-15 mA

IF = 5.0 mA

* FOR SINGLE CHANNEL PRODUCTS ONLY

0.8

0.4

-60 -20 20

60

100

T

A

– TEMPERATURE – °C

0.2

80400-40

0

V

OL

– LOW LEVEL OUTPUT VOLTAGE – V

IO = 16 mA

0.1

0.5

0.7

IO = 6.4 mA

WIDEBODY

VCC = 5.5 V V

E

= 2.0 V

I

F

= 5.0 mA

0.3

0.6

IO = 12.8 mA

IO = 9.6 mA

Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.

Figure 4. Typical Low Level Output Voltage vs. Temperature. Figure 5. Typical Low Level Output

Current vs. Temperature.

Figure 6. Typical Input Diode Forward Characteristic.

0.8

0.4

-60 -20 20

60

100

T

A

– TEMPERATURE – °C

0.2

80400-40

0

V

OL

– LOW LEVEL OUTPUT VOLTAGE – V

IO = 16 mA

0.1

0.5

0.7

IO = 6.4 mA

8-PIN DIP, SO-8

VCC = 5.5 V V

E

= 2.0 V*

I

F

= 5.0 mA

0.3

0.6

IO = 12.8 mA

IO = 9.6 mA

* FOR SINGLE CHANNEL PRODUCTS ONLY

I

F

– FORWARD CURRENT – mA

1.1

0.001

VF – FORWARD VOLTAGE – V

1.0

1000

1.3

0.01

1.51.2 1.4

0.1

T

A

= 25 °C

10

100

8-PIN DIP, SO-8

I

F

+ –

V

F

1.6

I

F

– FORWARD CURRENT – mA

1.2

0.001

VF – FORWARD VOLTAGE – V

1.0

110

1.4

0.01

1.61.3 1.5

0.1

10

100

WIDEBODY

I

F

+

–

V

F

1.7

T

A

= 25 °C

dV

F

/dT – FORWARD VOLTAGE 

TEMPERATURE COEFFICIENT – mV/°C

0.1 1 10 100 I

F

– PULSE INPUT CURRENT – mA

-1.4

-2.2

-2.0

-1.8

-1.6

-1.2

-2.4

8-PIN DIP, SO-8

dV

F

/dT – FORWARD VOLTAGE 

TEMPERATURE COEFFICIENT – mV/°C

0.1 1 10 100 I

F

– PULSE INPUT CURRENT – mA

-1.9

-2.2

-2.1

-2.0

-1.8

-2.3

WIDEBODY

1-160

VCC = 5.0 V I

F

= 7.5 mA

40

30

-20 20

60

100

T

A

– TEMPERATURE – °C

20

80400-40

PWD – PULSE WIDTH DISTORTION – ns

10

RL = 350 Ω

RL = 1 kΩ

RL = 4 kΩ

0

-60

-10

Figure 8. Test Circuit for t

PHL

and t

PLH

.

Figure 9. Typical Propagation Delay vs. Temperature.

Figure 10. Typical Propagation Delay vs. Pulse Input Current.

Figure 11. Typical Pulse Width Distortion vs. Temperature.

Figure 12. Typical Rise and Fall Time vs. Temperature.

VCC = 5.0 V T

A

= 25°C

105

90

5913

I

F

– PULSE INPUT CURRENT – mA

75

15117

30

t

P

– PROPAGATION DELAY – ns

60

45

t

PLH

, RL = 4 KΩ

t

PLH

, RL = 1 KΩ

t

PLH

, RL = 350 Ω

t

PHL

, RL = 350 Ω

1 KΩ 4 KΩ

OUTPUT V MONITORING NODE

O

+5 V

7

5

6

8

2

3

4

1

PULSE GEN.

Z = 50 Ω

t = t = 5 ns

O

f

I

F

L

R

M

CC

V

0.1µF BYPASS

*C

L

GND

INPUT

MONITORING

NODE

r

SINGLE CHANNEL

OUTPUT V MONITORING NODE

O

+5 V

7

5

6

8

2

3

4

1

PULSE GEN.

Z = 50 Ω

t = t = 5 ns

O

f

I

F

L

R

M

CC

V

0.1µF BYPASS

C

L

*

GND

INPUT

MONITORING

NODE

r

DUAL CHANNEL

1.5 V

t

PHL

t

PLH

I

F

INPUT

O

V

OUTPUT

I = 7.50 mA

F

I = 3.75 mA

F

*CL IS APPROXIMATELY 15 pF WHICH INCLUDES PROBE AND STRAY WIRING CAPACITANCE.

VCC = 5.0 V I

F

= 7.5 mA

100

80

-60 -20 20

60

100

T

A

– TEMPERATURE – °C

60

80400-40

0

t

P

– PROPAGATION DELAY – ns

40

20

t

PLH

, RL = 4 KΩ

t

PLH

, RL = 1 KΩ

t

PLH

, RL = 350 Ω

t

PHL

, RL = 350 Ω

1 KΩ 4 KΩ

t

r

, t

f

– RISE, FALL TIME – ns

-60

0

T

A

– TEMPERATURE – °C

100

300

-20

40

20 60-40 0 40 80

60

290

20

VCC = 5.0 V I

F

= 7.5 mA

R

L

= 4 kΩ

RL = 1 kΩ

RL = 350 Ω, 1 kΩ, 4 kΩ

t

RISE

t

FALL

RL = 350 Ω

1-161

OUTPUT V  MONITORING  NODE

O

1.5 V

t

EHL

t

ELH

V

E

INPUT

O

V

OUTPUT

3.0 V

1.5 V

+5 V

7

5

6

8

2

3

4

1

PULSE GEN.

Z = 50 Ω

t = t = 5 ns

O

f

I

F

L

R

CC

V

0.1 µF BYPASS

*C

L

*C IS APPROXIMATELY 15 pF WHICH INCLUDES  PROBE AND STRAY WIRING CAPACITANCE.

L

GND

r

7.5 mA

INPUT VE MONITORING NODE

Figure 13. Test Circuit for t

EHL

and t

ELH

.

Figure 14. Typical Enable Propagation Delay vs. Temperature.

Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.

V

O

0.5 V

O

V (MIN.)

5 V

0 V

SWITCH AT A: I = 0 mA

F

SWITCH AT B: I = 7.5 mA

F

CM

V

H

CM

L

O

V (MAX.)

CM

V (PEAK)

V

O

t

E

– ENABLE PROPAGATION DELAY – ns

-60

0

TA – TEMPERATURE – °C

100

90

120

-20

30

20 60-40 0 40 80

60

VCC = 5.0 V V

EH

= 3.0 V

V

EL

= 0 V

I

F

= 7.5 mA

t

ELH

, RL = 4 kΩ

t

ELH

, RL = 1 kΩ

t

EHL

, RL = 350 Ω, 1 kΩ, 4 kΩ

t

ELH

, RL = 350 Ω

+5 V

7

5

6

8

2

3

4

1

CC

V

0.1 µF BYPASS

GND

OUTPUT V MONITORING NODE

O

PULSE

GENERATOR

Z = 50 Ω

O

+

I

F

B A

V

FF

CM

V –

R

L

SINGLE CHANNEL

+5 V

7

5

6

8

2

3

4

1

CC

V

0.1 µF BYPASS

GND

OUTPUT V  MONITORING  NODE

O

PULSE

GENERATOR

Z = 50 Ω

O

+

I

F

B

A

V

FF

CM

V –

R

L

DUAL CHANNEL

1-162

Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per VDE 0884.

Figure 17. Recommended Printed Circuit Board Layout.

OUTPUT POWER – P

S

, INPUT CURRENT – I

S

0

TS – CASE TEMPERATURE – °C

17550

400

12525 75 100 150

600

800

200 100

300

500

700

PS (mW) I

S

(mA)

HCNWXXXX

GND BUS (BACK)

VCC BUS (FRONT)

ENABLE

0.1µF

10 mm MAX.

(SEE NOTE 5)

OUTPUT

NC

SINGLE CHANNEL DEVICE ILLUSTRATED.

OUTPUT POWER – P

S

, INPUT CURRENT – I

S

0

TS – CASE TEMPERATURE – °C

20050

400

12525 75 100 150

600

800

200 100

300

500

700

PS (mW) I

S

(mA)

HCPL-2611 OPTION 060

175

1-163

V

CC1

5 V

GND 1

D1*

SHIELD

DUAL CHANNEL DEVICE

CHANNEL 1 SHOWN

8

7

5

390 Ω

0.1 µF BYPASS

1

2

+

–

5 V

GND 2

V

CC2

2

470 Ω

1

I

F

V

F

*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.

V

CC1

5 V

GND 1

D1*

I

F

V

F

SHIELD

SINGLE CHANNEL DEVICE

8

6

5

390 Ω

0.1 µF BYPASS

2

3

+

–

5 V

GND 2

V

CC2

2

470 Ω

1

7

V

E

Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.

1-164

Propagation Delay, PulseWidth Distortion and Propagation Delay Skew

Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t

PLH

) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t

PHL

) is the amount of time required for the input signal to propagate to the output causing the output to change from high to low (see Figure 8).

Pulse-width distortion (PWD) results when t

PLH

and t

PHL

differ in value. PWD is defined as the difference between t

PLH

and t

PHL

and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20-30% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS232, RS422, T-l, etc.).

Propagation delay skew, t

PSK

, is an important parameter to consider in parallel data applica-

tions where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers.

Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t

PLH

or

t

PHL

, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating temperature). As illustrated in Figure 19, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t

PSK

is the difference between the shortest propagation delay, either t

PLH

or

t

PHL

, and the longest propagation

delay, either t

PLH

or t

PHL

.

As mentioned earlier, t

PSK

can determine the maximum parallel data transmission rate. Figure 20 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock

signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast.

Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 20 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t

PSK

. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.

The t

PSK

specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges.

1-165

Figure 19. Illustration of Propagation Delay Skew - t

PSK

.

Figure 20. Parallel Data Transmission Example.

50%

1.5 V

I

F

V

O

50%I

F

V

O

t

PSK

1.5 V

DATA

t

PSK

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

t

PSK

Datasheet HCPL-2631, HCPL-2630, HCPL-4661, HCPL-2611, HCPL-2601 Datasheet (HP)

Specifications and Main Features

Frequently Asked Questions

User Manual