Datasheet HCPL-2400, HCPL-2430 Datasheet (HP)

1-300

7

1

2

3

4

5

6

8

ANODE 1

CATHODE 1

CATHODE 2

ANODE 2 GND

V

CC

V

O1

V

O2

HCPL-2430

TRUTH TABLE

(POSITIVE LOGIC)

LED

ON

OFF

V

CC

GND

NC

7

1

2

3

4

5

6

8

HCPL-2400

NC

LED
ON

OFF
ON
OFF

ENABLE

L
L
H
H

OUTPUT

L
H
Z
Z

TRUTH TABLE

(POSITIVE LOGIC)

OUTPUT

L
H

V

E

V

O

ANODE

CATHODE

H

Features

• High Speed: 40 MBd Typical
Data Rate

• High Common Mode
Rejection:

HCPL-2400: 10 kV/µs at
VCM = 300 V (Typical)

• AC Performance Guaranteed
over Temperature

• High Speed AlGaAs Emitter

• Compatible with TTL, STTL,
LSTTL, and HCMOS Logic
Families

• Totem Pole and Tri State
Output (No Pull Up Resistor
Required)

• Safety Approval

UL Recognized – 2500 V rms

for 1 minute per UL1577

VDE 0884 Approved with

V

IORM

= 630 V peak (Option

060) for HCPL-2400

CSA Approved

• High Power Supply Noise
Immunity

• MIL-STD-1772 Version
Available (HCPL-5400/1 and
HCPL-5430/1)

20 MBd High CMR Logic Gate
Optocouplers

Technical Data

HCPL-2400
HCPL-2430

Applications

• Isolation of High Speed
Logic Systems

• Computer-Peripheral
Interfaces

• Switching Power Supplies

• Isolated Bus Driver
(Networking Applications)

• Ground Loop Elimination

• High Speed Disk Drive I/O

• Digital Isolation for A/D,
D/A Conversion

• Pulse Transformer
Replacement

Functional Diagram

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

Description

The HCPL-2400 and HCPL-2430
high speed optocouplers combine
an 820 nm AlGaAs light emitting
diode with a high speed
photodetector. This combination
results in very high data rate
capability and low input current.
The totem pole output (HCPL-

2430) or three state output
(HCPL-2400) eliminates the need
for a pull up resistor and allows
for direct drive of data buses.

5965-3586E

1-301

Selection Guide

8-Pin DIP (300 Mil) Minimum CMR

Single Dual Minimum Input Maximum

Channel Channel dV/dt V

CM

On Current Propagation Delay Hermetic

Package Package (V/µs) (V) (mA) (ns) Package

HCPL-2400 1000 300 4 60

HCPL-2430 1000 50 4 60

500 50 6 60 HCPL-540X*
500 50 6 60 HCPL-543X*
500 50 6 60 HCPL-643X*

*Technical data for the Hermetic HCPL-5400/01, HCPL-5430/31, and HCPL-6430/31 are on separate HP publications.

The detector has optical receiver
input stage with built-in Schmitt
trigger to provide logic compatible
waveforms, eliminating the need
for additional waveshaping. The
hysteresis provides differential
mode noise immunity and mini­mizes the potential for output
signal chatter.

The electrical and switching
characteristics of the HCPL-2400
and HCPL-2430 are guaranteed
over the temperature range of
0°C to 70°C.

These optocouplers are
compatible with TTL, STTL,
LSTTL, and HCMOS logic

families. When Schottky type TTL
devices (STTL) are used, a data
rate performance of 20 MBd over
temperature is guaranteed when
using the application circuit of
Figure 13. Typical data rates are
40 MBd.

Ordering Information

Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2400#XXX

060 = VDE 0884 V

IORM

= 630 V peak Option*
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option

*For HCPL-2400 only.

Schematic

I

F

V

F

V

CC

V

O

GND

I

CC

I

O

+

–

2

3

8

5

I

F1

V

F1

V

CC

V

O1

I

CC

I

O

+

–

1

2

8

6

SHIELD

V

F2

V

O2

GND

I

O

–

+

3

4

5

I

F2

7

ANODE

CATHODE

I

E

V

E

7
6

TRUTH TABLE

(POSITIVE LOGIC)

LED

ON

OFF

LED
ON

OFF
ON
OFF

ENABLE

L
L
H
H

OUTPUT

L
H
Z
Z

TRUTH TABLE

(POSITIVE LOGIC)

OUTPUT

L
H

1-302

9.65 ± 0.25

(0.380 ± 0.010)

1.78 (0.070) MAX.

1.19 (0.047) MAX.

HP XXXXZ

YYWW

DATE CODE

1.080 ± 0.320

(0.043 ± 0.013)

2.54 ± 0.25

(0.100 ± 0.010)

0.51 (0.020) MIN.

0.65 (0.025) MAX.

4.70 (0.185) MAX.

2.92 (0.115) MIN.

DIMENSIONS IN MILLIMETERS AND (INCHES).

5678

4321

5° TYP.

OPTION CODE*

UL
RECOGNITION

UR

0.254

+ 0.076

- 0.051

(0.010

+ 0.003)

- 0.002)

7.62 ± 0.25

(0.300 ± 0.010)

6.35 ± 0.25

(0.250 ± 0.010)

TYPE NUMBER

*MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.

Package Outline Drawings

8-Pin DIP Package (HCPL-2400, HCPL-2430)

8-Pin DIP Package with Gull Wing Surface Mount Option 300
(HCPL-2400, HCPL-2430)

0.635 ± 0.25

(0.025 ± 0.010)

12° NOM.

9.65 ± 0.25

(0.380 ± 0.010)

0.635 ± 0.130

(0.025 ± 0.005)

7.62 ± 0.25

(0.300 ± 0.010)

5

6

7

8

4

3

2

1

9.65 ± 0.25

(0.380 ± 0.010)

6.350 ± 0.25

(0.250 ± 0.010)

1.016 (0.040)

1.194 (0.047)

1.194 (0.047)

1.778 (0.070)

9.398 (0.370)

9.906 (0.390)

4.826

(0.190)



TYP.

0.381 (0.015)

0.635 (0.025)

PAD LOCATION (FOR REFERENCE ONLY)

1.080 ± 0.320

(0.043 ± 0.013)

4.19

(0.165)

MAX.

1.780

(0.070)

MAX.

1.19

(0.047)

MAX.

2.54

(0.100)

BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).

0.254

+ 0.076

- 0.051

(0.010

+ 0.003)

- 0.002)

1-303

Note: Use of nonchlorine activated fluxes is highly recommended.

240

∆T = 115°C, 0.3°C/SEC

0

∆T = 100°C, 1.5°C/SEC

∆T = 145°C, 1°C/SEC

TIME – MINUTES

TEMPERATURE – °C

220
200
180
160
140
120
100

80
60
40
20

0

260

123456789101112

Solder Reflow Temperature Profile
(Gull Wing Surface Mount Option 300 Parts)

Insulation and Safety Related Specifications

Parameter Symbol Value Units Conditions

Minimum External L(101) 7.1 mm Measured from input terminals to output
Air Gap (External terminals, shortest distance through air.
Clearance)

Minimum External L(102) 7.4 mm Measured from input terminals to output
Tracking (External terminals, shortest distance path along body.
Creepage)

Minimum Internal 0.08 mm Through insulation distance, conductor to
Plastic Gap conductor, usually the direct distance between the
(Internal Clearance) photoemitter and photodetector inside the

optocoupler cavity.

Tracking Resistance CTI 200 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative
Tracking Index)

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Option 300 - surface mount classification is Class A in accordance with CECC 00802.

Regulatory Information

The HCPL-24XX has been
approved by the following
organizations:

VDE

Approved according to VDE
0884/06.92 (Option 060 only).

UL

Recognized under UL 1577,
Component Recognition
Program, File E55361.

CSA

Approved under CSA Component
Acceptance Notice #5, File CA

88324.

1-304

VDE 0884 Insulation Related Characteristics
(HCPL-2400 OPTION 060 ONLY)

Description Symbol Characteristic Units

Installation classification per DIN VDE 0110/1.89, Table 1

for rated mains voltage ≤ 300 V rms I-IV
for rated mains voltage ≤ 450 V rms I-III

Climatic Classification 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage V

IORM

630 V peak

Input to Output Test Voltage, Method b*

V

IORM

x 1.875 = VPR, 100% Production Test with tm = 1 sec, V

PR

1181 V peak

Partial Discharge < 5 pC

Input to Output Test Voltage, Method a*

V

IORM

x 1.5 = VPR, Type and sample test, V

PR

945 V peak

tm = 60 sec, Partial Discharge < 5 pC

Highest Allowable Overvoltage*
(Transient Overvoltage, t

ini

= 10 sec) V

IOTM

6000 V peak

Safety Limiting Values

(Maximum values allowed in the event of a failure,
also see Figure 12, Thermal Derating curve.)

Case Temperature T

S

175 °C

Input Current I

S,INPUT

230 mA

Output Power P

S,OUTPUT

600 mW

Insulation Resistance at TS, VIO = 500 V R

S

≥ 10

9

Ω

*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section (VDE 0884) for a
detailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must ben ensured by protective circuits
in application.

1-305

Absolute Maximum Ratings

(No derating required up to 70°C)

Parameter Symbol Minimum Maximum Units Note

Storage Temperature T

S

-55 125 °C

Operating Temperature T

A

-40 85 °C

Average Forward Input Current I

F(AVG)

10 mA

Peak Forward Input Current I

FPK

20 mA 12

Reverse Input Voltage V

R

2V

Three State Enable Voltage V

E

-0.5 10 V

(HCPL-2400 Only)
Supply Voltage V

CC

07V

Average Output Collector Current I

O

-25 25 mA

Output Collector Voltage V

O

-0.5 10 V

Output Voltage V

O

-0.5 18 V

Output Collector Power Dissipation P

O

40 mW

(Each Channel)
Total Package Power Dissipation P

T

350 mW

(Each Channel)
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane

(for Through Hole Devices)
Reflow Temperature Profile See Package Outline Drawings section

(Option #300)

Recommended Operating Conditions

Parameter Symbol Minimum Maximum Units

Power Supply Voltage V

CC

4.75 5.25 V

Forward Input Current (ON) I

F(ON)

48mA

Forward Input Voltage (OFF) V

F(OFF)

0.8 V
Fan Out N 5 TTL Loads
Enable Voltage (Low) V

EL

0 0.8 V

HCPL-2400 Only)
Enable Voltage (High) V

EH

2VCCV

HCPL-2400 Only)
Operating Temperature T

A

070°C

1-306

Electrical Specifications

0°C ≤ TA ≤ 70°C, 4.75 V ≤ VCC ≤ 5.25 V, 4 mA ≤ I

F(ON)

≤ 8 mA, 0 V ≤ V

F(OFF)

≤ 0.8 V. All typicals at TA=25°C,

VCC = 5 V, I

F(ON)

= 6.0 mA, V

F(OFF)

= 0 V, except where noted. See Note 11.

Device

Parameter Symbol HCPL- Min. Typ.* Max. Units Test Conditions Fig. Note

Logic Low Output Voltage V

OL

0.5 V IOL = 8.0 mA (5 TTL Loads) 1

Logic High Output V

OH

2.4 V IOH = -4.0 mA 2

Voltage 2.7 IOH = -0.4 mA
Output Leakage Current I

OHH

100 µAVO = 5.25 V, VF = 0.8 V

Logic High Enable Current V

EH

2400 2.0 V

Logic Low Enable Voltage V

EL

2400 0.8 V

Logic High Enable I

EH

2400 20 µAVE = 2.4 V

100 VE = 5.25 V

Logic Low Enable Current I

EL

2400 -0.28 -0.4 mA VE = 0.4 V

Logic Low Supply Current I

CCL

2400 19 26 mA VCC = 5.25 V, VE = 0 V,

IO = Open

2430 34 46 VCC = 5.25 V, IO = Open

Logic High Supply I

CCH

2400 17 26 mA VCC = 5.25 V, VE = 0 V,

Current I

O

= Open

2430 32 42 VCC = 5.25 V, IO = Open

High Impedance State I

CCZ

2400 22 28 mA VCC = 5.25 V, VE = 5.25 V

Supply Current
High Impedance State I

OZL

2400 20 µAVO = 0.4 V VE = 2 V

I

OZH

20 µAVO = 2.4 V

I

OZH

100 µAVO = 5.25 V

Logic Low Short Circuit I

OSL

52 mA VO = VCC = 5.25 V, 2

Output Current IF = 8 mA
Logic High Short Circuit I

OSH

-45 mA VCC = 5.25 V, IF = 0 mA, 2

Output Current VO = GND
Input Current Hysteresis I

HYS

0.25 mA VCC = 5 V 3

Input Forward Voltage V

F

1.1 1.3 1.5 TA = 25°CIF = 8 mA

1.0 1.55 4

Input Reverse Breakdown BV

R

3.0 5.0 V TA = 25°CIR = 10 µA

2.0

Temperature ∆V

F

-1.44 mV/°CIF = 6 mA 4

Coefficient of
Forward Voltage

Input Capacitance C

IN

20 pF f = 1 MHz, VF = 0 V

*All typical values at TA = 25°C and VCC = 5 V, unless otherwise noted.

Current

Output Current

Voltage

∆T

A

1-307

Switching Specifications

0°C ≤ TA ≤ 70°C, 4.75 V ≤ VCC ≤ 5.25 V, 4 mA ≤ I

F(ON)

≤ 8 mA, 0 V ≤ V

F(OFF)

≤ 0.8 V. All typicals at TA = 25°C,

VCC = 5 V, I

F(ON)

= 6.0 mA, V

F(OFF)

= 0 V, except where noted. See Note 11.

Device

Parameter Symbol HCPL- Min. Typ.* Max. Units Test Conditions Figure Note

Propagation Delay t

PHL

55 ns I

F(ON)

= 7 mA 5, 6, 7 1, 4,
Time to Logic Low 5, 6
Output Level 15 33 60

Propagation Delay t

PLH

55 ns I

F(ON)

= 7 mA 5, 6, 7 1, 4,
Time to Logic High 5, 6
Output Level 15 30 60

Pulse Width |t

PHL-tPLH

|215nsI

F(ON)

= 7 mA 5, 8 6
Distortion

525

Propagation Delay t

PSK

35 ns Per Notes & Text 15, 16 7

Skew
Output Rise Time t

r

20 ns 5

Output Fall Time t

f

10 ns 5

Output Enable Time t

PZH

2400 15 ns 9, 10

to Logic High
Output Enable Time t

PZL

2400 30 ns 9, 10

to Logic Low
Output Disable Time t

PHZ

2400 20 ns 9, 10

from Logic High
Output Disable Time t

PLZ

2400 15 ns 9, 10

from Logic Low
Logic High Common |CM

H

| 1000 10,000 V/µsVCM = 300 V, TA = 25°C, 11 9

Mode Transient I

F

= 0 mA

Immunity
Logic Low Common |CM

L

| 1000 10,000 V/µsVCM = 300 V, TA = 25°C, 11 9

Mode Transient I

F

= 4 mA

Immunity
Power Supply Noise PSNI 0.5 V

p-p

VCC = 5.0 V, 10

Immunity 48 Hz ≤ = F

AC

≤ 50 MHz

*All typical values at TA = 25°C and VCC = 5 V, unless otherwise noted.

1-308

Package Characteristics

Parameter Sym. Device Min. Typ.* Max. Units Test Conditions Fig. Note

Input-Output V

ISO

2500 V rms RH ≤ 50%, 3, 13

Momentary t = 1 min.,
Withstand Voltage** TA = 25°C

Input-Output R

I-O

10

12

Ω V

I-O

= 500 Vdc 3

Resistance
Input-Output C

I-O

0.6 pF f = 1 MHz

Capacitance V

I-O

= 0 Vdc

Input-Input I

I-I

2430 0.005 µA RH ≤ 45% 8

Insulation Leakage t = 5 s,
Current V

I-I

= 500 Vdc

Resistance R

I-I

2430 10

11

Ω V

I-I

= 500 Vdc 8

(Input-Input)
Capacitance C

I-I

2430 0.25 pF f = 1 MHz 8

(Input-Input)

*All typical values are at TA = 25°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.

Notes:

1. Each channel.

2. Duration of output short circuit time
not to exceed 10 ms.

3. Device considered a two terminal
device: pins 1, 2, 3, and 4 shorted
together, and pins 5, 6, 7, and 8
shorted together.

4. t

PHL

propagation delay is measured
from the 50% level on the rising edge
of the input current pulse to the 1.5 V
level on the falling edge of the output
pulse. The t

PLH

propagation delay is
measured from the 50% level on the
falling edge of the input current pulse
to the 1.5 V level on the rising edge of
the output pulse.

5. The typical data shown is indicative of
what can be expected using the
application circuit in Figure 13.

6. This specification simulates the worst
case operating conditions of the
HCPL-2400 over the recommended
operating temperature and V

CC

range
with the suggested application circuit
of Figure 13.

7. Propagation delay skew is discussed
later in this data sheet.

8. Measured between pins 1 and 2
shorted together, and pins 3 and 4
shorted together.

9. Common mode transient immunity in a
Logic High level is the maximum
tolerable (positive) dVCM/dt of the
common mode pulse, VCM, to assure
that the output will remain in a Logic
High state (i.e., VO > 2.0 V. Common
mode transient immunity in a Logic
Low level is the maximum tolerable
(negative) dVCM/dt of the common
mode pulse, VCM, to assure that the
output will remain in a Logic Low state
(i.e., VO < 0.8 V).

10. Power Supply Noise Immunity is the
peak to peak amplitude of the ac ripple
voltage on the VCC line that the device
will withstand and still remain in the
desired logic state. For desired logic
high state, V

OH(MIN

) > 2.0 V, and for
desired logic low state,
V

OL(MAX)

< 0.8 V.

11. Use of a 0.1 µF bypass capacitor

connected between pins 8 and 5
adjacent to the device is required.

12. Peak Forward Input Current pulse

width < 50 µs at 1 KHz maximum
repetition rate.

13. In accordance with UL 1577, each
optocoupler is proof tested by applying
an insulation test voltage ≥ 3000 V rms
for one second (leakage detection
current limit, I

I-O

≤ 5 µA). This test is

performed before the 100% Produc­tion test shown in the VDE 0884
Insulation Related Characteristics
Table, if applicable.

1-309

Figure 4. Typical Diode Input Forward
Current Characteristic.

Figure 6. Typical Propagation Delay
vs. Ambient Temperature.

Figure 7. Typical Propagation Delay
vs. Input Forward Current.

Figure 8. Typical Pulse Width Distortion
vs. Ambient Temperature.

Figure 5. Test Circuit for t

PLH

, t

PHL

, tr, and tf.

Figure 1. Typical Logic Low Output
Voltage vs. Logic Low Output Current.

Figure 2. Typical Logic High Output
Voltage vs. Logic High Output Current.

Figure 3. Typical Output Voltage vs.
Input Forward Current.

1-310

Figure 9. Test Circuit for t

PHZ

, t

PZH

, t

PLZ

and t

PZL

.

Figure 10. Typical Enable Propagation
Delay vs. Ambient Temperature.

Figure 11. Test Diagram for Common Mode Transient Immunity
and Typical Waveforms.

Figure 12. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per VDE 0884.

OUTPUT POWER – P

S

, INPUT CURRENT – I

S

0

0

TS – CASE TEMPERATURE – °C

20050

400

12525 75 100 150

600

800

200
100

300

500

700

PS (mW)
I

S

(mA)

175

0.1 µF *

V

FF

+

–

F

I

CC

V

GND

NC

NC

CM

V

+

–

7

5

6

8

2

3

4

1

C = 15 pF

A

B

PULSE GENERATOR

L

CC

V

OUTPUT V
MONITORING NODE

O

HCPL-2400/11

†

1-311

Figure 15. Illustration of Propagation Delay Skew – t

PSK

.

50%

1.5 V

I

F

V

O

50%I

F

V

O

t

PSK

1.5 V

Figure 13. Recommended 20 MBd HCPL-2400/30 Interface Circuit.

Applications

Figure 14. Alternative HCPL-2400/30
Interface Circuit.

Figure 16. Parallel Data Transmission Example.

Figure 17. Modulation Code Selections. Figure 18. Typical HCPL-2400/30 Output Schematic.

DATA

t

PSK

INPUTS

CLOCK

DATA

OUTPUTS

CLOCK

t

PSK

HCPL-2400

HCPL-2400

V

1-312

Propagation Delay, Pulse­Width Distortion and
Propagation Delay Skew

Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga­tion delay from low to high (t

PLH

)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (t

PHL

) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low (see
Figure 5).

Pulse-width distortion (PWD)
results when t

PLH

and t

PHL

differ in
value. PWD is defined as the
difference between t

PLH

and t

PHL

and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being
transmitted. Typically, PWD on
the order of 20-30% of the
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-1, etc.).

Propagation delay skew, t

PSK

, is
an important parameter to
consider in parallel data applica­tions where synchronization of
signals on parallel data lines is a
concern. If the parallel data is
being sent through a group of
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of the
optocouplers at different times. If
this difference in propagation
delays is large enough, it will

determine the maximum rate at
which parallel data can be sent
through the optocouplers.

Propagation delay skew is defined
as the difference between the
minimum and maximum propaga­tion delays, either t

PLH

or t

PHL

, for
any given group of optocouplers
which are operating under the
same conditions (i.e., the same
drive current, supply voltage,
output load, and operating tem­perature). As illustrated in
Figure 15, if the inputs of a group
of optocouplers are switched
either ON or OFF at the same
time, t

PSK

is the difference
between the shortest propagation
delay, either t

PLH

or t

PHL

, and the
longest propagation delay, either
t

PLH

or t

PHL

.

As mentioned earlier, t

PSK

can
determine the maximum parallel
data transmission rate. Figure 16
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
signals at the inputs and outputs of
the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signals
are being used to clock the data;
if only one edge were used, the
clock signal would need to be
twice as fast.

Propagation delay skew repre­sents the uncertainty of where an
edge might be after being sent
through an optocoupler.
Figure 16 shows that there will be
uncertainty in both the data and
the clock lines. It is important
that these two areas of uncertainty
not overlap, otherwise the clock
signal might arrive before all of

the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice t

PHZ

.
A cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.

The HCPL-2400/30 optocouplers
offer the advantages of guaran­teed specifications for propaga­tion delays, pulse-width distortion,
and propagation delay skew over
the recommended temperature,
input current, and power supply
ranges.

Application Circuit

A recommended LED drive circuit
is shown in Figure 13. This circuit
utilizes several techniques to
minimize the total pulse-width
distortion at the output of the
optocoupler. By using two
inverting TTL gates connected in
series, the inherent pulse-width
distortion of each gate cancels the
distortion of the other gate. For
best results, the two series­connected gates should be from
the same package.

The circuit in Figure 13 also uses
techniques known as prebias and
peaking to enhance the
performance of the optocoupler
LED. Prebias is a small forward
voltage applied to the LED when
the LED is off. This small prebias
voltage partially charges the
junction capacitance of the LED,
allowing the LED to turn on more
quickly. The speed of the LED is
further increased by applying

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momentary current peaks to the
LED during the turn-on and turn­off transitions of the drive
current. These peak currents help
to charge and discharge the
capacitances of the LED more
quickly, shortening the time
required for the LED to turn on
and off.

Switching performance of the
HCPL-2400/30 optocouplers is
not sensitive to the TTL logic
family used in the recommended
drive circuit. The typical and
worst-case switching parameters
given in the data sheet can be met
using common 74LS TTL invert­ing gates or buffers. Use of faster
TTL families will slightly reduce
the overall propagation delays
from the input of the drive circuit

to the output of the optocoupler,
but will not necessarily result in
lower pulse-width distortion or
propagation delay skew. This
reduction in overall propagation
delay is due to shorter delays in
the drive circuit, not to changes in
the propagation delays of the
optocoupler; optocoupler prop­agation delays are not affected by
the speed of the logic used in the
drive circuit.