700ns, Low Distortion, Precision Sample
and Hold Amplifier
The HA-5340 combines the advantages of two sample/ hold
architectures to create a new generation of monolithic
sample/hold. High amplitude, high frequency signals can be
sampled with very low distortion being introduced. The
combination of exceptionally fast acquisition time and
specified/characterized hold mode distortion is an industry
first. Additionally, the AC performance is only minimally
affected by additional hold capacitance.
To achieve this level of performance, the benefits of an
integrating output stage have been combined with the
advantages of a buff ered hold capacitor. To the user this
translates to a front-endstagethat has high bandwidth due to
charging only a small capacitive load and an output stage with
constant pedestal error which can be nulled out using the
offset adjust pins. Since the performance penalty for
additional hold capacitance is low , the designer can further
minimize pedestal error and droop rate without sacrificing
speed.
Low distortion, fast acquisition, and low droop rate are the
result, making the HA-5340 the obvious choice for high
speed, high accuracy sampling systems. For a Military
temperature range version request the HA-5340/883 data
sheet.
Ordering Information
TEMP.
PART NUMBER
RANGE (oC)PACKAGE
HA3-5340-50 to 7514 Ld PDIPE14.3
HA9P5340-50 to 7516 Ld SOICM16.3
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . ±12V to ±18V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation must be designed to maintain the junction temperature below 150oC for the plastic packages.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
3. Derived from Computer Simulation only, not tested.
4. +CMRR is measured from 0V to +10V, -CMRR is measured from 0V to -10V.
5. Based on the calculation FPBW = Slew Rate/2πV
PEAK
(V
PEAK
= 10V).
Test Circuits and Waveforms
1
S/H
CONTROL
INPUT
-INPUT
2
+INPUT
14
S/H CONTROL
HA-5340
OUTPUT
(CH = 135pF = INTERNAL)
FIGURE 1. HOLD STEP ERROR AND DROOP RATE
7
11
NC
V
O
S/H CONTROL
V
O
NOTE:
6. Observe the “hold step” voltage V
FIGURE 2. HOLD STEP ERRORFIGURE 3. DROOP RATE TEST
ANALOG
MUX OR
SWITCH
A
IN
20V
P-P
200kHz
SINE WAVE
S/H CONTROL
INPUT
V
IN
HOLD (+4.0V)
SAMPLE (0V)
∆V
O
HOLD (+4.0V)
SAMPLE (0V)
S/H CONTROL
V
O
∆t
NOTES:
7. Observe the voltage “droop”, ∆VO/∆t.
V
P
8. Measure the slope of the output during hold, ∆VO/∆t.
9. Droopcan be positive or negative-usually to one rail or theother
P.
HA-5340
95
1
-IN
2
+IN
14
S/H
CONTROL
SUPPLY
GND
136
TO
SUPPLY
COMMON
not to GND.
V-V+
REF
COM
TO
SIGNAL
GND
OUT
NOTE:
10. Feedthrough in
V
OUT
7
dB20
V
OUT=VP-P
V
= V
IN
log=
P-P
V
OUT
-------------- -
where:
V
IN
, Hold Mode,
FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
4
Page 5
HA-5340
Application Information
The HA-5340 has the uncommitted differential inputs of an op
amp, allowing the Sample and Hold function to be combined
with many conventional op amp circuits . See the Intersil
Application Note AN517 for a collection of circuit ideas.
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01µF to 0.1µF,
ceramic) should be provided from each power supply
terminal to the Supply Ground terminal on pin 13.
The ideal ground connections are pin 6 (SIG. GND) directly
to the system Signal Ground, and pin 13 (Supply Ground)
directly to the system Supply Common.
Hold Capacitor
The HA-5340 includes a 135pF MOS hold capacitor,
sufficient for most high speed applications (the Electrical
Specifications section is based on this internal capacitor).
Additional capacitance may be added between pins 7 and
11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.
The hold capacitor C
resistance and low dielectric absorption, to minimize droop
errors. Teflon®, polystyrene and polypropylene dielectric
should have high insulation
H
capacitor types offer good performance over the specified
operating temperature range.
The hold capacitor terminal (pin 11) remains at virtual
ground potential. Any PC connection to this terminal should
be kept short and “guarded” by the ground plane, since
nearby signal lines or power supply voltages will introduce
errors due to drift current.
®Teflon is a registered Trademark of Dupont Corporation.
Typical Application
Figure 5 shows the HA-5340 connected as a unity gain
noninverting amplifier - its most widely used configuration.
As an input device for a fast successive - approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5340’s hold step error
is adjustable to zero using the Offset Adjust potentiometer,
to deliver a 12-bit accurate output from the converter.
The HA-5340 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
V
S/H CONTROL
H
S
-
+15V
15V
OFFSET
ADJUST
≈ ±15mV
50kΩ
3495
1
IN
FIGURE 5. TYPICAL HA-5340 CONNECTIONS; NONINVERTING UNITY GAIN MODE
2
14
HA 5340-
136
SYSTEM
POWER
GROUND
SYSTEM
SIGNAL
GROUND
C
H
11
HI 774-
120pF
15pF
7
CONVERT
13
INPUT
5
R/
C
9
ANALOG
COMMON
NOTE: Pin Numbers Refer to
DIP Package Only.
DIGITAL
OUTPUT
5
Page 6
HA-5340
Typical Performance Curves T
S/H
CONTROL
V
OUT
FIGURE 6. T
4V
0V
POS 0 TO +10 STEPFIGURE 7. T
ACQ
A
30
28
26
24
22
20
18
16
14
12
10
8
DROOP RATE (µV/µs)
6
4
75oC
2
0
1101001000
100oC
EXTERNAL HOLD CAPACITANCE (pF)
= 25oC, VS = ±15V, Unless Otherwise Specified
S/H
0V
10V
125oC
CONTROL
V
OUT
2300
2100
1900
1700
1500
1300
1100
900
ACQUISITION TIME TO±1mV (ns)
700
04008001200160020002400
4V
0V
0pF
470pF
1000pF
vs ADDITIONAL C
ACQ
2200pF
H
EXTERNAL HOLD CAPACITANCE (pF)
FIGURE 8. DROOP RATE vs HOLD CAPACITANCEFIGURE 9. ACQUISITION TIME (0.01%) vs HOLD CAPACITANCE
13
CH = INTERNAL
12
TEMPERATURE = 25
11
o
C
10
9
8
7
6
VIH = 3V
5
4
3
HOLD STEP ERROR (mV)
2
1
0
5101520
T
RISE
(ns)
FIGURE 10. HOLD STEP ERROR vs T
VIH = 4V
RISE
20
VIH= 4V
C
= 470pF
H
10
0
HOLD STEP ERROR (mV)
-10
-55-35-150255075100125
o
TEMPERATURE (
C)
FIGURE 11. HOLD STEP ERROR vs TEMPERATURE
6
Page 7
HA-5340
Typical Performance Curves T
14
T
= 5ns
RISE
TA = 25oC
12
10
8
6
HOLD STEP ERROR (mV)
4
2
02004006008001000
EXTERNAL HOLD CAPACITANCE (pF)
VIH = 4V
= 25oC, VS = ±15V, Unless Otherwise Specified (Continued)
A
20
VIH = 4V, CH = INTERNAL
= 5ns, 10ns, 20ns
t
R
10
0
HOLD STEP ERROR (mV)
-10
-55-35-150255075100125
TEMPERATURE (
5ns
10ns
20ns
o
C)
FIGURE 12. HOLD STEP ERROR vs HOLD CAPACITANCEFIGURE 13. HOLD STEP ERROR vs TEMPERATURE
40
20
MAGNITUDE (dB)
0
AV = +100, ±15V AND
±12V SUPPLIES (NOTE)
1K10K100K1M10M
MAGNITUDE
PHASE
180
90
0
-90
PHASE ANGLE (DEGREES)
-180
40
20
MAGNITUDE (dB)
0
CH = 1000pF
C
= 470pF
H
= 0pF
C
H
CH = 1000pF
= 470pF
C
H
C
= 0pF
H
MAGNITUDE
PHASE
AV = +100
NOTE: ±15V and ±12V supplies tracethesame line within
the width of the line, therefore only one line is shown.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly , the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
8
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