Datasheet HA-5320-883 Datasheet (Intersil Corporation)

HA5320/883

July 1994

High Speed Precision Sample and Hold Amplifier

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Gain, DC . . . . . . . . . . . . . . . . . . . . . . . . 2 x 10

6

V/V (Typ)

• Acquisition Time . . . . . . . . . . . . . . . 1.0µs (0.01%) (Typ)

• Droop Rate . . . . . . . . . . . . . . . . 0.08µV/µs (+25oC) (Typ)

17µV/µs (Full Temperature) (Typ)

• Aperture Time. . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Typ)

• Hold Step Error . . . . . . . . . . . . . . . . . . . . . . 1.0mV (Typ)

• Internal Hold Capacitor

• Fully Differential Input

• TTL Compatible

Applications

• High Bandwidth Precision Data Acquisition Systems

• Inertial Navigation and Guidance Systems

• Ultrasonics

• SONAR / RADAR

• Digital to Analog Converter Deglitcher

Description

The HA-5320/883 was designed for use in precision, high speed
data acquisition systems.

The circuit consists of an input transconductance amplifier
capable of providing large amounts of charging current, a low
leakage analog switch, and an output integrating amplifier. The
analog switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire input/
output voltage range. The pedestal voltage resulting from this
charge injection can be adjusted to zero by use of the offset
adjust inputs. The device includes a hold capacitor. However, if
improved droop rate is required at the expense of acquisition
time, additional hold capacitance may be added externally.

This monolithic device is manufactured using the Intersil
Dielectric Isolation Process, minimizing stray capacitance and
eliminating SCR’s. This allows higher speed and latch-free
operation. For further information, please see Application Note
AN538.

Pinouts

HA-5320/883 (CERDIP)

Ordering Information

TOP VIEW

-INPUT

+INPUT
OFFSET ADJ
OFFSET ADJ

SIG GND

OUTPUT

V-

1
2
3
4
5
6
7

S/H CONTROL

14

SUPPLY GND

13

NC

12

C

11

EXT

10

NC
V+

9

INT. BW

8

PART NUMBER

HA1-5320/883 -55oC to +125oC 14 Lead CerDIP
HA4-5320/883 -55oC to +125oC 20 Lead Ceramic LCC

Functional Diagram

HA-5320/883 (CLCC)

TOP VIEW

-INPUT

1

S/H

2

14

+INPUT

CNTL

S/H

SUPPLY GND

NC

-IN

+IN

3212019

18

NC

17

NC

16

C

EXT

15

NC

14

NC

13

V+

INT. BW

| Copyright © Intersil Corporation 1999

CONTROL

7-3

NC

NC

V-

4
5
6
7
8

9101112

SIG

GND

OUTPUT

NC

OFFSET ADJ

OFFSET ADJ

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

TEMPERATURE

RANGE PACKAGE

OFFSET
ADJUST

3 4

13

SUPPLY

GND

HA-5320/883

5 86

V-

11

C

EXT

V+

SIG

GND

9

100pF

-

+

INTEGRATOR
BANDWIDTH

Spec Number 51 1096-883

File Number 2927.3

7

OUTPUT

Specifications HA-5320/883

Absolute Maximum Ratings Thermal Information

Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . . 40V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V

Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . .+8V, -15V

Output Current, Continuous (Note 1) . . . . . . . . . . . . . . . . . . . . .±20mA

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Temperature Range. . . . . . . . . . . . .-55oC ≤ TA≤ +125oC

Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V

Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10V

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH= Internal = 100pF; Signal GND = Supply GND,

Unless Otherwise Specified

Thermal Resistance θ

JA

θ

JC

CerDIP Package . . . . . . . . . . . . . . . . . . . 66oC/W 16oC/W

Ceramic LCC Package . . . . . . . . . . . . . . 57oC/W 9oC/W

Package Power Dissipation at +75oC

CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.75W

Package Power Dissipation Derating Factor Above +75oC

CerDip Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mW/oC

Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . 17mW/oC

Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V

Logic Level High (VIH). . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V

PARAMETERS SYMBOL CONDITIONS

Input Offset Voltage V

Input Bias Current +I

Input Offset Current I

Open Loop Voltage Gain +A

Common Mode
Rejection Ratio

IO

B

-I

B

IO

RL = 1kΩ, V

VS

-A

VS

RL = 1kΩ, V

+CMRR V+ = 10V, V- = -20V,

V

= -5V, V

OUT

V

= -5V

GND

-CMRR V+ = 20V, V- = -10V,
V

= +5V, V

OUT

V

= +5V

GND

Output Current +I

V

O

= +10V 1 +25oC10-mA

OUT

GROUP A

LIMITS

SUBGROUP TEMPERATURE

1 +25oC −1 +1mV

2, 3 +125oC, -55oC −2 + 2mV

1 +25oC −200 +200 nA

2, 3 +125oC, -55oC −200 +200 nA

1 +25oC −200 +200 nA

2, 3 +125oC, -55oC −200 +200 nA

1 +25oC −100 +100 nA

2, 3 +125oC, -55oC −100 +100 nA

= +10V 1 +25oC 120 - dB

OUT

2, 3 +125oC, -55oC 110 - dB

= -10V 1 +25oC 120 - dB

OUT

2, 3 +125oC, -55oC 110 - dB

1 +25oC80-dB

= -4.2V,

S/H

2, 3 +125oC, -55oC80 - dB

1 +25oC80-dB

= 5.8V,

S/H

2, 3 +125oC, -55oC80 - dB

2, 3 +125oC, -55oC10 - mA

UNITSMIN MAX

-I

V

O

= -10V 1 +25oC -10 - mA

OUT

2, 3 +125oC, -55oC -10 - mA

CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.

7-4

Spec Number 51 1096-883

Specifications HA-5320/883

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Tested at: V+ = +15V; V- = -15V; VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH= Internal = 100pF; Signal GND = Supply GND,

Unless Otherwise Specified

PARAMETERS SYMBOL CONDITIONS

Output Voltage Swing +V

-V

Power Supply Current +I

Power Supply Rejection

+PSRR V+ = 14.5V, 15.5V

Ratio

-I

CC

RL = 1kΩ 1 +25oC10-V

OP

RL = 1kΩ 1 +25oC - -10 V

OP

V

CC

= 0V, I

OUT

V

= 0V, I

OUT

V- = -15V, -15V

-PSRR V+ = +15V, +15V,
V- = -14.5V, -15.5V

Digital Input Current I

I

INL

INH

VIN = 0V 1 +25oC-4µA

VIN = 5V 1 +25oC - 0.1 µA

GROUP A

LIMITS

SUBGROUP TEMPERATURE

2, 3 +125oC, -55oC10 - V

2, 3 +125oC, -55oC - -10 V

= 0mA 1 +25oC - 13 mA

OUT

2, 3 +125oC, -55oC - 13 mA

= 0mA 1 +25oC -13 - mA

OUT

2, 3 +125oC, -55oC -13 - mA

1 +25oC80-dB

2, 3 +125oC, -55oC80 - dB

1 +25oC65-dB

2, 3 +125oC, -55oC65 - dB

2, 3 +125oC, -55oC- 10µA

2, 3 +125oC, -55oC - 0.1 µA

UNITSMIN MAX

Digital Input Voltage V

Output Voltage Droop

IL

V

IH

V

V

D

= 0V 2 +125oC - 100 µV/µs

OUT

Rate

NOTE:

1. Internal power dissipation may limit output current below 20mA.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

Table 2 Intentionally Left Blank. See AC Specifications in Table 3.

1 +25oC - 0.8 V

2, 3 +125oC, -55oC - 0.8 V

1 +25oC 2.0 - V

2, 3 +125oC, -55oC 2.0 - V

CAUTION: These devices are sensitive to electronic discharge. Proper IC handling procedures should be followed.

7-5

Spec Number 51 1096-883

Specifications HA-5320/883

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE

Hold Mode Feedthrough V

Hold Step Error V

Sample Mode Noise

HMF

ERRORVIH

E

N(SAMPLE)

Voltage

Hold Mode Noise

E

N(HOLD)

Voltage

Input Capacitance C

Input Resistance R

Slew Rate +SR CL = 50pF, RL = 2kΩ,

IN

IN

VIN = 10V

= 3.5V, VIL = 0V,

T

RISE

DC to 10MHz, V
R

LOAD

DC to 10MHz, V
R

LOAD

V

= 0V 1 +25oC-5pF

S/H

V

= 0V, Delta VIN = 20V 1 +25oC1-MΩ

S/H

, 100kHz 1 +25oC-3mV

P-P

1 +25oC -11 11 mV

(VIL to VIH) = 10ns

S/H

= 0V,

1 +25oC - 200 µV

= 2kΩ

S/H

= 5V,

1 +25oC - 200 µV

= 2kΩ

1 +25oC30-V/µs

V

= -5V to +5V Step

OUT

10%, 90% pts

-SR CL = 50pF, RL = 2kΩ,
V

= +5V to -5V Step

OUT

1 +25oC30-V/µs

10%, 90% pts

Rise and Fall Times T

CL = 50pF, RL = 2kΩ,

R

V

OUT

1 +25oC - 150 ns

= 0V to +200mV Step

10%, 90% pts

UNITSMIN MAX

RMS

RMS

T

CL = 50pF, RL = 2kΩ,

F

V

OUT

1 +25oC - 150 ns

= 0V to -200mV Step

10%, 90% pts

Overshoot +OS CL = 50pF, RL = 2kΩ,

V

= 0V to +200mV Step

OUT

-OS CL = 50pF, RL = 2kΩ,
V

= 0V to -200mV Step

OUT

0.1% Acquisition Time T

0.1% CL = 50pF, RL = 2kΩ,

ACQ

V

= 0V to 10V Step

OUT

1 +25oC - 25 %

1 +25oC - 25 %

1 +25oC - 1.2 µs

NOTE:

1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.

TABLE 4. ELECTRICAL TEST REQUIREMENTS

MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1)

Interim Electrical Parameters (Pre Burn-In) -

Final Electrical Test Parameters 1(Note 1), 2, 3

Group A Test Requirements 1, 2, 3

Groups C and D Endpoints 1

NOTE:

1. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.

7-6

Spec Number 51 1096-883

Die Characteristics

DIE DIMENSIONS:

92 x 152 x 19 ± 1mils

METALLIZATION:

Type: Al, 1% Cu
Thickness: 16k

Å ±2kÅ

GLASSIVATION:

Type: Nitride (Si
Silox Thickness: 12k

) over Silox (SiO2, 5% Phos)

3N4

Å ± 2kÅ

Nitride Thickness: 3.5kÅ ± 1.5kÅ

WORST CASE CURRENT DENSITY:

1.742 x 10

5

A/cm

2

TRANSISTOR COUNT: 184
SUBSTRATE POTENTIAL: V-

Metallization Mask Layout

HA-5320/883

HA-5320/883

S/H CTRL (14)

-INPUT (1)

+INPUT (2)

SUPPL Y GND

(3)

C

EXT

(4)

ADJVIO ADJ

V

IO

(5)
V-

V+
(9)(11)(13)

(8) INT BW

(7) OUTPUT

(6) SIG GND

7-7

Spec Number 51 1096-883

Burn-In Circuits

HA-5320/883

HA-5320/883 DIP BURN-IN/LIFE TEST CIRCUIT

1

2

R

1

-V
D

2

C

2

3

4

5

6

7

14

13

12

11

10

9

C

8

1

+V

D

1

HA-5320/883 LCC BURN-IN/LIFE TEST CIRCUIT

R

1

32120 19
4
5
6
7

-V
D

2

C

2

8

9 10111213

18
17
16
15
14

+V

C

1

D

1

NOTES:

1. R1 = 100kΩ, 5%, (per socket).

2. C1, C2 = 0.01µF minimum per socket or 0.1µF minimum per row.

3. D1, D2 = 1N4002 or equivalent (per board).

4. +V = +15.5V ±0.5V, -V = -15.5V ± 0.5V.

Spec Number 51 1096-883

7-8

HA-5320/883

Packaging

c1

LEAD FINISH

-A-

-B-

S

bbb C A - B

BASE

PLANE

SEATING

PLANE

S1
b2

ccc C A - BMD

D

A

A

b

e

S

S

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, andN/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b1.

5. This dimension allows for off-center lid, meniscus, and glass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling Dimension: Inch.

11. Materials: Compliant to MIL-I-38535.

-D­BASE

M

SECTION A-A

eA/2

METAL

b1

M

(b)

α

S

e

A

c

D

E

S

S

D

Q

A

-C­L

M

aaa C A - B

F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)

14 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE

(c)

SYMBOL

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3

D - 0.785 - 19.94 5

E 0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC ­eA 0.300 BSC 7.62 BSC -

S

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
S2 0.005 - 0.13 - -

α

aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2

N14 148

INCHES MILLIMETERS

90

o

105

o

90

o

105

NOTESMIN MAX MIN MAX

o

-

7-9

Spec Number 51 1096-883

HA-5320/883

Packaging

o

j x 45

B

o

h x 45

AA1

E1

E2

e1

(Continued)

L

L2

D3

D

D1

D2

B2

J20.A MIL-STD-1835 CQCC1-N20 (C-2)

20 PAD METAL SEAL LEADLESS CERAMIC CHIP CARRIER

INCHES MILLIMETERS

SYMBOL

A 0.060 0.100 1.52 2.54 6, 7

A1 0.050 0.088 1.27 2.23 7

E3

E

B----4
B1 0.022 0.028 0.56 0.71 2, 4
B2 0.072 REF 1.83 REF ­B3 0.006 0.022 0.15 0.56 -

D 0.342 0.358 8.69 9.09 ­D1 0.200 BSC 5.08 BSC ­D2 0.100 BSC 2.54 BSC ­D3 - 0.358 - 9.09 2

E 0.342 0.358 8.69 9.09 -

PLANE 2

PLANE 1

E1 0.200 BSC 5.08 BSC ­E2 0.100 BSC 2.54 BSC ­E3 - 0.358 - 9.09 2

e 0.050 BSC 1.27 BSC -

e

L3

e1 0.015 - 0.38 - 2

h 0.040 REF 1.02 REF 5

j 0.020 REF 0.51 REF 5

L 0.045 0.055 1.14 1.40 ­L1 0.045 0.055 1.14 1.40 ­L2 0.075 0.095 1.91 2.41 -

B1

B3

L3 0.003 0.015 0.08 0.38 -

ND 5 5 3
NE 5 5 3

N20 203

NOTES:

L1

1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.

2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.381mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)

3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.

4. The required plane 1 terminals and optional plane 2 terminals
shall be ellectrically connected.

5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.

6. Chip carriers shall be constructed of a minimum of two ceramic
layers.

7. Maximum limits allows for 0.007 inch solder thickness on pads.

8. Materials: Compliant to MIL-I-38535.

NOTESMIN MAX MIN MAX

7-10

Spec Number 51 1096-883

Semiconductor

HA5320

DESIGN INFORMATION

August 1999

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as applica­tion and design information only. No guarantee is implied.

Applying the HA-5320

errors. Polystyrene dielectric is a good choice for operating
temperatures up to +85

The HA-5320 has the uncommitted differential inputs of an

offer good performance to +125

Sample and Hold Amplifier

High Speed Precision

o

C. Teflon and glass dielectrics

o

C and above.

op amp, allowing the Sample and Hold function to be
combined with many conventional op amp circuits. See the
Intersil Application Note 517 for a collection of circuit ideas.

The hold capacitor terminal (pin 11) remains at virtual
ground potential. Any PC connection to this terminal should
be kept short and “guarded” by the ground plane, since

Layout

A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01 to 0.1µF,

nearby signal lines or power supply voltages will introduce
errors due to drift current.

Teflon is a registered Trademark of Dupont Corporation.

ceramic) should be provided from each power supply termi­nal to the Supply Ground terminal on pin 13.

The ideal ground connections are pin 6 (SIG. Ground)
directly to the system Signal Ground, and pin 13 (Supply
Ground) directly to the system Supply Common.

Hold Capacitor

The HA-5320 includes a 100pF MOS hold capacitor, suffi­cient for most high speed applications (the Electrical Specifi­cations section is based on this internal capacitor).
Additional capacitance may be added between pins 7 and

11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.

If an external hold capacitor C
band- width capacitor of value 0.1C

is used, then a noise

EXT

should be connected

EXT

from pin 8 to ground. Exact value and type are not critical.
The hold capacitor C

should have high insulation resis-

EXT

tance and low dielectric absorption, to minimize droop

Applications

Figure 1 shows the HA-5320 connected as a unity gain non­inverting amplifier – its most widely used configuration. As
an input device for a fast successive – approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the hold step error is adjust­able to zero using the Offset Adjust potentiometer, to deliver
a 12-bit accurate output from the converter.

The application may call for an external hold capacitor C
as shown. As mentioned earlier, 0.1C
mended at pin 8 to reduce output noise in the Hold mode.

The HA-5320 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load cur­rent which occur during an A/D conversion are absorbed at
the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.

is then recom-

EXT

EXT

OFFSET
ADJUST

±15mV

1
2

V

IN

S/H CONTROL

H

S

FIGURE 1. TYPICAL HA-5320/883 CONNECTIONS; NONINVERTING UNITY GAIN MODE

14

SYSTEM

POWER

GROUND

-15V +15V

10kΩ

C

100pF

-

+

EXT

0.1C

7

EXT

13

CONVERT

119543

-

+

HA-5320

13 6 8

SYSTEM

SIGNAL

GROUND

NOTE: Pin Numbers Refer to DIP Package Only.

INPUT

R/

5
9

ANALOG
COMMON

HI-574A

C

DIGITAL
OUTPUT

Spec Number 51 1096-883

7-11

HA-5320

DESIGN INFORMATION (Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as applica­tion and design information only. No guarantee is implied.

Test Circuits

CHARGE TRANSFER AND DRIFT CURRENT

S/H

CONTROL

INPUT

CHARGE TRANSFER TEST

1. Observe the “hold step” voltage Vp:

S/H CONTROL

V

O

V

2. Compute charge transfer: Q = VpC

1

-INPUT

2

+INPUT

14

S/H CONTROL

OUTPUT

HA-5320

(CH = 100pF)

7

8

N.C.

11

N.C.

V

O

DRIFT CURRENT TEST

1. Observe the voltage “droop”, ∆VO/∆T:

HOLD (+3.5V)
SAMPLE (0V)

p

H

S/H CONTROL

V

O

∆T

HOLD (4.0V)

SAMPLE (0V)

∆V

O

2. Measure the slope of the output during hold, ∆VO/∆T, and com-
pute drift current: ID = CH∆VO/∆T.

10V

p-p

100kHz

SINE WAVE

S/H CONTROL

V

INPUT

HOLD MODE FEED THROUGH ATTENUATION

-V+V

ANALOG

MUX OR

IN

SWITCH

A

IN

1

-IN

2

+IN

14

S/H CONTROL

SUPPLY

GND

13 11 6

TO

SUPPLY

COMMON

Feedthrough in dB = 20 Log V

V

= Volts

OUT

VIN = Volts

, Hold Mode,

p-p

.

p-p

HA-5320

95

REF

COM

TO

SIGNAL

GND

COMP.

OUT

V

IN

C

EXT

N.C.

where:

INT.

8

N.C.

OUT

V

OUT

7

Spec Number 51 1096-883

7-12

HA-5320

DESIGN INFORMATION (Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as applica­tion and design information only. No guarantee is implied.

Performance Curves

TYPICAL SAMPLE AND HOLD PERFORMANCE

AS FUNCTION OF HOLDING CAPACITOR DRIFT CURRENT vs TEMPERATURE

10

5

1.0

0.5

0.1

0.05

0.01
100 1000 10K 100K

CH VALUE (pF)

V

ACQUISITION TIME
FOR 10V STEP TO +0.01%(µs)

VOLTAGE DROOP
DURING HOLD MODE
(mV/100ms)

SAMPLE-TO-HOLD
OFFSET (HOLD STEP)
ERROR (mV)

SUPPLY

= ±15VDC

OPEN LOOP GAIN AND PHASE RESPONSE

120

100

1000

(pA)

DRIFT

I

C

= 100pF, INTERNAL

H

100

10

1.0

-25 0 +25 +50 +75 +100 +125
TEMPERATURE (oC)

0

80

60

GAIN (dB)

40

20

0

θ

G

(CH = 1100pF)

10 100 1K 10K 100K 1M 10M

FREQUENCY (Hz)

(CH = 100pF)

G

45

90

135

PHASE (DEGREES)

180

TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR

HOLD STEP vs. INPUT VOLTAGE HOLD STEP vs. LOGIC (VIH) VOLTAGE

2.0

HOLD STEP

VOLTAGE

(mV)

= +25oC

T

A

-10 -8 -6 -4 -2 2 10864

1.0

0.1

0.01

DC INPUT (V)

C

= 100pF

H

CH = 1000pF
C

= 0.01µF

H

1.5

1.0

0.5

HOLD STEP VOLTAGE (mV)

0.0

+25oC

234 5

LOGIC LEVEL HIGH (V)

C

= 100pF

H

+75oC

7-13

Spec Number 51 1096-883

HA-5320

DESIGN INFORMATION (Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as applica­tion and design information only. No guarantee is implied.

Glossary of Terms

Acquisition Time

The time required following a “sample” command, for the
output to reach its final value within ±0.1% or ±0.01%. This is
the minimum sample time required to obtain a given accu­racy, and includes switch delay time, slewing time and set­tling time.

Charge Transfer

The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly pro­portional to sample-to-hold offset pedestal error, where:

Charge Transfer (pC) = C

(pF) x Offset Error (V)

H

Aperture Time

The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.

Hold Step Error

Hold Step Error is the output error due to Charge Transfer
(see above). It may be calculated from Charge Transfer,
using the following relationship:

HOLD STEP (V) = CHARGE TRANSFER (pC)

HOLD CAPACITANCE (pF)

See Performance Curves.

Effective Aperture Delay Time (EADT)

The difference between propagation time from the analog
input to S/H switch, and digital delay time between the Hold
command and opening of the switch.

EADT may be positive, negative or zero. If zero, the
amplifier will output a voltage equal to V

at the instant the

IN

S/H

Hold command was received. For negative EADT, the output
in Hold (exclusive of pedestal and droop errors) will
correspond to a value of V

that occurred before the Hold

IN

command.

Aperture Uncertainty

The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay
Uncertainty, Aperture Time Jitter, etc.) sets a limit on the
accuracy with which a waveform can be reconstructed from
sample data.

Drift Current

The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:

I

(pA) = CH (pF) x ∆V (V/s)

D

∆T

TYPICAL PERFORMANCE CHARACTERISTICS

PARAMETER CONDITIONS TEMPERATURE TYP UNITS

Input Voltage Range Full ±10 V
Offset Voltage Drift Full 5 µV/oC
Gain Bandwidth Product (CH = 100pF) Av = +1, VO = 200mV
Gain Bandwidth Product (CH = 1000pF) Av = +1, VO = 200mV
Full Power Bandwidth VO = 20V
Output Resistance (Hold Mode) +25oC 1.0 Ω

0.1% Acquisition Time VO = 10V Step, RL = 2K, CL = 50pF +25oC 0.8 µs

0.01% Acquisition Time VO = 10V Step, RL = 2K, CL = 50pF +25oC 1.0 µs
Effective Aperture Delay Time +25oC -25 ns
Aperture Uncertainty +25oC 0.3 ns

0.01% Hold Mode Settling Time +25oC 165 ns

, RL = 2K, CL = 50pF +25oC 600 kHz

P-P

, RL = 2K, CL = 50pF +25oC 2 MHz

P-P

, RL = 2K, CL = 50pF +25oC 0.18 MHz

P-P

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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Spec Number 51 1096-883

7-14