Datasheet gm2125, gm2115 Datasheet (Genesis)

PRELIMINARY DATA SHEET

gm2115/25

Analog Interface XGA/SXGA OnPanel

LCD Panel Controller

*** Genesis Microchip Confidential ***

C2115-DAT-01B

June 2002

2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: [phone] Fax: [phone]

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1096, 12thA Main, Hal II Stage, Indira Nagar, Bangalore-560 008, India, Tel: [phone], Fax: [phone]

4F, No. 24, Ln 123, Sec 6, Min-Chuan E. Rd., Taipei, Taiwan, ROC Tel: [phone] Fax: [phone]

143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel [phone] Fax [phone]

Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel [phone], Fax [phone]

2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel [phone], Fax [phone]

www.genesis-microchip.com / [e-mail]

Genesis Microchip Inc.

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

•

Revision History

Document Description Date

C2115-DAT-01A Initial release. August 2001

D2115-DAT-01B

• Pins 143 ~ 146: changed xxx_SDDS or xxxx_SDDS to xxx_DDDS or xxxx_DDDS
respectively

• Pins 138 ~ 141: changed xxx_DDDS or xxxx_DDDS to xxx_SDDS or xxxx_SDDS
respectively

Pins 147 ~ 148: changed xxx_DPLL to xxx_RPLL

June 2002

Trademarks: RealColor and Real Recovery are trademarks of Genesis Microchip Inc.

© Copyright 2001, Genesis Microchip Inc. All Rights Reserved.

Genesis Microchip Inc. reserves the right to change or modify the information contained herein without
notice. Please obtain the most recent revision of this document. Genesis Microchip Inc. makes no warranty
for the use of its products and bears no responsibility for any errors or omissions that may appear.

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table Of Contents

1. Overview ............................................................................................................................................ 5

1.1 gm2115/25 System Design Example ........................................................................................... 5

1.2 gm2115/25 Features..................................................................................................................... 6

2. gm2115/25 Pinout ..............................................................................................................................7

3. gm2115/25 Pin List ............................................................................................................................ 8

4. Functional Description ..................................................................................................................... 14

4.1 Clock Generation ....................................................................................................................... 14

4.1.1 Using the Internal Oscillator with External Crystal............................................................ 15

4.1.2 Using an External Clock Oscillator ....................................................................................17

4.1.3 Clock Synthesis................................................................................................................... 18

4.2 Hardware Reset.......................................................................................................................... 20

4.3 Analog to Digital Converter (ADC)........................................................................................... 20

4.3.1 ADC Pin Connection .......................................................................................................... 21

4.3.2 ADC Characteristics ........................................................................................................... 21

4.3.3 Clock Recovery Circuit ...................................................................................................... 22

4.3.4 Sampling Phase Adjustment ............................................................................................... 23

4.3.5 ADC Capture Window........................................................................................................ 23

4.4 Test Pattern Generator (TPG) .................................................................................................... 24

4.5 Input Format Measurement (IFM) ............................................................................................. 24

4.5.1 HSYNC / VSYNC Delay.................................................................................................... 24

4.5.2 Horizontal and Vertical Measurement ................................................................................ 25

4.5.3 Format Change Detection ................................................................................................... 26

4.5.4 Watchdog............................................................................................................................ 26

4.5.5 Internal Odd/Even Field Detection ..................................................................................... 26

4.5.6 Input Pixel Measurement .................................................................................................... 27

4.5.7 Image Phase Measurement ................................................................................................. 27

4.5.8 Image Boundary Detection ................................................................................................. 27

4.5.9 Image Auto Balance............................................................................................................ 27

4.6 RealColor Digital Color Controls .............................................................................................. 27

4.6.1 RealColor Flesh tone Adjustment....................................................................................... 28

4.6.2 Color Standardization and sRGB Support .......................................................................... 28

4.7 High-Quality Scaling ................................................................................................................. 28

4.7.1 Variable Zoom Scaling ....................................................................................................... 28

4.7.2 Horizontal and Vertical Shrink ........................................................................................... 29

4.7.3 Moiré Cancellation ............................................................................................................. 29

4.8 Bypass Options ..........................................................................................................................29

4.9 Gamma Look-Up-Table (LUT) ................................................................................................. 29

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.10 Display Output Interface.......................................................................................................... 29

4.10.1 Display Synchronization................................................................................................... 30

4.10.2 Programming the Display Timing .................................................................................... 30

4.10.3 Panel Power Sequencing (PPWR, PBIAS)....................................................................... 32

4.10.4 Output Dithering............................................................................................................... 32

4.11 Timing Controller (TCON)...................................................................................................... 33

4.11.1 Programmable Column Driver Interface .......................................................................... 33

4.11.2 Programmable Row Driver Interface................................................................................ 36

4.11.3 Reduced EMI .................................................................................................................... 36

4.12 OSD.......................................................................................................................................... 38

4.12.1 On-Chip OSD SRAM ....................................................................................................... 38

4.12.2 Color Look-up Table (LUT) ............................................................................................. 39

4.12.3 OSD Position .................................................................................................................... 39

4.12.4 OSD Stretch ...................................................................................................................... 39

4.12.5 Blending............................................................................................................................ 39

4.13 On-Chip Microcontroller (OCM)............................................................................................. 40

4.13.1 Standalone Configuration ................................................................................................. 40

4.13.2 Full-Custom Configuration............................................................................................... 41

4.13.3 General Purpose Inputs and Outputs (GPIO).................................................................... 42

4.14 Bootstrap Configuration Pins................................................................................................... 43

4.15 Host Interface........................................................................................................................... 44

4.15.1 Host Interface Command Format...................................................................................... 44

4.15.2 2-wire Serial Protocol ....................................................................................................... 45

4.16 Miscellaneous Functions.......................................................................................................... 47

4.16.1 Power Down Operation .................................................................................................... 47

4.16.2 Pulse Width Modulation (PWM) Back Light Control...................................................... 47

5. Electrical Specifications ................................................................................................................... 48

5.1 Preliminary DC Characteristics ................................................................................................. 48

5.2 Preliminary AC Characteristics ................................................................................................. 49

6. Ordering Information ....................................................................................................................... 51

7. Mechanical Specifications................................................................................................................ 52

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

List Of Tables

Table 1. Analog Input Port.......................................................................................................8

Table 2. RCLK PLL Pins.........................................................................................................8

Table 3. System Interface and GPIO Signals...........................................................................9

Table 4. Display Output Port .................................................................................................10

Table 5. Parallel ROM Interface Port ....................................................................................11

Table 6. TCON Output Port...................................................................................................11

Table 7. Reserved Pins...........................................................................................................11

Table 8. Power Pins for ADC Sampling Clock DDS ............................................................13

Table 9. Power Pins for Display Clock DDS.........................................................................13

Table 10. I/O Power and Ground Pins .....................................................................................13

Table 11. Core Power and Ground Pins...................................................................................13

Table 12. TCLK Specification.................................................................................................18

Table 13. Pin Connection for RGB Input with HSYNC/VSYNC ...........................................21

Table 14. ADC Characteristics ................................................................................................22

Table 15. gm2115/25 GPIOs and Alternate Functions............................................................43

Table 16. Bootstrap Signals .....................................................................................................43

Table 17. Instruction Byte Map ...............................................................................................45

Table 18. Absolute Maximum Ratings ....................................................................................48

Table 19. DC Characteristics ...................................................................................................49

Table 20. Maximum Speed of Operation.................................................................................50

Table 21. Display Timing and DCLK Adjustments ................................................................50

Table 22. 2-Wire Host Interface Port Timing..........................................................................50

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

List Of Figures

Figure 1. gm2115/25 System Design Example.........................................................................5

Figure 2. gm2115/25 Pin Out Diagram.....................................................................................7

Figure 3. gm2115/25 Functional Block Diagram....................................................................14

Figure 4. Using the Internal Oscillator with External Crystal.................................................15

Figure 5. Internal Oscillator Output ........................................................................................16

Figure 6. Sources of Parasitic Capacitance .............................................................................17

Figure 7. Using an External Single-ended Clock Oscillator ...................................................18

Figure 8. Internally Synthesized Clocks .................................................................................19

Figure 9. On-chip Clock Domains ..........................................................................................20

Figure 10. Example ADC Signal Terminations ....................................................................21

Figure 11. gm2115/25 Clock Recovery ................................................................................22

Figure 12. ADC Capture Window.........................................................................................23

Figure 13. Some of gm2115/25 built-in test patterns............................................................24

Figure 14. HSYNC Delay .....................................................................................................25

Figure 15. Active Data Crosses HSYNC Boundary..............................................................25

Figure 16. ODD/EVEN Field Detection ...............................................................................26

Figure 17. RealColor Digital Color Controls ........................................................................27

Figure 18. Display Windows and Timing .............................................................................31

Figure 19. Single Pixel Width Display Data .........................................................................31

Figure 20. Double Pixel Wide Display Data.........................................................................32

Figure 21. Panel Power Sequencing......................................................................................32

Figure 22. Column Driver Interface Timing .........................................................................35

Figure 23. Row Driver Interface Timing...............................................................................37

Figure 24. OSD Cell Map......................................................................................................38

Figure 25. OCM Full-Custom and Standalone Configurations.............................................40

Figure 26. Programming OCM in Standalone Configuration ...............................................41

Figure 27. Programming the OCM in Full-Custom Configuration.......................................42

Figure 28. Factory Calibration and Test Environment..........................................................44

Figure 29. 2-Wire Protocol Data Transfer.............................................................................45

Figure 30. 2-Wire Write Operations (0x1x & 0x2x).............................................................46

Figure 31. 2-Wire Read Operation (0xAx) ...........................................................................46

Figure 32. gm2115/25 208-pin PQFP Mechanical Drawing................................................52

June 2002 C2115-DAT-01B

4

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

1. OVERVIEW

The gm2115/25 is a graphics processing IC for Liquid Crystal Display (LCD) monitors at
XGA/SXGA resolution. The gm2115/25 are pin compatible and firmware compatible to
gm5115/25 and gm3115/25. It provides all key IC functions required for image capture,
processing and timing control for direct interface to the row and column drivers of the LCD
panel. On-chip functions include a high-speed triple-ADC and PLL, a high quality zoom and
shrink scaling engine, an on-screen display (OSD) controller, an on-chip microcontroller
(OCM), and a programmable panel timing controller (TCON). With all these functions
integrated onto a single device, the gm2115/25 eliminates the need for a separate LCD
monitor controller printed circuit board (PCB) from the system along with the associated
connectors and cables. Therefore, the gm2115/25 simplifies the design and reduces the cost
of LCD monitors while maintaining a high-degree of flexibility and quality.

11..11 ggmm22111155//2255 SSyysstteemm DDeessiiggnn EExxaammppllee

Figure 1 below shows a typical dual interface LCD monitor system based on the gm2115/25.
Designs based on the gm2115/25 have reduced system cost, simplified hardware and
firmware design and increased reliability because only a minimal number of components are
required in the system.

Analog

RGB

gm2115/25

Row

Driver

ICs

Column

Driver

ICs

LCD

Panel

Back-light

NVRAM

ROM

(optional)

Figure 1. gm2115/25 System Design Example

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

11..22 ggmm22111155//2255 FFeeaattuurreess

FEATURES

• Zoom (from VGA) and shrink (from UXGA) scaling

• Integrated 8-bit triple-channel ADC / PLL

• On-chip programmable OnPanel timing controller

• Embedded microcontroller with parallel ROM interface

• On-chip versatile OSD engine

• All system clocks synthesized from a single external crystal

• Programmable gamma correction (CLUT)

• RealColor™ controls provide sRGB compliance

• PWM back light intensity control

• 5 Volt tolerant inputs

• Low EMI and power saving features

• High-Quality Advanced Scaling

• Fully programmable zoom ratios

• High-quality shrink capability from UXGA resolution

• Real Recovery™ function provides full color recovery

image for refresh rates higher than those supported by
the LCD panel

• Moire cancellation

• Analog RGB Input Port

• Supports up to 162.5MHz (SXGA 75Hz / UXGA 60Hz)

• On-chip high-performance PLLs

(only a single reference crystal required)

• Auto-Configuration / Auto-Detection

• Input format detection

• Phase and image positioning

• RealColor Technology

• Digital brightness and contrast controls

• TV color controls including hue and saturation controls

• Flesh-tone adjustment

• Full color matrix allows end-users to experience the

same colors as viewed on CRTs and other displays
(e.g. sRGB compliance)

• On-chip OSD Controller

• On-chip RAM for downloadable menus

• 1, 2 and 4-bit per pixel character cells

• Horizontal and vertical stretch of OSD menus

• Blinking, transparency and blending

• On-chip Microcontroller

• Requires no external micro-controller

• External parallel ROM interface allows firmware customization

with little additional cost

• 23 general-purpose inputs/outputs (GPIOs) available for
managing system devices (keypad, back-light, NVRAM, etc)

• Industry-standard firmware embedded on-chip, requires no
external ROM (configuration settings stored in NVRAM)

• Built-in OnPanel Timing Controller

• Eliminates the need for an external panel timing controller

(TCON) device, thereby reducing system cost

• Direct connect to commercial row/column driver ICs (supports
dual-bus / dual-port and dual-bus / single-port)

• Low EMI and power saving features include frame, line and in-line
inversion, blanking, data staggering and slew rate control.

• Programmable Output Format

• Single / double wide up to XGA/SXGA 75Hz output

• Pin swap, odd / even swap and red / blue group swap of

RGB outputs for flexibility in board layout

• Support for 8 or 6-bit panels (with high-quality dithering)

• Highly Integrated System-on-a-Chip

Reduces Component Count for Highly Cost

Effective Solution

• Standalone operation requires no external

ROM and no firmware development for Fast

Time to Market

• Pin and register compatible OnPanel Family:

- gm5115/gm5125 Dual-Interface XGA/SXGA

- gm3115/gm3125 Digital-Interface XGA/SXGA

- gm2115/gm2125 Analog-Interface XGA/SXGA

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

2. GM2115/25 PINOUT

The gm2115/25 is available in a 208-pin Plastic Quad Flat Pack (PQFP) package. Figure 2
provides the pin locations for all signals.

GPIO18

GPIO19

GPIO20

GPIO16/HFSn

GPIO22/HCLK

CVDD_2.5

CVSS

CLKOUT

N/C

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

AVDD_RED

RED+

RED-

AGND_RED

AVDD_GREEN

GREEN+

GREEN-

AGND_GREEN

AVDD_BLUE

BLUE+

BLUE-

AGND_BLUE

AVDD_ADC

ADC_TEST

AGND_ADC

RVDD
RVSS

RVDD
RVSS

CVSS

RVDD
RVSS

1

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

gm2115/25

167

166

165

164

163

162

161

100

160

101

159

102

158

103

GPIO17

GPIO21/IRQn

RESETn
GPIO14/DDC_SCL
GPIO15/DDC_SDA

ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10

ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4

ROM_ADDR3
ROM_ADDR2
ROM_ADDR1
ROM_ADDR0

CVDD_2.5

ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0

ROM_Oen

GPIO8/IRQINn

GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2

GPIO3/TIMER1
GPIO4/UART_D1
GPIO5/UART_D0

GPIO6/TCON_SHC

GPIO7/TCON_TDIV

GPIO9/TCON_ROE2

GPIO10/TCON_ROE3

GPIO11/ROM_WEn
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL

SGND_ADC

157

104

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

GND1_ADC
VDD1_ADC_2.5
GND2_ADC
VDD2_ADC_2.5
TCLK
XTAL
AVDD_RPLL
AVSS_RPLL
VDD_RPLL
VSS_RPLL
AVDD_DDDS
AVSS_DDDS
VDD_DDDS
VSS_DDDS
N/C
AVDD_SDDS
AVSS_SDDS
VDD_SDDS
VSS_SDDS
HSYNC
VSYNC
CVSS
CVDD_2.5
CVSS
Reserved
Reserved
RVSS
RVDD
TCON_ROE
TCON_RCLK
TCON_RSP3
TCON_RSP2
TCON_EINV
TCON_EPOL
TCON_ESP
TCON_OINV
TCON_OPOL
TCON_OSP
DCLK/TCON_OCLK
DVS/TCON_FSYNC
DHS/TCON_LP
DEN/TCON_ECLK
PBIAS
PPWR
RVSS
RVDD
PD47/OB7
PD46/OB6
PD45/OB5
PD44/OB4
PD43/OB3
PD42/OB2

RVSS

RVDD

PD0/ER0

PD1/ER1

PD2/ER2

PD3/ER3

PD4/ER4

PD5/ER5

PD6/ER6

PD7/ER7

PD8/EG0

RVSS

RVDD

PD9/EG1

PD10/EG2

PD11/EG3

PD16/EB0

PD17/EB1

PD18/EB2

PD19/EB3

PD12/EG4

PD13/EG5

PD14/EG6

PD15/EG7

PD20/EB4

PD21/EB5

PD22/EB6

PD23/EB7

RVSS

RVDD

CVSS

PD24/OR0

CVDD_2.5

PD25/OR1

PD26/OR2

PD27/OR3

PD28/OR4

PD29/OR5

PD30/OR6

PD31/OR7

PD32/OG0

PD33/OG1

PD34/OG2

PD35/OG3

RVSS

RVDD

PD36/OG4

PD37/OG5

PD38/OG6

PD39/OG7

PD40/OB0

PD41/OB1

Figure 2. gm2115/25 Pin Out Diagram

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

3. GM2115/25 PIN LIST

I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground

Table 1. Analog Input Port

Pin Name No. I/O Description

AVDD_RED 172 AP Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to

RED+ 171 AI Positive analog input for Red channel.
RED- 170 AI Negative analog input for Red channel.
AGND_RED 169 AG Analog ground for the red channel.

AVDD_GREEN 168 AP Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to

GREEN+ 167 AI Positive analog input for Green channel.
GREEN- 166 AI Negative analog input for Green channel.
AGND_GREEN 165 AG Analog ground for the green channel.

AVDD_BLUE 164 AP Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to

BLUE+ 163 AI Positive analog input for Blue channel.
BLUE- 162 AI Negative analog input for Blue channel.
AGND_BLUE 161 AG Analog ground for the blue channel.

AVDD_ADC 160 AP Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes

ADC_TEST 159 AO Analog test output for ADC Do not connect.
AGND_ADC 158 AG Analog ground for ADC analog blocks that are shared by all three channels. Includes band

SGND_ADC 157 AG Dedicated pad for substrate guard ring that protects the ADC reference system.

GND1_ADC 156 G Digital GND for ADC clocking circuit.

VDD1_ADC_2.5 155 P Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to

GND2_ADC 154 G Digital GND for ADC clocking circuit.

VDD2_ADC_2.5 153 P Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to

HSYNC 137 I ADC input horizontal sync input.

VSYNC 136 I ADC input vertical sync input.

AGND_RED pin on system board (as close as possible to the pin).

Must be directly connected to the analog system ground plane.

AGND_GREEN pin on system board (as close as possible to the pin).

Must be directly connected to the analog system ground plane.

AGND_BLUE pin on system board (as close as possible to the pin).

Must be directly connected to the analog system ground plane.

band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).

gap reference, master biasing and full-scale adjust.
Must be directly connected to analog system ground plane.

Must be directly connected to the analog system ground plane.

Must be directly connected to the digital system ground plane

GND1_ADC pin on system board (as close as possible to the pin).

Must be directly connected to the digital system ground plane.

GND2_ADC pin on system board (as close as possible to the pin).

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

Table 2. RCLK PLL Pins

Pin Name No I/O Description

AVDD_RPLL 150 AP Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a

AVSS_RPLL 149 AG Analog ground for the Reference DDS PLL.

TCLK 152 AI Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-

XTAL 151 AO Crystal oscillator output.
VDD_RPLL 148 P Digital power for RCLK PLL. Connect to 3.3V supply.
VSS_RPLL 147 G Digital ground for RCLK PLL.

June 2002 C2115-DAT-01B

0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).

Must be directly connected to the analog system ground plane.

ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 13.

8

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 3. System Interface and GPIO Signals

Pin Name No I/O Description

RESETn 5 I

GPIO0/PWM0 40 IO General-purpose input/output signal or PWM0. Open drain option via register setting.

GPIO1/PWM1 41 IO General-purpose input/output signal or PWM1. Open drain option via register setting.

GPIO2/PWM2 42 IO General-purpose input/output signal or PWM2. Open drain option via register setting.

GPIO3/TIMER1 43 IO General-purpose input/output signal. Open drain option via register setting. This pin is also

GPIO4/UART_DI 44 IO General-purpose input/output signal. Open drain option via register setting. This pin is also

GPIO5/UART_DO 45 IO General-purpose input/output signal. Open drain option via register setting. This pin is also

GPIO6/TCON_SHC 46 IO General-purpose input/output signal.

GPIO7/TCON_TDIV 47 IO General-purpose input/output signal.

GPIO8/IRQINn 39 IO General-purpose input/output signal. This is also active-low interrupt input to OCM and is

GPIO9/TCON_ROE2 48 IO General-purpose input/output signal. Open drain option via register setting. This pin can

GPIO10/TCON_ROE3 49 IO General-purpose input/output signal. Open drain option via register setting. This pin can

GPIO11/ROM_WEn 50 IO General-purpose input/output signal, or ROM write enable if a programmable FLASH

GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL

GPIO14/DDC_SCL
GPIO15/DDC_SDA

GPIO16/HFSn 205 IO General-purpose input/output signal when host port is disabled, or data signal for 2-wire

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21/IRQn 4 IO General-purpose input/output signal when host port is disabled, or active-low and open-

GPIO22/HCLK 204 IO General-purpose input/output signal when host port is disabled, or clock for 2-wire serial

51
52

6 7 IO General-purpose input/output signals, or 2-wire master serial interface to NVRAM in

1
208
207
206

Active-low hardware reset signal. The reset signal must be held low for at least 1µS.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

connected to Timer 1 clock input of the OCM.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

connected to the OCM UART data input signal by programming an OCM register.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

connected to the OCM UART data output signal by programming an OCM register.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

directly wired to OCM int_0n.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

also function as TCON signal ROE2.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

also function as TCON signal ROE3.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

device is used. Open drain option via register setting.
[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

IO

General-purpose input/output signals, or 2-wire master serial interface to NVRAM in
standalone mode. Open drain option via register setting.

IO

[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

standalone mode. Open drain option via register setting.
[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

serial host interface.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V tolerant]

IO

General-purpose input/output signals.

IO

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
IO
IO

drain interrupt output pin.

[Bi-directional, 5V-tolerant]

host interface.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 4. Display Output Port

Pin Name No I/O Description

DCLK/TCON_OCLK 118 O Panel output clock or TCON Odd Column Driver Bus Clock.

DVS/TCON_FSYNC 117 O Panel Vertical Sync or TCON Frame Synchronization.

DHS/TCON_LP 116 O Panel Horizontal Sync or TCON Load Pulse.

DEN/TCON_ECLK 115 O Panel Display Enable, which frames the output background window, or TCON Even Column

PBIAS 114 O Panel Bias Control (back light enable)

PPWR 113 O Panel Power Control

PD47
PD46
PD45
PD44
PD43
PD42
PD41
PD40
PD39
PD38
PD37
PD36
PD35
PD34
PD33
PD32
PD31
PD30
PD29
PD28
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

110
109
108
107
106
105
104
103
102
101
100

99
96
95
94
93
92
91
90
87
86
85
84
83
80
79
78
77
76
75
74
73
72
71
70
69
66
65
64
63
62
61
60
59
58
57
56
55

[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

Driver Bus Clock.
[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

O

Panel or TCON output data.

O

[Tri-state output, Programmable Drive]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 5. Parallel ROM Interface Port

Pin Name No I/O Description

ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10
ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4
ROM_ADDR3
ROM_ADDR2
ROM_ADDR1
ROM_ADDR0
ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0
ROM_Oen 36 O External PROM data Output Enable

8

9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
28
29
30
31
32
33
34
35

IO

ROM address output. These pins also serve as 5V-tolerant bootstrap inputs on power up.
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

I

5V-tolerant external PROM data input

I
I
I
I
I
I
I

Table 6. TCON Output Port

Pin Name No I/O Description

TCON_OSP 119 O Odd Starting Pulse
TCON_OPOL 120 O Odd Polarity
TCON_OINV 121 O Odd Data Transmission Inversion
TCON_ESP 122 O Even Starting Pulse
TCON_EPOL 123 O Even Polarity
TCON_EINV 124 O Even Data Transmission Inversion
TCON_RSP2 125 O Row Starting Pulse for 2-Voltage Row Driver
TCON_RSP3 126 O Row Starting Pulse for 3-Voltage Row Driver
TCON_RCLK 127 O Row Shift Clock
TCON_ROE 128 O Row Output Enable

Table 7. Reserved Pins

Pin Name No I/O Description

Reserved 131 I Tie to GND.
Reserved 132 I Tie to GND.
N/C 142 O No connect.
Reserved 173 N/C No connect.
Reserved 174 N/C No connect.
Reserved 175 N/C No connect.
Reserved 176 N/C No connect.
Reserved 177 N/C No connect.
Reserved 178 N/C No connect.
Reserved 179 N/C No connect.
Reserved 180 N/C No connect.
Reserved 181 N/C No connect.
Reserved 182 N/C No connect.
Reserved 183 N/C No connect.
Reserved 184 N/C No connect.
Reserved 185 N/C No connect.
Reserved 186 N/C No connect.
Reserved 187 N/C No connect.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Reserved 188 N/C No connect.
Reserved 189 N/C No connect.
Reserved 190 N/C No connect.
Reserved 191 N/C No connect.
Reserved 192 N/C No connect.
Reserved 193 N/C No connect.
Reserved 194 N/C No connect.
Reserved 195 N/C No connect.
Reserved 196 N/C No connect.
Reserved 197 N/C No connect.
Reserved 198 N/C No connect.
Reserved 199 N/C No connect.
N/C 200 O No connect.
CLKOUT 201 AO For test purposes only. Do not connect.

Note: For PCB compatibility with gm5115/25 and gm3115/25 input pins 173-199 should be
connected as described in the gm5115 data sheet C5115-DAT-01.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Note that VDD pins having "_2.5" in their names should be connected to 2.5V power supplies. All

other VDD pins should be connected to 3.3V power supplies.

Table 8. Power Pins for ADC Sampling Clock DDS

Pin Name No I/O Description

AVDD_DDDS 146 AP Analog power for the Destination DDS. Connect to 3.3V supply.

AVSS_DDDS 145 AG Analog ground for the Destination DDS.

VDD_DDDS 144 P Digital power for the Destination DDS. Connect to 3.3V supply.
VSS_DDDS 143 G Digital ground for the Destination DDS.

Must be bypassed with a 0.1uF capacitor to AVSS_DDDS pin
(as close to the pin as possible).

Must be directly connected to the analog system ground.

Table 9. Power Pins for Display Clock DDS

Pin Name No I/O Description

AVDD_SDDS 141 AP Analog power for Source DDS. Connect to 3.3V supply.

AVSS_SDDS 140 AG Analog ground for Source DDS.

VDD_SDDS 139 P Digital power for the Source DDS. Connect to 3.3V supply.
VSS_SDDS 138 G Digital ground for the Source DDS.

Must be bypassed with a 0.1uF capacitor to AVSS_SDDS pin
(as close to the pin as possible).

Must be directly connected to the analog system ground plane.

Table 10. I/O Power and Ground Pins

Pin Name No I/O Description

RVDD 2

111
129

RVSS 3

112
130

20
37
53
67
81
97

21
38
54
68
82
98

P

Connect to 3.3V supply.

P

Must be bypassed with a 0.1uF capacitor to RVSS (as close to the pin as possible).
P
P
P
P
P
P
P

G

Connect to digital ground.

G
G
G
G
G
G
G
G

Table 11. Core Power and Ground Pins

Pin Name No I/O Description

CVDD_2.5 26

134
203

CVSS 27

133
135
202

Note, “AP” indicates a power supply that is analog in nature and does not have large switching

currents. These should be isolated from other digital supplies that do have large switching currents.

88

89

P

Connect to 2.5V supply.
P

Must be bypassed with a 0.1uF capacitor to CVSS (as close to the pin as possible).
P
P

G

Connect to digital ground.

G
G
G
G

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4. FUNCTIONAL DESCRIPTION

A functional block diagram is illustrated below. Each of the functional units shown is
described in the following sections.

Analog RGB

Input

NVRAM

Serial I/F

Serial Host I/F

Parallel
ROM IF

Crystal

Reference

Host

Interface

8051-style

Micro-

controller

MCU

RAM

External
ROM I/F

Internal

ROM

Triple ADC

and PLL

Test Pattern

Generator

Image
Capture /
Measure-

ment

Brightness /

Contrast /
Hue / Sat /

RealColor /

Moire

Zoom /

Shrink /

Filter

Controller

OSD

OSD

RAMs

Gamma
Control

Clock

Generation

Panel

Timing

Controller

Output

Data
Path

Timing
Control
Signals

Panel Data

Figure 3. gm2115/25 Functional Block Diagram

44..11 CClloocckk GGeenneerraattiioonn

The gm2115/25 features two clock inputs. All additional clocks are internal clocks derived
from one or both of these:

1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal
oscillator and corresponding logic. A 14.3 MHz TV crystal is recommended. Other
crystal frequencies may be used, but require custom programming. This is illustrated in
Figure 4 below. Alternatively, a single-ended TTL/CMOS clock oscillator can be driven
into the TCLK pin (leave XTAL as N/C in this case). This is illustrated in Figure 7
below. This option is selected by connecting a 10KΩ pull-up to ROM_ADDR13 (refer to
Table 16). See also Table 13.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

2. Host Interface Transfer Clock (HCLK)

The gm2115 TCLK oscillator circuitry is a custom designed circuit to support the use of an
external oscillator or a crystal resonator to generate a reference frequency source for the
gm2115 device.

4.1.1 Using the Internal Oscillator with External Crystal

The first option for providing a clock reference is to use the internal oscillator with an
external crystal. The oscillator circuit is designed to provide a very low jitter and very low
harmonic clock to the internal circuitry of the gm2115. An Automatic Gain Control (AGC) is
used to insure startup and operation over a wide range of conditions. The oscillator circuit
also minimizes the overdrive of the crystal, which reduces the aging of the crystal.

When the gm2115/25 is in reset, the state of the ROM_ADDR13 pin (pin number 10) is
sampled. If the pin is left unconnected (internal pull-down) then internal oscillator is enabled.
In this mode a crystal resonator is connected between TCLK (pin 152) and the XTAL (pin

151) with the appropriately sized loading capacitors CL1 and CL2. The size of CL1 and CL2 are

determined from the crystal manufacturer’s specification and by compensating for the
parasitic capacitance of the gm2115/25 device and the printed circuit board traces. The
loading capacitors are terminated to the analog VDD power supply. This connection
increases the power supply rejection ratio when compared to terminating the loading
capacitors to ground.

Vdda

CL1

152

TCLK

gm2115/25

Vdd

Vdda

CL2

151

XTAL

100 K

180 uA

OSC_OUT

TCLK Distribution

N/C

ROM_ADDR13

10

Reset State Logic

Internal Pull Down

Resistor

~ 60K

Internal Oscillator Enable

Figure 4. Using the Internal Oscillator with External Crystal

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

The TCLK oscillator uses a Pierce Oscillator circuit. The output of the oscillator circuit,
measured at the TCLK pin, is an approximate sine wave with a bias of about 2 volts above
ground (see Figure 5). The peak-to-peak voltage of the output can range from 250 mV to
1000 mV depending on the specific characteristics of the crystal and variation in the
oscillator characteristics. The output of the oscillator is connected to a comparator that
converts the sine wave to a square wave. The comparator requires a minimum signal level of
about 50-mV peak to peak to function correctly. The output of the comparator is buffered and
then distributed to the gm2115/25 circuits.

3.3 Volts

~ 2 Volts

250 mV peak to peak

to

1000 mV peak to peak

time

Figure 5. Internal Oscillator Output

One of the design parameters that must be given some consideration is the value of the
loading capacitors used with the crystal as shown in Figure 6. The loading capacitance (C
on the crystal is the combination of CL1 and CL2 and is calculated by C
(CL1 + CL2)) + C

. The shunt capacitance C

shunt

is the effective capacitance between the

shunt

= ((CL1 * CL2) /

load

load

)

XTAL and TCLK pins. For the gm2115/25 this is approximately 9 pF. CL1 and CL2 are a
parallel combination of the external loading capacitors (Cex), the PCB board capacitance

), the pin capacitance (C

(C

pcb

capacitance (C
C

+ C

pad

ESD

). The capacitances are symmetrical so that CL1 = CL2 = Cex + C

esd

. The correct value of Cex must be calculated based on the values of the load

), the pad capacitance (C

pin

), and the ESD protection

pad

+ C

PCB

pin

+

capacitances. Approximate values are provided in Figure 6.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

A

CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd

Vdda

Cex1

Vdda

Cex2

CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd

Cpcb

Cshunt

Cpcb

141

TCLK

142

XTAL

Cpin Cpad Cesd

gm2115/25

Cpin Cpad Cesd

Internal Oscillator

pproximate values:

C

~ 2 pF to 10 pF (layout dependent)

PCB

~ 1.1 pF

C

pin

C

~ 1 pF

pad

~ 5.3 pF

C

esd

C

~ 9 pF

shunt

Figure 6. Sources of Parasitic Capacitance

Some attention must be given to the details of the oscillator circuit when used with a crystal
resonator. The PCB traces should be as short as possible. The value of C

that is specified

load

by the manufacturer should not be exceeded because of potential start up problems with the
oscillator. Additionally, the crystal should be a parallel resonate-cut and the value of the
equivalent series resistance must be less then 90 Ohms.

4.1.2 Using an External Clock Oscillator

Another option for providing the reference clock is to use a single-ended external clock
oscillator. When the gm2115/25 is in reset, the state of the ROM_ADDR13 (pin 10) is
sampled. If ROM_ADDR13 is pulled high by connecting to VDD through a pull-up resistor
(10KΩ recommended, 15KΩ maximum) then external oscillator mode is enabled. In this
mode the internal oscillator circuit is disabled and the external oscillator signal that is
connected to the TCLK pin (pin number 152) is routed to an internal clock buffer. This is
illustrated in Figure 7.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Vdd

Oscillator

GND

Vdd

14 to 24 MHz

Vdd

TCLK

151

XTAL

152

gm2115/25

Internal

Oscillator

Disable

OSC_OUT

TCLK Distribution

10 K

ROM_ADDR13

10

Reset State Logic

External Oscillator Enable

Internal Pull Down

Resistor

~ 60 K

Figure 7. Using an External Single-ended Clock Oscillator

Frequency 14 to 24 MHz
Jitter Tolerance 250 ps
Rise Time (10% to 90%) 5 ns
Maximum Duty Cycle 40-60

Table 12. TCLK Specification

4.1.3 Clock Synthesis

The gm2115/25 synthesis all additional clocks internally as illustrated in Figure 8 below. The
synthesized clocks are as follows:

1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is
derived from the TCLK/XTAL pad input.

2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the
reference.

3. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input
HSYNC as the reference. The SDDS internal digital logic is driven by RCLK.

4. Display Clock (DCLK) synthesized by Destination DDS (DDDS) PLL using IP_CLK as
the reference. The DDDS internal digital logic is driven by RCLK.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

5. Half Reference Clock (RCLK/2) is the RCLK (see 2, above) divided by 2. Used as
OCM_CLK domain driver.

6. Quarter Reference Clock (RCLK/4) is the RCLK (see 2, above) divided by 4. Used as
alternative clock (faster than TCLK) to drive IFM.

8. ADC Output Clock (SENSE_ACLK) is a delay-adjusted ADC sampling clock, ACLK.
ACLK is derived from SCLK.

TCLK

RCLK

PLL

HSYNC

SDDS

IP_CLK

/2

/4

DDDS

SCLK

DCLK

RCLK/2

RCLK/4

Figure 8. Internally Synthesized Clocks

The on-chip clock domains are selected from the synthesized clocks as shown in Figure 9
below. These include:

1. Input Domain Clock (IP_CLK). Max = 165MHz

2. Host Interface and On-Chip Microcontroller Clock (OCM_CLK). Max = 100MHz

3. Filter and Display Pixel Clock (DP_CLK). Max = 135MHz

4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz

5. ADC Domain Clock (ACLK). Max = 165MHz.

The clock selection for each domain as shown in the figure below is controlled using the
CLOCK_CONFIG registers (index 0x03 and 0x04).

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

DCLK

SCLK

SENSE_ACLK

IP_CLK

DP_CLK

IP_CLK

SCLK

ACLK

RCLK/2

OCM_CLK

TCLK

RCLK/4

IFM_CLK

TCLK

Figure 9. On-chip Clock Domains

44..22 HHaarrddwwaarree RReesseett

Hardware Reset is performed by holding the RESETn pin low for a minimum of 1µs. A
TCLK input (see Clock Options above) must be applied during and after the reset. When the
reset period is complete and RESETn is de-asserted, the power-up sequence is as follows:

1. Reset all registers of all types to their default state (this is 00h unless otherwise specified
in the gm2115/25 Register Listing).

2. Force each clock domain into reset. Reset will remain asserted for 64 local clock domain
cycles following the de-assertion of RESETn.

3. Operate the OCM_CLK domain at the TCLK frequency.

4. Preset the RCLK PLL to output ~200MHz clock (assumes 14.3MHz TCLK crystal
frequency).

5. Wait for RCLK PLL to Lock. Then, switch the OCM_CLK domain to operate from the
bootstrap selected clock.

6. If a pull-up resistor is installed on ROM_ADDR9 pin (see Table 16), then the OCM
becomes active as soon as OCM_CLK is stable. Otherwise, the OCM remains in reset
until OCM_CONTROL register (0x22) bit 1 is enabled.

44..33 AAnnaalloogg ttoo DDiiggiittaall CCoonnvveerrtteerr ((AADDCC))

The gm2115/25 chip has three ADC’s (analog-to-digital converters), one for each color (red,
green, and blue).

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.3.1 ADC Pin Connection

The analog RGB signals are connected to the gm2115/25 as described below:

Table 13. Pin Connection for RGB Input with HSYNC/VSYNC

Pin Name ADC Signal Name

Red+ Red

Red- Terminate as illustrated in Figure 10
Green+ Green
Green- Terminate as illustrated in Figure 10

Blue+ Blue
Blue- Terminate as illustrated in Figure 10
HSYNC Horizontal Sync (Terminate as illustrated in Figure 10)

VSYNC Vertical Sync (Terminate as with HSYNC illustrated in Figure 10)

gm2115/25

100Ω

RED +

RED -

DB15

RED

0.01uF

75Ω

100Ω

GND

0.01uF

HSYNC

HS

Figure 10. Example ADC Signal Terminations

Please note that it is very important to follow the recommended layout guidelines for the
circuit shown in Figure 10. These are described in "gm5115/25 Layout Guidelines"
document number C5115-SLG-01A.

4.3.2 ADC Characteristics

The table below summarizes the characteristics of the ADC:

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 14. ADC Characteristics

MIN TYP MAX NOTE

Track & Hold Amp Bandwidth 290 MHz Guaranteed by design. Note that the Track &

Full Scale Adjust Range at RGB Inputs 0.55 V 0.90 V

Full Scale Adjust Sensitivity +/- 1 LSB Measured at ADC Output.

Zero Scale Adjust Sensitivity +/- 1 LSB Measured at ADC Output.

Sampling Frequency (Fs) 10 MHz 162.5 MHz

Differential Non-Linearity (DNL) +/-0.5 LSB +/-0.9 LSB Fs = 135 MHz

No Missing Codes Guaranteed by test.

Integral Non-Linearity (INL) +/- 1.5 LSB Fs =135 MHz

Channel to Channel Matching +/- 0.5 LSB

Hold Amp Bandwidth is programmable. 290
MHz is the maximum setting.

Independent of full-scale RGB input.

The gm2115/25 ADC has a built-in clamp circuit for AC-coupled inputs. By inserting series
capacitors (about 10 nF), the DC offset of an external video source can be removed. The
clamp pulse position and width are programmable.

4.3.3 Clock Recovery Circuit

The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used
to sample analog RGB data (IP_CLK or source clock). This circuit is locked to HSYNC of
the incoming video signal.

Patented digital clock synthesis technology makes the gm2115/25 clock circuits resistant to
temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock
recovery circuit can generate any IP_CLK clock frequency within the range of 10MHz to
165MHz.

Image Phase

Measurement

HSYNC

Phase

HSYNC

(delayed)

R
G

B

SDDS

ADC

24

IPCLK

Window

Capture

Figure 11. gm2115/25 Clock Recovery

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.3.4 Sampling Phase Adjustment

The programmable ADC sampling phase is adjusted by delaying the HSYNC input to the
SDDS. The accuracy of the sampling phase is checked and the result read from a register.
This feature enables accurate auto-adjustment of the ADC sampling phase.

4.3.5 ADC Capture Window

Figure 12 below illustrates the capture window used for the ADC input. In the horizontal
direction the capture window is defined in IP_CLKs (equivalent to a pixel count). In the
vertical direction it is defined in lines.

All the parameters beginning with “Source” are programmed gm2115/25 registers values.
Note that the Input Vertical Total is solely determined by the input and is not a
programmable parameter.

Reference

Point

Source

Hstart

Source Horizontal Total (pixels)

Source Width

Vstart

Source

Capture Window

Source Height

Input Vertical Total (lines)

Figure 12. ADC Capture Window

The Reference Point marks the leading edge of the first internal HSYNC following the
leading edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are
derived from external HSYNC and VSYNC inputs.

Horizontal parameters are defined in terms of single pixel increments relative to the internal
horizontal sync. Vertical parameters are defined in terms of single line increments relative to
the internal vertical sync.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

For ADC interlaced inputs, the gm2115/25 may be programmed to automatically determine
the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format
Measurement, Section 4.5.

44..44 TTeesstt PPaatttteerrnn GGeenneerraattoorr ((TTPPGG))

The gm2115/25 contains hundreds of test patterns, some of which are shown in Figure 13.
Once programmed, the gm2115/25 test pattern generator can replace a video source (e.g. a
PC) during factory calibration and test. This simplifies the test procedure and eliminates the
possibility of image noise being injected into the system from the source. The foreground and
background colors are programmable. In addition, the gm2115/25 OSD controller can be
used to produce other patterns.

Figure 13. Some of gm2115/25 built-in test patterns

44..55 IInnppuutt FFoorrmmaatt MMeeaassuurreemmeenntt ((IIFFMM))

The gm2115/25 has an Input Format Measurement block (the IFM) providing the capability
of measuring the horizontal and vertical timing parameters of the input video source. This
information may be used to determine the video format and to detect a change in the input
format. It is also capable of detecting the field type of interlaced formats.

The IFM features a programmable reset, separate from the regular gm2115/25 soft reset.
This reset disables the IFM, reducing power consumption. The IFM is capable of operating
while the gm2115/25 is running in power-down mode.

Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or
RCLK/4), while vertical measurements are measured in terms of HSYNC pulses.

For an overview of the internally synthesized clocks, see section 4.1.

4.5.1 HSYNC / VSYNC Delay

The active input region captured by the gm2115/25 is specified with respect to internal
HSYNC and VSYNC. By default, internal syncs are equivalent to the HSYNC and VSYNC
at the input pins and thus force the captured region to be bounded by external HSYNC and

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

VSYNC timing. However, the gm2115/25 provides an internal HSYNC and VSYNC delay
feature that removes this limitation. This feature is available for use with the ADC input. By
delaying the sync internally, the gm2115/25 can capture data that spans across the sync pulse.

It is possible to use HSNYC and VSYNC delay for image positioning. (Alternatively,
Source_HSTART and Source_VSTART in Figure 12 are used for image positioning of
analog input.) Taken to an extreme, the intentional movement of images across apparent
HSYNC and VSYNC boundaries creates a horizontal and/or vertical wrap effect.

HSYNC is delayed by a programmed number of selected input clocks.

HS(system)

HS(internal)

capture

programmable

delay

active active

capture capture

input block actually

captures across HSYNC

Figure 14. HSYNC Delay

Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with
respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but
with different paths to the gm2115/25 (HSYNC is often regenerated from a PLL). As a
result, VSYNC may be seen earlier or later. Because VSYNC is used to reset the line
counter and HSYNC is used to increment it, any difference in the relative position of
HSYNC and VSYNC is seen on-screen as vertical jitter. By delaying the HSYNC a small
amount, it can be ensured that VSYNC always resets the line counter prior to it being
incremented by the “first” HSYNC.

active data crosses HS boundary

delayed HS placed safely within blanking

Data

HS (system)

Internal Delayed HS

Figure 15. Active Data Crosses HSYNC Boundary

4.5.2 Horizontal and Vertical Measurement

The IFM is able to measure the horizontal period and active high pulse width of the HSYNC
signal, in terms of the selected clock period (either TCLK or RCLK/4.). Horizontal

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

measurements are performed on only a single line per frame (or field). The line used is
programmable. It is able to measure the vertical period and VSYNC pulse width in terms of
rising edges of HSYNC.

Once enabled, measurement begins on the rising VSYNC and is completed on the following
rising VSYNC. Measurements are made on every field / frame until disabled.

4.5.3 Format Change Detection

The IFM is able to detect changes in the input format relative to the last measurement and
then alert both the system and the on-chip microcontroller. The microcontroller sets a
measurement difference threshold separately for horizontal and vertical timing. If the current
field / frame timing is different from the previously captured measurement by an amount
exceeding this threshold, a status bit is set. An interrupt can also be programmed to occur.

4.5.4 Watchdog

The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the
programmed timing threshold (in terms of the selected IFM_CLK), a register bit is set. When
any VSYNC period exceeds the programmed timing threshold (in terms of HSYNC pulses),
a second register bit is set. An interrupt can also be programmed to occur.

4.5.5 Internal Odd/Even Field Detection

The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user
specifies start and end values to outline a “window” relative to HSYNC. If the VSYNC
leading edge occurs within this window, the IFM signals the start of an ODD field. If the
VSYNC leading edge occurs outside this window, an EVEN field is indicated (the
interpretation of odd and even can be reversed). The window start and end points are
selected from a predefined set of values.

HS

window

Window

Start

Window End

VS - even

VS - odd

Figure 16. ODD/EVEN Field Detection

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.5.6 Input Pixel Measurement

The gm2115/25 provides a number of pixel measurement functions intended to assist in
configuring system parameters such as pixel clock, SDDS sample clocks per line and phase
setting, centering the image, or adjusting the contrast and brightness.

4.5.7 Image Phase Measurement

This function measures the sampling phase quality over a selected active window region.
This feature may be used when programming the source DDS to select the proper phase
setting. Please refer to the gm5115/25 Programming Guide for the optimized algorithm.

4.5.8 Image Boundary Detection

The gm2115/25 performs measurements to determine the image boundary. This information
is used when programming the Active Window and centering the image.

4.5.9 Image Auto Balance

The gm2115/25 performs measurements on the input data that are used to adjust brightness
and contrast.

44..66 RReeaallCCoolloorr DDiiggiittaall CCoolloorr CCoonnttrroollss

The gm2115/25 provides high-quality digital color controls. These consist of a subtractive
"black level" stage, followed by a full 3x3 RGB matrix multiplication stage, followed by an
signed offset stage as shown in Figure 17.

Additive

Offset

(Brightness)

+/-

+/-

Red Out

Green Out

Red In

Green In

Subtractive

Offset

(Black Level)

-

-

3x3 Color

Conversion

X

Blue In

-

+/-

Blue Out

Figure 17. RealColor Digital Color Controls

This structure can accommodate all RGB color controls such as black-level (subtractive
stage), contrast (multiplicative stage), and brightness (signed additive offset). In addition, it

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

supports all YUV color controls including brightness (additive factor applied to Y), contrast
(multiplicative factor applied to Y), hue (rotation of U and V through an angle) and
saturation (multiplicative factor applied to both Y and V).

To provide the highest color purity all mathematical functions use 10 bits of accuracy. The
final result is then dithered to eight or six bits (as required by the LCD panel).

4.6.1 RealColor Flesh tone Adjustment

The human eye is more sensitive to variations of flesh tones than other colors; for example,
the user may not care if the color of grass is modified slightly during image capture and/or
display. However, if skin tones are modified by even a small amount, it is unacceptable. The
gm2115/25 features flesh tone adjustment capabilities. This feature is not based on lookup
tables, but rather a manipulation of YUV-channel parameters. Flesh tone adjustment is
available for all inputs.

4.6.2 Color Standardization and sRGB Support

Internet shoppers may be very picky about what color they experience on the display.
gm2115/25 RealColor digital color controls can be used to make the color response of an
LCD monitor compliant with standard color definitions, such as sRGB. sRGB is a standard
for color exchange proposed by Microsoft and HP (see www.srgb.com). gm2115/25
RealColor controls can be used to make LCD monitors sRGB compliant, even if the native
response of the LCD panel itself is not. For more information on sRGB compliance using
gm5115/25 family devices please refer to the sRGB application brief C5115-APB-02A.

44..77 HHiigghh--QQuuaalliittyy SSccaalliinngg

The gm2115/25 zoom/shrink scaler uses an adaptive scaling technique proprietary to Genesis
Microchip Inc., and provides high quality scaling of real time video and graphics images. An
input field/frame is scalable in both the vertical and horizontal dimensions.

Interlaced fields may be spatially de-interlaced by vertically scaling and repositioning the
input fields to align with the output display’s pixel map.

4.7.1 Variable Zoom Scaling

The gm2115/25 scaling filter can combine its advanced scaling with a pixel-replication type
scaling function. This is useful for improving the sharpness and definition of graphics when
scaling at high zoom factors (such as VGA to XGA).

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.7.2 Horizontal and Vertical Shrink

A shrink function may be performed on the input data. This is an arbitrary horizontal active
resolution reduction to between (50% + 1 pixel) to 100% of the input. For example, this
allows SXGA 1280 pixels to be displayed as 1024 (XGA).

The gm2115/25 provides an arbitrary vertical shrink down to (50% + 1 line) of the original
image size. Together with the arbitrary horizontal shrink, this allows the gm2115/25 to
capture and display images one VESA standard format larger than the native display
resolution. For example, SXGA may be captured and displayed on an XGA panel.

4.7.3 Moiré Cancellation

The gamma curve and other non-linearities can affect the energy distribution of pixels when
scaled to different areas of the screen. This is an example of the Moiré effect. The
gm2115/25 has hardware features to negate the Moiré effect, improving the scaling quality.

44..88 BByyppaassss OOppttiioonnss

The gm2115/25 has the capability to completely bypass internal processing. In this case,
captured input signals and data are passed, with a small latency, straight through to the
display output. The gm2115/25 is also able to bypass the zoom filter and the gamma LUT.

44..99 GGaammmmaa LLooookk--UUpp--TTaabbllee ((LLUUTT))

The gm2115/25 provides an 8 to 10-bit look-up table (LUT) for each input color channel
intended for Gamma correction and to compensate for a non-linear response of the LCD
panel. A 10-bit output results in an improved color depth control. The 10-bit output is then
dithered down to 8 bits (or 6 bits) per channel at the display (see section 4.10.3 below). The
LUT is user-programmable to provide an arbitrary transfer function. Gamma correction
occurs after the zoom / shrink scaling block. If bypassed, the LUT does not require
programming.

44..1100 DDiissppllaayy OOuuttppuutt IInntteerrffaaccee

The Display Output Port provides data and control signals that permit the gm2115/25 to
connect to a variety of flat panel or CRT devices. The output interface is configurable for 18
or 24-bit RGB pixels, either single- or double-pixel wide. All display data and timing signals
are synchronous with the DCLK output clock.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.10.1 Display Synchronization

Refer to section 4.1 for information regarding internal clock synthesis.

The gm2115/25 supports the following display synchronization modes:

• Frame Sync Mode: The display frame rate is synchronized to the input frame or

field rate. This mode is used for standard operation.

• Free Run Mode: No synchronization. This mode is used when there is no valid input

timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In
free-run mode, the display timing is determined only by the values programmed into
the display window and timing registers.

4.10.2 Programming the Display Timing

Display timing signals provide timing information so the Display Port can be connected to an
external display device. Based on values programmed in registers, the Display Output Port
produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control
signals. The figure below provides the registers that define the output display timing.

Horizontal values are programmed in single-pixel increments relative to the leading edge of
the horizontal sync signal. Vertical values are programmed in line increments relative to the
leading edge of the vertical sync signal.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

DH_BKGND_START DH_BKGND_END

Display Background Window

Display Active Window

HSYNC region

Horizontal Blanking (Back Porch)

Vertical Blanking (Front Porch)

DHS

DEN **

DH_HS_END

DH_ACTIVE_START

VSYNC Region

Vertical Blanking (Back Porch)

DH_TOTAL

DH_ACTIVE_WIDTH

DVS

DV_BKGND_START

DV_ACTIVE_START

DV_ACTIVE_LENGTH

DV_TOTAL

Horizontal Blanking (Front Porch)

DV_BKGND_END

**

DEN is not asserted during vertical blanking

DV_VS_END

Figure 18. Display Windows and Timing

The double-wide output only supports an even number of horizontal pixels.

DCLK (Output)

DEN (Output)

ER/EG/EB

(Output)

OR/OG/OB

(Output)

XXX

rgb0 rgb4rgb3rgb2rgb1

XXX

Figure 19. Single Pixel Width Display Data

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

DCLK (Output)

DEN (Output)

ER/EG/EB

(Output)

OR/OG/OB

(Output)

XXX

XXX

rgb0 rgb8rgb6rgb4rgb2

rgb1 rgb9rgb7rgb5rgb3

Figure 20. Double Pixel Wide Display Data

4.10.3 Panel Power Sequencing (PPWR, PBIAS)

The gm2115/25 has two dedicated outputs PPWR and PBIAS (pins 113 and 114) to control
LCD power sequencing once data and control signals are stable. The timing of these signals
is fully programmable.

TMG1 TMG2 TMG2 TMG1

PPWR Output

Panel Data and Control Signals

PBIAS Output

<State0> <State1> <State2> <State3> <State2> <State1> <State0>

POWER_SEQ_EN = 1 POWER_SEQ_EN = 0

Figure 21. Panel Power Sequencing

4.10.4 Output Dithering

The Gamma LUT outputs a 10-bit value for each color channel. This value is dithered down
to either 8-bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels.

The benefit of dithering is that the eye tends to average neighboring pixels and a smooth
image free of contours is perceived. Dithering works by spreading the quantization error over
neighboring pixels both spatially and temporally. Two dithering algorithms are available:
random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

All gray scales are available on the panel output whether using 8-bit panel (dithering from 10
to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).

44..1111 TTiimmiinngg CCoonnttrroolllleerr ((TTCCOONN))

The gm2115/25 features an integrated timing controller (TCON) that connects directly to
commercially available row and column drivers. It supports either 18 or 24-bits per pixel in 1
or 2 pixels per clock XGA operation. Also, it supports single or dual-edge clocking modes.
Frame, Line (Row) and pixel inversion is available for better image quality. In-Line
inversion reduces power consumption and EMI radiation. Data signals have programmable
drive strength.

During panel power-up the TCON control signals can be held inactive. This is to provide
correct power sequencing that does not damage the panel. The TCON control signals only
become active when the panel power sequencing is complete.

4.11.1 Programmable Column Driver Interface

The gm2115/25 column driver interface is highly programmable. It supports dual bus / dual
port, dual bus / one port (both interleave and bank) as well as single bus / single port for
XGA column drivers.

The column driver interface consists of the following signals:

OCLK/ECLK – Odd/Even Column Driver bus clock. OCLK and ECLK have a
programmable phase control (0-7ns) and programmable polarities. Even output data bus
(ERGB) can be skewed ½ clock (early) to reduce the number of outputs switching
simultaneously.

OSP/ESP - Odd/Even Starting Pulse. OSP and ESP have programmable positioning before
valid data. They also have programmable polarities.

ORGB[24]/ERGB[24] – Odd/Even 24 bits data bus supports 24 or 18 bits per pixel in 1 or 2
pixels per clock. These signals support even/odd, red/blue and data bit swap. They also have
programmable group and inter-group delays (0-7ns).

OPOL/EPOL – Odd/Even polarity. With programmable position of OPOL/EPOL, the
OPOL/EPOL can be switched when LP is active or before or after LP.

OINV/EINV – Odd/Even data transition inversion. These signals provide data inversion
capability to reduce electromagnetic interference (EMI). One INV signal can be used (either
EINV or OINV), or both.

LP – Load/Latch pulse. The Load/Latch pulse has a programmable width and polarity.

SHC – Output circuit control. This signal has programmable timing similar to OPOL/EPOL.

It is optionally available on GPIO6.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

TDIV – Horizontal timing. This signal rises with LP and has a programmable falling edge. It
is optionally available on GPIO7.

All signals OCLK, ECLK, ORGB, ERGB, OSP, ESP, OPOL, EPOL, OINV, EINV have
programmable drive strengths and can be disabled.

Clocks (OCLK/ECLK), Polarities (EPOL/OPOL) and Data (ERGB/ORGB, ESP/OSP) can
be blanked separately, during horizontal and/or vertical blanking period (programmable) to
reduce power. Clocks and Polarities are forced to zero and Data (ERGB/ORGB) is forced to
either white or black during blanking period.

Refer to Figure 22 for the column driver interface timing. See the gm5115/25 Programming
Guide (C5115-DSR-01) for details regarding column driver programming.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

8

0 2 4 6 8 10

1 3 5 7 9 11

0 2 4 6 8 10

1 3 5 7 9 11

1 2 3 4 5 6 7

655 0

654

inv alid data

inv alid data

invalid inv er s ion

invalid inv er s ion

hz XGA ( 25.4nsx99= 2.5146 us)

To m eet 2.5 us puls e width l p we need 99 e/ocl k for 75

617 618 619 620 621

inv alid datainvalid data

invalid data

inv alid inv er sion

inv alid inv er s ion

invalid data

invalid inv er s ion

invalid inv er s ion

accor ding to the v alue of pr ogramm able r egister s

The e/opol can be swi tched when l p is acti ve, befor e or after lp

515 516 517 518 519 520 521

508 510

8

509 511

508 510

509 511

e/osp can be as serted0,1, 2,3 cycle before the first

2 4 6 8 10

val id data based on the val ue of progr ammabl e regis ter

0

1 3 5 7 9 11

0 2 4 6 8 10

lp c an be asser ted and deserated ac cordi ng to the

val ue of start ing and ending pr ogram mable r egister s

1 3 5 7 9 11

1 2 3 4 5 6 7

655 0

inv alid data

inv alid data

inv alid inver sion

inv alid inver sion

E/OCLK

HCNT

E/OSP

ERGB

ORGB

EINV

OINV

LP

E/OPOL

Figure 22. Column Driver Interface Timing

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.11.2 Programmable Row Driver Interface

The gm2115/25 row driver interface supports 2 and 3 voltage row drivers.

The row driver interface consists of the following signals. The starting time and pulse-width
of each are fully programmable.

RSP2 – Row Starting Pulse for 2 voltage Row Driver

RSP3 – Row Starting Pulse for 3 voltage Row Driver

RCLK – Row/Vertical shift clock

ROE – Row Output Enable or Row Blank Time or Gate Driver Output Enable. This signal

is used to control RC discharge time. Note that some vendors support three ROE’s for this
function to avoid 2 lines being activated at the same time (ROE2 and ROE3 are optionally
available on pins GPIO9 and GPIO10). The polarities of ROE, ROE2 and ROE3 are
programmable. These signals can be blanked during horizontal and/or vertical blanking to
reduce power. In addition, ROE, ROE2 and ROE3 may be staggered.

RCLK, ROE, ROE2 and ROE3 have programmable polarities and can be blanked during
horizontal and/or vertical blanking period (programmable) to reduce power. Note that ROE2
and ROE3 can be used to drive GV and GVOFF signals required by some row driver ICs.

See the gm5115/25 Programming Guide (C5115-DSR-01) for details regarding row driver
programming.

4.11.3 Reduced EMI

The gm2115/25 programmable TCON has many features that can be used to reduce
electromagnetic interference (EMI). These include transition minimization, data staggering,
data swapping for reduced trace length (even with odd, red with blue and bit 0 with bit 7),
slew rate control and dual-edge clocking.

In addition, the DP_CLK generation circuit features a proprietary method for the reduction of
electromagnetic interference (EMI) emitted by the display port. High spikes in the EMI
power spectrum may cause LCD monitor products to violate emissions standards.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

799 0797 798795 796 1 2 3 762 763 764 765 766 767 768 769

PDE

PVSYNC

VCNT

RCLK

RSP2

RSP3

ROE

Notes:

1. The rclk low and high time can be determined by horizontal starting and ending programmable registers

2. The pulse width of RSP2 and RSP3 based on number of rclks can be determined by vertical starting and

ending programmable registers

3. The pulse width of ROE can be determinded by horizontal starting and ending programmable registers

4. For example, For 75 Hz XGA the Hor Total Time is 1312x12.7ns = 16.6 us, the low/high time of rclk is

16.6 us/2 = 328 ecoclk

Figure 23. Row Driver Interface Timing

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

44..1122 OOSSDD

The gm2115/25 has a fully programmable, high-quality OSD controller. The graphics are
divided into "cells" 12 by 18 pixels in size. The cells are stored in an on-chip static RAM
(4096 words by 24 bits) and can be stored as 1-bit per pixel data, 2-bit per pixel data or 4-bit
per pixel data. This permits a good compression ratio while allowing more than 16 colors in
the image.

4.12.1 On-Chip OSD SRAM

The on-chip static RAM (4096 words by 24 bits) stores the cell map and the cell definitions.

In memory, the cell map is organized as an array of words, each defining the attributes of one
visible character on the screen starting from upper left of the visible character array. These
attributes specify which character to display, whether it is stored as 1, 2 or 4 bits per pixel,
the foreground and background colors, blinking, etc.

Registers CELLMAP_XSZ and CELLMAP_YSZ are used to define the visible area of the
OSD image. For example, Figure 24 shows a cell map for which CELLMAP_XSZ =25 and
CELLMAP_YSZ =10.

Address26:

Cell attributes for

1

st

cell, 2nd row

Cell definitions are stored as bit map data. On-chip registers point to the start of 1-bit per
pixel definitions, 2-bit per pixel definitions and 4-bit per pixel definitions respectively. 1, 2
and 4-bit per pixel cell definitions require 9, 18 and 36 words of the OSD RAM respectively.

Note that the cell map and the cell definitions share the same on-chip RAM. Thus, the size of
the cell map can be traded off against the number of different cell definitions. In particular,
the size of the OSD image and the number of cell definitions must fit in OSD SRAM. That is,
the following inequality must be satisfied. (Note, the ROUND operation rounds 3.5 to 4).

CELLMAP_YSZ

Address 1:

Cell Attributes for

upper-left hand cell

Figure 24. OSD Cell Map

Address 25:

Attributes for

upper-right hand cell

CELLMAP_XSZ

Brightness
Contrast

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

(CELLMAP_XSZ+1) * CELLMAP_YSZ +
18 * ROUND(Number of 1-bit per pixel fonts / 2) +
18 * (Number of 2-bit per pixel fonts) +
36 * (Number of 4-bit per pixel fonts) <= 4096

For example, an OSD menu 360 pixels wide by 360 pixels high is 30 cells in width and 20
cells in height. Many of these cells would be the same (e.g. empty). In this case, the menu
could contain more than 32 1-bit per pixel cells, 100 2-bit per pixel cells, and 16 4-bit per
pixel cells. Of course, different numbers of each type can also be used.

4.12.2 Color Look-up Table (LUT)

Each pixel of a displayed cell is resolved to an 8-bit color code. This selected color code is
then transformed to a 24-bit value using a 256 x 24-bit look up table. This LUT is stored in
an on-chip RAM that is separate from the OSD RAM. Color index value 0x00 is reserved for
transparent OSD pixels.

4.12.3 OSD Position

The OSD menu can be positioned anywhere on the display region. The reference point is
Horizontal and Vertical Display Background Start (DH_BKGND_START and
DV_BKGND_START in Figure 18).

4.12.4 OSD Stretch

The OSD image can be stretched horizontally and/or vertically by a factor of two, three, or
four. Pixel and line replication is used to stretch the image.

4.12.5 Blending

Sixteeen levels of blending are supported for the character-mapped and bitmapped images.
One host register controls the blend levels for pixels with LUT values of 128 and greater,
while another host register controls the blend levels for pixels with LUT values of 127 and
lower. OSD color LUT value 0 is reserved for transparency and is unaffected by the blend
attribute.

Blend levels for binary codes “1111” through “0000” are 6.25%, 12.5%, 18.75%, 25%,

31.25%, 37.5%, 43.75%, 50%, 56.25%, 62.5%, 68.75%, 75%, 81.25%, 87.5%, 93.75%,

100%. Blend percentage level refers the percentage of the output data that is OSD.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

(

)

44..1133 OOnn--CChhiipp MMiiccrrooccoonnttrroolllleerr ((OOCCMM))

The gm2115/25 on-chip microcontroller (OCM) serves as the system microcontroller. It
programs the gm2115/25 and manages other devices in the system such as the keypad, the
back light and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO)
pins.

The OCM can operate in two configurations, Standalone configuration and Full-Custom
configuration, as illustrated in Figure 25.

Factory

Port

Analog

RGB

Input

Configuration settings in NVRAM:

• OSD Colors, Logo and other configuration

• Panel Parameters

• Additional input modes

• Code patches

Figure 25A - Standalone Configuration

gm2115/25

NVRAM

OCM

ROM

Figure 25. OCM Full-Custom and Standalone Configurations

No external ROM

Output to

LCD Panel

On-chip ROM:

• Auto mode detection

• Auto-configuration

• Standard high-quality OSD menus

• Factory test / calibration functions

Factory

Port

NVRAM

gm2115/25

OCM

PROM

External ROM:

• Contains firmware code and data
for all firmware functions

Output to

LCD Panel

Analog

RGB

Input

User settings in NVRAM:

• Brightness/contrast settings, etc

• On mode-by-mode basis

Figure 25B - Full-Custom Configuration

(Program and Data stored in external ROM)

4.13.1 Standalone Configuration

Standalone configuration offers the most simple and inexpensive system solution for generic
LCD monitors. In this configuration the OCM executes firmware stored internally in
gm2115/25. This is illustrated in Figure 25A. The on-chip firmware provides all the standard
functions required in a high-quality generic LCD monitor. This includes mode-detection,
auto-configuration and a high-quality standard OSD menu system. No external ROM is
required (which reduces BOM cost) and no firmware development effort is required (which
reduces time-to-market).

In Standalone configuration many customization parameters are stored in NVRAM. These
include the LCD panel timing parameters (including TCON programming), the color scheme
and logos used in the OSD menus, the functions provided by the OSD menus, and arbitrary
firmware modifications. These customization parameters are described in the Standalone

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

User’s Guide (B0108-SUG-01). Based on the customization parameters, G-Wizard (a GUI­based development tool used to program Genesis devices) produces the hex image file for
NVRAM. G-Probe is then used to download the NVRAM image file into the NVRAM
device. This is illustrated in Figure 26.

Specify Configurable Parameters

(See Standalone Users Guide)

G-Wizard

NVRAM

Image File

(.nvram_image. hex)

G-Probe

LCD
Controller
Board

gm2115/25

NVRAM

Figure 26. Programming OCM in Standalone Configuration

4.13.2 Full-Custom Configuration

In full-custom configuration the OCM executes a firmware program running from external
ROM. This is illustrated in Figure 25B. A parallel port with separate address and data busses
is available for this purpose. This port connects directly to standard, commercially available
ROM or programmable Flash ROM devices. Normally 64KB or 128KB of ROM is required.

Both instructions and data are fetched from external ROM on a cycle-by-cycle basis. The
speed of the accesses on the parallel port is determined by the gm2115/25 internal
OCM_CLK. This in turn determines the speed of the external ROM device. For example, if a

14.3 MHz crystal is being used to produce TCLK, and the OCM_CLK is derived from

TCLK, then a 45ns ROM can be used.

To program gm2115/25 in full-custom configuration the content of the external ROM is
generated using Genesis software development tools G-Wizard and OSD-Workbench. This is
illustrated in Figure 27. G-Wizard is a GUI-based tool for capturing system information such

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

as panel timing, support modes, system configuration, etc. OSD-Workbench is a GUI based
tool for defining OSD menus and functionality.

G-Wizard

gm5115/25 Driver

OSD Workbench

gm5115/25 Driver

Firmware source files (*.c *.h)

Keil Compiler

External ROM

Image File (.hex)

ROM Programmer

LCD
Controller
Board

gm2115/25

ROM

Figure 27. Programming the OCM in Full-Custom Configuration

Genesis recommends using Keil compiler (http://www.keil.com/

) to compile the firmware
source code into a hex file. This hex file is then downloaded into the external ROM using
commercially available ROM programmers.

For development purposes it may be useful to use a ROM emulator. For example, a
PROMJET ROM emulator can be used (http://www.emutec.com/pjetmain.html)

.

4.13.3 General Purpose Inputs and Outputs (GPIO)

The gm2115/25 has 21 general-purpose input/output (GPIO) pins. These are used by the
OCM to communicate with other devices in the system such as keypad buttons, NVRAM,
LEDs, audio DAC, etc. Each GPIO has independent direction control, open drain enable, for
reading and writing. Note that the GPIO pins have alternate functionality as described in
Table 15 below.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Pin Name Pin Number Alternate function

GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2
GPIO3/TIMER1 43 Timer1 input of the OCM.
GPIO4/UART_DI
GPIO5/UARD_D0
GPIO6
GPIO7
GPIO8/IRQINn 39 OCM external interrupt source (IRQINn).
GPIO9/TCON_ROE2
GPIO10/TCON_ROE3
GPIO11/ROM_WEn 50 Write enable for external ROM if programmable FLASH device is used.
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL
GPIO14/DDC_SCL
GPIO15/DDC_SDA
GPIO16/HFSn 205 Serial data line for 2-wire host interface.
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21/IRQn 4 OCM interrupt output pin.
GPIO22/HCLK 204 Serial input clock for 2-wire host interface.

40
41
42

44
45
46
47

48
49

51
52

6
7

1
208
207
206

PWM0, PWM1 and PWM2 back light intensity controls, as described in section 4.16.2 below.

OCM UART data in/out signals respectively.

Horizontal timing signals in the TCON column driver interface.

Row output enables ROE2 and ROE3 in the TCON row driver interface.

Data and clock lines for master 2-wire serial interface to NVRAM when gm2115/25 is used in
standalone configuration (section Figure 25).

General-purpose input/output signals. Open drain option via register setting.
[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

No alternative function.

Table 15. gm2115/25 GPIOs and Alternate Functions

44..1144 BBoooottssttrraapp CCoonnffiigguurraattiioonn PPiinnss

During hardware reset, the external ROM address pins ROM_ADDR[15:0] are configured as
inputs. On the negating edge of RESETn, the value on these pins is latched and stored. This
value is readable by the on-chip microcontroller (or an external microcontroller via the host
interface). Install a 10K pull-up resistor to indicate a ‘1’, otherwise a ‘0’ is indicated.

Signal Name Pin Name Description

HOST_ADDR(4:0)
USER_BITS(4:0)

HOST_ADDR(5) ROM_ADDR5 If using 2-wire host protocol, this is bit 5 of serial the bus device address.

HOST_ADDR(6) ROM_ADDR6 If using 2-wire host protocol, this is bit 6 of the serial bus device address.

HOST_PROTOCOL ROM_ADDR7 Program this bit to 0 for 2-wire host protocol operation.

HOST_PORT_EN ROM_ADDR8 Program this bit to 0 for 2-wire host protocol operation.

OCM_START ROM_ADDR9 Determines the operating condition of the OCM after HW reset:

USER_BITS(7:5) ROM_ADDR(12:10) These settings are available for reading from a status register but are otherwise unused by the gm2115/25.

OSC_SEL ROM_ADDR13 Selects reference clock source:

OCM_ROM_CNFG(1) ROM_ADDR14 Together with OCM_CONTROL register (0x22) bit 4, this bit selects internal/external ROM configuration.

ROM_ADDR(4:0) If using 2-wire host protocol, these are bits 4:0 of the serial bus device address.

Otherwise, these settings are available for reading from a status register but are otherwise unused by the
gm2115/25. Used for “soft” configuration settings.

Otherwise, program this bit to 0.

Otherwise, program this bit to 0.

0 = OCM remains in reset until enabled by register bit.
1 = OCM becomes active after OCM_CLK is stable.

0 = XTAL and TCLK pins are connected to a crystal oscillator (see Figure 4).
1 = TCLK input is driven with a single-ended TTL/CMOS clock oscillator (see Figure 7).

0 = All 48K of ROM is internal.
1 = All 48K of ROM is in external ROM using ROM_ADDR15:0 address outputs if
register 0x22 bit 4 is 0. If register 0x22 bit 4 is 1, 0-32K ROM is internal, and

32K~48K ROM is external using ROM_ADDR13:0 address outputs.

Table 16. Bootstrap Signals

June 2002 C2115-DAT-01B

43

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

44..1155 HHoosstt IInntteerrffaaccee

A serial host interface is provided to allow an external device to peek and poke registers in
the gm2115/25. This is done using a 2-wire serial protocol. Note that 2-wire host interface
requires bootstrap settings as described in Table 16.

The 2-wire host interface is suitable for connection to a factory interrogation port. This is
illustrated in Figure 28. The factory test station connects to the gm2115/25 through the Direct
Data Channel (DDC) of the DSUB15. For example, the PC can make gm2115/25 display test
patterns (see section 4.4). A camera can be used to automate the calibration of the LCD
panel.

Figure 28. Factory Calibration and Test Environment

DDC

Device-Under-Test Factory Test Station

Camera

An arbitration mechanism ensures that register accesses from the OCM and the 2-wire host
interface port are always serviced (time division multiplexing).

4.15.1 Host Interface Command Format

Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or
two nibbles respectively). These form an instruction byte, a device register address and/or
one or more data bytes. This is described in Table 17.

The first byte of each transfer indicates the type of operation to be performed by the
gm2115/25. The table below lists the instruction codes and the type of transfer operation. The
content of bytes that follow the instruction byte will vary depending on the instruction
chosen. By utilizing these modes effectively, registers can be quickly configured.

The two LSBs of the instruction code, denoted 'A9' and 'A8' in Table 17 below, are bits 9 and
8 of the internal register address respectively. Thus, they should be set to ‘00’ to select a
starting register address of less than 256, ‘01’ to select an address in the range 256 to 511,
and '10' to select an address in the range 512 to 767. These bits of the address increment in
Address Increment transfers. The unused bits in the instruction byte, denoted by 'x', should be
set to ‘1’.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 17. Instruction Byte Map

Bit

7 6 5 4 3 2 1 0

0 0 0 1 x x A9 A8 Write Address Increment
0 0 1 0 x x A9 A8 Write Address No Increment

1 0 0 1 x x A9 A8 Reserved
1 0 1 0 x x A9 A8 Read Address No Increment

0 0 1 1 x x A9 A8
0 1 0 0 x x A9 A8
1 0 0 0 x x A9 A8
1 0 1 1 x x A9 A8
1 1 0 0 x x A9 A8
0 0 0 0 x x A9 A8
0 1 0 1 x x A9 A8
0 1 1 0 x x A9 A8
0 1 1 1 x x A9 A8
1 1 0 1 x x A9 A8
1 1 1 0 x x A9 A8
1 1 1 1 x x A9 A8

Operation Mode Description

Allows the user to write a single or multiple bytes to a specified starting
address location. A Macro operation will cause the internal address pointer to

(for table loading)

(for table reading)

Reserved

Spare No operation will be performed

increment after each byte transmission. Termination of the transfer will cause
the address pointer to increment to the next address location.
Allows the user to read multiple bytes from a specified starting address
location. A Macro operation will cause the internal address pointer to
increment after each read byte. Termination of the transfer will cause the
address pointer to increment to the next address location.

4.15.2 2-wire Serial Protocol

The 2-wire protocol consists of a serial clock HCLK (pin number 204) and bi-directional
serial data line HFSn (pin number 205). The bus master drives HCLK and either the master
or slave can drive the HFSn line (open drain) depending on whether a read or write operation
is being performed. The gm2115/25 operates as a slave on the interface.

The 2-wire protocol requires each device be addressable by a 7-bit identification number.
The gm2115/25 is initialized on power-up to 2-wire mode by asserting bootstrap pins
HOST_PROTOCOL=0 and the device identification number on HOST_ADDR(6:0) on the
rising edge of RESETn (see Table 16). This provides flexibility in system configuration with
multiple devices that can have the same address.

A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in
the figure below. A transfer is initiated (START) by a high-to-low transition on HFSn while
HCLK is held high. A transfer is terminated by a STOP (a low-to-high transition on HFSn
while HCLK is held high) or by a START (to begin another transfer). The HFSn signal must
be stable when HCLK is high, it may only change when HCLK is low (to avoid being
misinterpreted as START or STOP).

HCLK

HFSn

START

123 789

Receiver acknowledges by holding SDA low

456

ADDRESS BYTE

R/WA6 A1A2A3A4A5 A0 D6D7 D0

ACK

12 89

ACK

DATA BYTE

STOP

Figure 29. 2-Wire Protocol Data Transfer

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Each transaction on the HFSn is in integer multiples of 8 bits (i.e. bytes). The number of
bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the
most significant bit (MSB) first. After the eight data bits, the master releases the HFSn line
and the receiver asserts the HFSn line low to acknowledge receipt of the data. The master
device generates the HCLK pulse during the acknowledge cycle. The addressed receiver is
obliged to acknowledge each byte that has been received.

The Write Address Increment and the Write Address No Increment operations allow one or
multiple registers to be programmed with only sending one start address. In Write Address
Increment, the address pointer is automatically incremented after each byte has been sent and
written. The transmission data stream for this mode is illustrated in Figure 30 below. The
highlighted sections of the waveform represent moments when the transmitting device must
release the HFSn line and wait for an acknowledgement from the gm2115/25 (the slave
receiver).

HCLK

123456789

HFSn

START

DEVICE ADDRES S

123456789

R/W

ACK OPERATI ON CODE

A9

12345678912 9

A8

Two MSBs of regi ster address

REGISTER ADDRESS

DATA

ACKACK

DATA

ACK

STOP

Figure 30. 2-Wire Write Operations (0x1x & 0x2x)

The Read Address No Increment (0xA0) operation is illustrated in Figure 31. The highlighted
sections of the waveform represent moments when the transmitting device must release the
HFSn line and waits for an acknowledgement from the master receiver.

Note that on the last byte read, no acknowledgement is issued to terminate the transfer.

HCLK

HFSn

DEVICE ADDRESS

START

R/W

ACK

OPERATION CODE

REGISTER ADDRESS

ACKACK

START

DEVICE ADDRESS

R/W

ACK

DATA

ACK

DATADATA

Figure 31. 2-Wire Read Operation (0xAx)

STOP

Please note that in all the above operations the operation code includes two address bits, as
described in Table 17.

June 2002 C2115-DAT-01B

46

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

44..1166 MMiisscceellllaanneeoouuss FFuunnccttiioonnss

4.16.1 Power Down Operation

The gm2115/25 provides a low power state in which the clocks to selected parts of the chip may
be disabled (see Table 19).

4.16.2 Pulse Width Modulation (PWM) Back Light Control

Many of today’s LCD back light inverters require both a PWM input and variable DC
voltage to minimize flickering (due to the interference between panel timing and inverter’s
AC timing), and adjust brightness. Most LCD monitor manufacturers currently use a
microcontroller to provide these control signals. To minimize the burden on the external
microcontroller, the gm2115/25 generates these signals directly.

There are three pins available for controlling the LCD back light, PWM0 (GPIO0), PWM1
(GPIO1) and PWM2 (GPIO2). The duty cycle of these signals is programmable. They may
be connected to an external RC integrator to generate a variable DC voltage for a LCD back
light inverter. Panel HSYNC is used as the clock for a counter generating this output signal.

June 2002 C2115-DAT-01B

47

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

5. ELECTRICAL SPECIFICATIONS

The following targeted specifications have been derived by simulation.

55..11 PPrreelliimmiinnaarryy DDCC CChhaarraacctteerriissttiiccss

Table 18. Absolute Maximum Ratings

PARAMETER SYMBOL MIN TYP MAX UNITS

3.3V Supply Voltages

2.5V Supply Voltages
Input Voltage (5V tolerant inputs)
Input Voltage (non 5V tolerant inputs)

Electrostatic Discharge V

Latch-up ILA

Ambient Operating Temperature TA 0 70

Storage Temperature T

Operating Junction Temp. TJ 0 125

Thermal Resistance (Junction to Air) Natural Convection

Thermal Resistance (Junction to Case) Convection or air flow

Soldering Temperature (30 sec.) T

Vapor Phase Soldering (30 sec.) T

NOTE: All voltages are measured with respect to GND

NOTE (1): Absolute maximum voltage ranges are for transient voltage excursions.

NOTE (2): Package thermal resistance is based on a PCB with one signal plane and two power planes. Package θ

four or more layers.

(1)

V

(1)

V

(1)

V

(1)

V

-0.3 3.6 V

VDD_3.3

-0.3 2.75 V

VDD_2.5

-0.3 5.5 V

IN5Vtol

-0.3 3.6 V

IN

ESD

-40 125

STG

θJA

θJC

220

SOL

220

VAP

25.0

14.0

is improved on a PCB with

JA

±2.0

±100

kV

mA

°C

°C

°C

°C/W

°C/W

°C

°C

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 19. DC Characteristics

PARAMETER SYMBOL MIN TYP MAX UNITS

POWER

Power Consumption @ 96 MHz (gm2115) P
Power Consumption @ 135 MHz (gm2125) P

Power Consumption @ Low Power Mode

(1)

P

3.3V Supply Voltages (AVDD and RVDD) V

2.5V Supply Voltages (VDD and CVDD) V

Supply Current @ CLK = 96 MHz (gm2115)

• 2.5V digital supply

• 2.5V analog supply

• 3.3V digital supply

• 3.3V analog supply

(2)

(3)

(4)

I

I

XGA_2.5_AVDD

I

I

XGA_3.3_AVDD

Supply Current @ CLK =135MHz (gm2125)

• 2.5V digital supply

• 2.5V analog supply

• 3.3V digital supply

• 3.3V analog supply

(2)

(3)

(4)

I

I

XGA_2.5_AVDD

I

I

XGA_3.3_AVDD

Supply Current @ Low Power Mode* ILP 140 mA

High Voltage VIH 2.0 VDD V
Low Voltage VIL GND 0.8 V
Clock High Voltage V
Clock Low Voltage V
High Current (VIN = 5.0 V) IIH -25 25
Low Current (VIN = 0.8 V) IIL -25 25
Capacitance (VIN = 2.4 V) CIN 8 pF

High Voltage (IOH = 7 mA) VOH 2.4 VDD V
Low Voltage (IOL = -7 mA) VOL GND 0.4 V
Tri-State Leakage Current IOZ -25 25

NOTE (1): Low power figures result from setting the ADC and clock power down bits.
NOTE (2): Includes pins CVDD_2.5, VDD1_ADC_2.5, VDD2_ADC_2.5
NOTE (3): Includes pins VDD_DPLL, VDD_SDDS, VDD_DDDS and RVDD.
NOTE (4): Includes pins AVDD_RED, AVDD_GREEN, AVDD_BLUE, AVDD_RPLL, AVDD_SDDS and AVDD_DDDS.

TBD W

XGA

TBD W

XGA

TBD W

LP

3.15 3.3 3.45 V

VDD_3.3

2.35 2.5 2.65 V

VDD_2.5

I

XGA

XGA_2.5_VDD

400

TBD
TBD

XGA_3.3_VDD

I

XGA

XGA_2.5_VDD

TBD
TBD

TBD
TBD

XGA_3.3_VDD

TBD
TBD

INPUTS

2.4 VDD V

IHC

GND 0.4 V

ILC

OUTPUTS

mA

mA

µA
µA

µA

55..22 PPrreelliimmiinnaarryy AACC CChhaarraacctteerriissttiiccss

The following targeted specifications have been derived by simulation.

All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum
operating conditions used were: T

16pF for all outputs.

June 2002 C2115-DAT-01B

= 0 to 125° C, Vdd = 2.35 to 2.65V, Process = best to worst, CL =

DIE

49

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 20. Maximum Speed of Operation

Clock Domain Max Speed of Operation

Main Input Clock (TCLK) 24 MHz (14.3MHz recommended)
ADC Clock (ACLK) 162.5 MHz
HCLK Host Interface Clock (2-wire protocol) 5 MHz
Input Format Measurement Clock (IFM_CLK) 50MHz (14.3MHz recommended)
Reference Clock (RCLK) 200MHz (200MHz recommended)
On-Chip Microcontroller Clock (OCM_CLK) 100 MHz
Display Clock (DCLK) 135 MHz

Table 21. Display Timing and DCLK Adjustments

DP_TIMING -> Tap 0 (default) Tap 1 Tap 2 Tap 3

Propagation delay from DCLK to DA*/DB* 1.0 4.5 0.5 3.5 -0.5 2.5 -1.5 1.5
Propagation delay from DCLK to DHS 1.0 4.5 0.5 3.5 -0.5 2.5 -1.5 1.5
Propagation delay from DCLK to DVS 0.5 4.5 0.0 3.5 -1.0 2.5 -2.0 1.5
Propagation delay from DCLK to DEN 1.0 4.5 0.5 3.5 -0.5 2.5 -1.5 1.5

Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the propagation
delay between DCLK and its related signals.

Min
(ns)

Max
(ns)

Min
(ns)

Max
(ns)

Min
(ns)

Max
(ns)

Min
(ns)

Max
(ns)

Table 22. 2-Wire Host Interface Port Timing

Parameter Symbol MIN TYP MAX Units

SCL HIGH time T

SCL LOW time T

SDA to SCL Setup T

SDA from SCL Hold T

Propagation delay from SCL to SDA T

Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)

1.25 us

SHI

1.25 us

SLO

30 ns

SDIS

20 ns

SDIH

10 150 ns

SDO3

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

6. ORDERING INFORMATION

Order Code

gm2115 XGA 208-pin PQFP 96 MHz 0-70°C

gm2125 SXGA 208-pin PQFP 135 MHz 0-70°C

Application Package Speed Temperature

Range

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

7. MECHANICAL SPECIFICATIONS

Figure 32. gm2115/25 208-pin PQFP Mechanical Drawing

D

H

208

D

157

1

52

53

Seating Plane

e

See Detail A

156

E

E

H

105

104

b

c

A

2

1 A

A

y

L

1

L

Detail A

A
A
A2

b
c

D
E

e
H

H
L

L1
y
0

1

D

E

Dimension in mm

Nom

Min

3.92

0.25

3.23

3.15

0.18

0.13

27.90

28.00

28.00

27.90

0.50 BSC

31.20

30.95

30.95

31.20

0.65

0.80

1.60 REF

0

Max

4.07

3.30

0.28

0.23

28.10

28.10

31.45

31.45

0.95

0.10

7

Symbol

June 2002 C2115-DAT-01B

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