Datasheet GDC21D601 Datasheet (HEI)

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GDC21D601

32-Bit RISC MCU

Ver 1.6

HDS-GDC21D601-9908 / 10

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GDC21D601

The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No

responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Hyundai or others.

These Hyundai products are intended for usage in general electronic equipment (office equipment, communication equipment, measuring equipment, domestic electrification, etc.).

Please make sure that you consult with us before you use these Hyundai products in equipment which require high quality and / or reliability, and in equipment which could have major impact to the welfare of human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.

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GDC21D601

TABLE OF CONTENTS

Section 1. Overview.....................................................................................................................8

1. General Description..............................................................................................................8

2. Feature................................................................................................................................10

3. Package..............................................................................................................................12

4. Pin Assignment...................................................................................................................13

5. Pin Descriptions..................................................................................................................15

Section 2. System Architecture ................................................................................................20

1. Internal Bus Architecture.....................................................................................................20

2. Arbiter .................................................................................................................................20

3. System Decoder .................................................................................................................21

4. Memory Map.......................................................................................................................21

5. Memory Format...................................................................................................................22

6. Boot Mode...........................................................................................................................22

7. Multi-Function Pin ...............................................................................................................23

Section 3. ARM720T Core..........................................................................................................24

1. General Description............................................................................................................24

2. Feature................................................................................................................................24

3. Core Block Diagram............................................................................................................26

Section 4. DRAM Controller......................................................................................................27

1. General Description............................................................................................................27

2. Hardware Interface and Signal Description ........................................................................28

3. Functional Description ........................................................................................................31

4. Register Description............................................................................................................34

Section 5. On-Chip SRAM .........................................................................................................37

1. General Description............................................................................................................37

2. Signal Description...............................................................................................................37

3. Function Description...........................................................................................................37

Section 6. Static Memory Controller........................................................................................38

1. General Description............................................................................................................38

2. Signal Description...............................................................................................................39

3. Functional Description ........................................................................................................43

4. Programmer’ s Model..........................................................................................................45

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GDC21D601

Section 7. MCU Controller.........................................................................................................48

1. General Description............................................................................................................48

2. Signal Description...............................................................................................................48

3. Register Description............................................................................................................49

Section 8. Power Management Unit.........................................................................................54

1. General Description............................................................................................................54

2. Hardware Interface and Signal Description ........................................................................55

3. Operation Modes ................................................................................................................56

4. Register Description............................................................................................................58

5. Power Management Unit Register Map..............................................................................63

6. Test Mode Guide for MCU..................................................................................................64

7. Signal Timing Diagram........................................................................................................66

Section 9. Watchdog Timer.......................................................................................................68

1. General Description............................................................................................................68

2. Hardware Interface and Signal Description ........................................................................69

3. Watchdog Timer Introduction .............................................................................................71

4. Watchdog Timer Operation ................................................................................................72

5. Watchdog Timer Memory Map ...........................................................................................74

6. Watchdog Timer Register Descriptions..............................................................................75

7. Examples of Register Setting..............................................................................................77

Section 10. Interrupt Controller................................................................................................81

1. General Description............................................................................................................81

2. Hardware Interface and Signal Description ........................................................................82

3. Interrupt Controller..............................................................................................................84

4. Interrupt Controller Memory Map........................................................................................86

5. Interrupt Controller Register Descriptions...........................................................................87

Section 11. Real Time Clock .....................................................................................................91

1. General Description............................................................................................................91

2. Signal Description...............................................................................................................92

3. Hardware Interface .............................................................................................................93

4. Functional Description ........................................................................................................94

5. Real Time Clock Memory Map ...........................................................................................95

6. Real Time Clock Register Descriptions..............................................................................95

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GDC21D601

Section 12. General Purpose Timer Unit .................................................................................96

1. General Description............................................................................................................96

2. Hardware Interface and Signal Description ........................................................................97

3. General Purpose Timer Unit Introduction.........................................................................100

4. General Purpose Timer Unit Operation............................................................................101

5. General Purpose Timer Unit Memory Map.......................................................................102

6. General Purpose Timer Unit Register Descriptions..........................................................104

7. Examples of Register Setting............................................................................................108

Section 13. PIO.........................................................................................................................111

1. General Description..........................................................................................................111

2. Signal Description.............................................................................................................112

3. Hardware Interface ...........................................................................................................115

4. Functional Description ......................................................................................................116

5. Programmer’ s Model........................................................................................................117

Section 14. Synchronous Serial Peripheral Interface...........................................................118

1. General Description..........................................................................................................118

2. Signal Description.............................................................................................................119

3. Hardware Interface ...........................................................................................................120

4. Functional Description ......................................................................................................121

5. Register Memory Map.......................................................................................................123

6. SSPI Data Clock Timing Diagram.....................................................................................124

Section 15. UART.....................................................................................................................125

1. General Description..........................................................................................................125

2. Features............................................................................................................................125

3. Signal Description.............................................................................................................126

4. Internal Block Diagram......................................................................................................129

5. Registers Description........................................................................................................130

Section 16. Smart Card Interface............................................................................................142

1. General Description..........................................................................................................142

2. Signal Description.............................................................................................................143

3. Hardware Interface ...........................................................................................................144

4. Functional Description ......................................................................................................145

5. Programmer’ s Model........................................................................................................146

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GDC21D601

Section 17. I2C Controller........................................................................................................149

1. General Description..........................................................................................................149

2. I2C Controller Key Features..............................................................................................150

3. I2C Controller Clocking and Pin Functions........................................................................150

4. I2C Master Mode Transmit / Receive Process..................................................................150

5. I2C Restart Capability (Combined Mode)..........................................................................151

6. I2C Controller Programming Model...................................................................................152

7. I2C Module Signal Description ..........................................................................................154

8. Hardware Interface ...........................................................................................................155

9. Register Memory Map.......................................................................................................156

Section 18. Direct Memory Access Controller ......................................................................157

1. General Description..........................................................................................................157

2. Signal Description.............................................................................................................158

3. Programmer’ s Model........................................................................................................159

4. Address Modes.................................................................................................................163

Section 19. Debug and Test Interface....................................................................................167

1. General Description..........................................................................................................167

2. Software Development Debug and Test Interface............................................................167

3. Test Access Port and Boundary Scan..............................................................................167

Section 20. Electrical Ratings.................................................................................................169

1. Absolute Maximum Ratings..............................................................................................169

2. Thermal Characteristics....................................................................................................169

3. D.C Electrical Characteristics ...........................................................................................169

APENDIX A. Register Map.......................................................................................................170

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GDC21D601

32-Bit RISC MCU

Section 1. Overview

1. General Description

The GDC21D601 is the HME’s 32bit high performance microcontroller unit (MCU). The GDC21D601 contains ARM720T, which is a general-purpose 32bit microprocessor, and extensive peripherals: 6 channel 16bit Timer, Watch Dog Timer, 2 channel UART, 2 channel SSPI, 3 channel I2C, Programmable Priority Interrupt Controller, 10 port PIO, 2 channel DMA Controller, External Memory Controller and BUS Controller including chip select logic. ARM720T is a 32bit Microprocessor with the CPU of the ARM7TDMI, 8KB Cache, enlarged write buffer and Memory Management Unit (MMU). The ARM720T is fully software compatible with the ARM processor family.

JTAG[0:4]

RESET

EXPRDY EXPCLK

Mode[0:2]

DRAM OE, WE

WR[0:3], RD

RD&WR

BCLKOUT / PORT F[5]

BWAIT / PORT F[4]

A[0:31] D[0:31]

nCS[4:7] / PORT H[4:7]

RAS[0:1] / PORT G[6:7] CAS[0:3] / PORT G[0:3]

DREQ[0:1] / PORT G[2:3] DACK[0:1] / PORT G[4:5]

IRQ[0:5] / PORT A[0:5]

nCS[0:3]

Bus

controller

DRAM

controller

DMA

controller

INT

controller

JTAG

ASB

APB

32-bit

ARM 720T

Core

AMBA Logic

APB Bridge

MCU

controller

Internal

SRAM

(8KB)

GDC21D601

RTC

Timer

UART

I2C

controller

SSPI

PIO

PMU

WDT

RTCin/Out (32.768kHz)

PORT B[0:7] / Timer TCIO / PWM PORT C[0:3] / Timer TCIO / PWM TCLK A,B,C / PORT C[4:6]

UART channel 0 , 1 SMART Card / UART channel 2 ( PORT D[0:7] ,PORT E[0:4] )

I2C channel 0 I2C channel 1 I2C channel 2

SSPI 0, 1 ( PORT E[5:7], PORT F[0:4] )

PORT I[0:7] PORTJ[0:7]

NPDM

WDTOUT

Figure. 1 GDC21D601 Block Diagram

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GDC21D601

The general descriptions of the GDC21D601 like following :

• On-Chip Modular Architecture (using AMBA)

• Utilizes the ARM720T(“ARM7TDMI with 8Kbyte Cache and MMU”) 32bit RISC Family

• 8Kbyte internal SRAM

• support 8bit/16bit/32bit external Data bus width

• Eight Programmable Chip Select Outputs with EXPRDY

• Support Little and Big Endian memory format

• Low Power Consumption using Power Management Unit

• Fully static operation : Max. 80MHz

• Two 32bit DMA Controllers (External request only)

• Programmable Priority Interrupt Controller (6 external sources)

• Two DRAM Banks Support

• Six 16bit Multi Function Timers / Counters for General Purpose Applications

• One 8bit Watch Dog Timer (WDT)

• Real Time Clock : 32.768 KHz

• Three UARTs (Universal Asynchronous Receiver Transmitter) compatible with 16C550 UART, one

UART with Smart card interface

• Two SSPIs (Synchronous Serial Peripheral Interface) with FIFO

• Three I2C Master/Slave Controllers

• Programmable Input/Output (8bit 10 channel)

• 208 MQFP Package

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2. Feature

GDC21D601

• ARM720T Core

- This is an ARM7TDMI CPU core with . 8KB cache . enlarged write buffer . MMU(Memory Management Unit) . On-chip ICEbreaker debug support . 32-bit x 8 hardware multiplier . Thumb decompressor . High-performance 32-bit RISC architecture . High-density 16-bit insturction set Enhanced ARM software toolkit

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

The MMU supports 4G bytes Virtual address. The allocation of virtual addresses with different task ID improves performance in task switching operations with the cache enabled.

• DMA Controller

- Two Channels with identical function

- Four Gigabytes of address space

- 256 Kbytes transfers to the maximum

- Data Transfer unit : Byte, Half-word, Word

- Two kinds of Bus mode . Burst mode . Exception mode(Cycle steal)

- Two kinds of address mode . Single address mode . Dual address mode

- Two types of Transfer request source

. External I/O request . Auto-request

- Two kind of fixed priority for channels

- Interrupted when the data transfers are

complete

• DRAM Controller

- DRAM access

- Support Word, Half-word, and Byte transaction

- CBR refresh in normal operation and self-refresh

in power-down mode

- Support programmable refresh rate

- Support various DRAM access time by setting

the wait count control register

• Static Memory Controller

- Chip Select up to 8 (Each Bank is 256 MByte)

- Exchangeable Chip Select Active High/Low (CS6 and CS7 only)

- Little-Endian and Big-Endian Memory Support

- Programmable wait-state (up to 16 wait-state)

- Support External BUS Ready Strobe

- Support various type Bus Control timing

- Support Word, Half-word, and Byte transaction

• On-Chip SRAM

- 8k Bytes(2048x32)

- Asynchronous SRAM

- Can write 8/16/32bits data, and read 32bits data

• MCU Controller

- The Memory Map Structure Control signals

- DRAM Power-Down Request and Powr-Down

Ack signal

- Generate the Multi Function Pin control signals

- Device Code : $GDC601

• Power Management Unit

- Power On Reset, WD_OF Reset, and S/W Reset

- Status : RESET, Power Down, RUN_FAST, RUN_SLOW

- Provide separated clock for each modules on chip

- Provide BCLKOUT, WD_OF, Power-Down pins for external devices

• Watch Dog Timer

- Watchdog timer mode & interval timer mode

- Eight counter clock sources

- Generate the Power Down reset or the Watch

Dog Overflow

• Interrupt Controller

- Asynchronous interrupt controller

- Six external interrupt

- Twenty internal interrupt

- Level or edge triggered

- Mask for each interrupt source

Request of IRQ, FIQ for each interrupt source

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GDC21D601

• Real Time Clock

- 32bit counter clocked by a 32.768KHz clock.

- 32bit match register

• Programmable Input Output

- up to 80 pin (8bit 10channel)

- Each pin can be configurable as either input or output

• Timer

- 6 channel 16-bit up-count

- 4-internal pre-scaleable , 4-external input clock

. 1 interrupt per 1 channel . 2 inout pin per 1 channel for input capture or output compare

- Basic function :

. Compare match waveform output . Input capture . Match clear . Capture clear

- Synchronous mode

. Synch. clear at two or more channel . Synch. write at two or more channel

- PWM waveform output mode

• Synchronous Serial Interface

- Supports full duplex communication

- Sends and receives data continuously, using 16 x 8 bit FIFOs

- Built-in baud rate generator capable of

generation 4 clock rate

- Selectable clock source : either built-in buad-rate generator or external clock

- 4 independent interrupts : transmit-end, rx-full, tx-empty and tx-full

• UART

- 2 channel : UART only . Compatible with 16550 . 16 byte each FIFO for TX / RX . Start, stop and parity bit can be added or

deleted from/to serial data

. MODEM control functions (CTS, RTS, DSR,

DTR, RI and DCD ) . Fully programmable serial-interface characteristics

: 5-, 6-, 7- or 8-bit characters : even, odd or no-parity bit generation and detection : 1-, 1.5- or 2-stop bit generation and detection

• SmartCard Interface

- 1 channel : Support SmartCard Interface . Supports only asynchronous operation . Supports cards that have internal reset capability . Supports cards that have an active low reset input . Supports cards that use the internal clock . Generate the clock for a card expecting the external clock . Use the serial in/out ports for I/O . Use the PIO ports for other interface signals like RST, DETECT, etc

• I2C

- 3 channels

- Master / Slave function

- Programmable clock speed

- 8bit data transfer

- Slave clock stretch support

- Maskable interrupt

- Support clock rates up to 1.84MHz Baud

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3. Package

9921

Rev. ES

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129

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117

116

115

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106

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153

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134

45464748495051

156

155

154

HME

32bit MCU

GDC21D601

157 158

159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

ARM

GDC21D601R1

(Top View)

104 103 102 101 100 99 98 97

96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

Figure 2. Package Outline

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GDC21D601

4. Pin Assignment

PIN NAME PIN NAME PIN NAME PIN NAME

1 A0 45 IRQ0/PA0 89 VDD 133 NRAS0/PG6 2 A1 46 VDD 90 SMDI/PE2 134 VSS 3 VDD 47 IRQ1/PA1 91 SMDO/PE3 135 NRAS1/PG7 4 A2 48 IRQ2/PA2 92 SMCLK/PE4 136 NCAS0/PH0 5 A3 49 IRQ3/PA3 93 VSS 137 NCAS1/PH1 6 A4 50 VSS 94 SIN0/ PE5 138 NCAS2/PH2 7 VSS 51 IRQ4/PA4 95 8 A5 52 IRQ5/PA5 96 SCLK0/PE7 140 VSS

9 A6 53 PA6 97 VDD 141 XOUT 10 A7 54 PA7 98 11 VDD 55 TCIOA0/PB0 99 12 A8 56 VDD 100 13 A9 57 TCIOB0/PB1 101 VSS 145 NDRAMWE 14 A10 58 TCIOA1/PB2 102 15 VSS 59 TCIOB1/PB3 103 SCS1/PF4 147 NWR0 16 A11 60 VSS 104 BCLKOUT/PF5 148 NWR1 17 A12 61 TCIOA2/PB4 105 NFIQOUT/PF6 149 NWR2 18 VDD 62 TCIOB2/PB5 106 NIRQOUT/PF7 150 VDD 19 A13 63 TCIOA3/PB6 107 VDD 151 NWR3 20 A14 64 VDD 108 I2CSDA0 152 NRD 21 A15 65 TCIOB3/PB7 109 I2CSCL0 153 RDNWR 22 VSS 66 PC0/TCIOA4 110 I2CSDA1 154 VSS 23 A16 67 PC1/TCIOB4 111 VSS 155 NEXPRDY 24 A17 68 VSS 112 I2CSCL1 156 EXPCLK 25 A18 69 PC2/TCIOA5 113 I2CSDA2 157 NCS0 26 VDD 70 PC3/TCIOB5 114 I2CSCL2 158 NCS1 27 A19 71 PC4/TCLKA 115 VDD 159 NCS2 28 A20 72 VDD 116 Mode0/TREQA 160 VDD 29 A21 73 PC5/TCLKB 117 Mode1/TREQB 161 NCS3 30 VSS 74 PC6/TCLKC 118 Mode2/TACK 162 NCS4/PH4 31 A22 75 PC7/TCLKD 119 VSS 163 NCS5/PH5 32 A23 76 RXD0/PD0 120 UCLKOUT 164 VSS 33 WDTOUT 77 VSS 121 UCLKIN 165 CS6/PH6 34 NPDN 78 TXD0/PD1 122 VDD 166 CS7/PH7 35 VSS 79 RXD1/ PD2 123 TEST 167 D31/PJ7 36 RTCOSCIN 80 TXD1/PD3 124 NEXTREQ/PG0 168 VDD 37 RTCOSCOUT 81 VDD 125 NRESET 169 D30/PJ6 38 VDD 82 NCTS/ PD4 126 VSS 170 D29/PJ5 39 NTRST 83 NDSR/ PD5 127 NEXTACK/PG1 171 D28/PJ4 40 TDI 84 NDCD/ PD6 128 NDREQ0/PG2 172 VSS 41 TCK 85 VSS 129 NDACK0/PG3 173 D27/PJ3 42 VSS 86 NRI/ PD7 130 VDD 174 D26/PJ2 43 TDO 87 NDTR/PE0 131 NDREQ1/PG4 175 D25/PJ1 44 TMS 88 NRTS/PE1 132 NDACK1/PG5 176 VDD

SOUT0/PE6

SCS0/PF0/MemByte0

SIN1/PF1/MemByte1

SOUT1/PF2

SCLK1/PF3

139 NCAS3/PH3

142 XIN 143 VDD 144 NDRAMOE

146 VSS

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GDC21D601

PIN NAME PIN NAME PIN NAME PIN NAME

177 D24/PJ0 185 VDD 193 VDD 201 VDD 178 D23/PI7 186 D17/PI1 194 D11 202 D5 179 D22/PI6 187 D16/PI0 195 D10 203 D4 180 D21/PI5 188 D15 196 D9 204 D3 181 VSS 189 VSS 197 VSS 205 VSS 182 D20/PI4 190 D14 198 D8 206 D2 183 D19/PI3 191 D13 199 D7 207 D1 184 D18/PI2 192 D12 200 D6 208 D0

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5. Pin Descriptions

PIN NUMBER PIN NAME TYPE DESCRIPTION

1~2, 4~6, 8~10,

12~14, 16~17, 19~21, 23~25,

27~29, 31~32

33 WDTOUT O Watch Dog Timer Overflow Output 34 NPDN O Power Down Signal from PMU block

37 RTCOSCIN I Real Time Clock Oscillator Input 32.768kHz 36 RTCOSCOUT O Real Time Clock Oscillator Output 39 NRST I JTAG Reset 40 TDI I JTAG Data Input 41 TCK I JTAG Clock Input 43 TDO O JTAG Data Output 44 TMS I JTAG Mode Signal 45

53 PA6 I/O PIO Port A[6]

54 PA7 I/O PIO Port A[7]

A[31:0] O Address Bus

Valid After RESET.

When it is LOW, MCU entered the power down mode. When HIGH, normal

IRQ0 External Interrupt Input 0, when PINMUX_PA[0] = 0

PA0 IRQ1 External Interrupt Input 1, when PINMUX_PA[1] = 047 PA1 IRQ2 External Interrupt Input 2, when PINMUX_PA[2] = 048 PA2 IRQ3 External Interrupt Input 3, when PINMUX_PA[3] = 049 PA3 IRQ4 External Interrupt Input 4, when PINMUX_PA[4] = 051 PA4 IRQ5 External Interrupt Input 5, when PINMUX_PA[5] = 052 PA5

TCIOA0 Timer Channel 0 Input Capture A, when PINMUX_PB[0] = 055 PB0 TCIOB0 Timer Channel 0 Input Capture B, when PINMUX_PB[1] = 057 PB1 TCIOA1 Timer Channel 1 Input Capture A, when PINMUX_PB[2] = 058 PB2 TCIOB1 Timer Channel 1 Input Capture B, when PINMUX_PB[3] = 059 PB3 TCIOA2 Timer Channel 2 Input Capture A, when PINMUX_PB[4] = 061 PB4 TCIOB2 Timer Channel 2 Input Capture B, when PINMUX_PB[5] = 062 PB5

I/O

Programmable I/O ports. Each pin can be mapped to specified function pin name. (External IRQ0,IRQ1,…)

PIO Port A[0], when PINMUX_PA[0] = 1

I/O

PIO Port A[1], when PINMUX_PA[1] = 1

I/O

PIO Port A[2], when PINMUX_PA[2] = 1

I/O

PIO Port A[3], when PINMUX_PA[3] = 1

I/O

PIO Port A[4], when PINMUX_PA[4] =1

I/O

PIO Port A[5], when PINMUX_PA[5] = 1

Tbclk Clock Input for TIC test

Tfclk Clock Input for TIC test

I/O

PIO Port B[0], when PINMUX_PB[0] = 1

I/O

PIO Port B[1], when PINMUX_PB[1] = 1

I/O

PIO Port B[2], when PINMX_PB[2] = 1

I/O

PIO Port B[3], when PINMUX_PB[3] = 1

I/O

PIO Port B[4], when PINMUX_PB[4] = 1

I/O

PIO Port B[5], when PINMUX_PB[5] = 1

GDC21D601

Page 15

PIN NUMBER PIN NAME TYPE DESCRIPTION

TCIOA3 Timer Channel 3 Input Capture A, when PINMUX_PB[6] = 063 PB6 TCIOB3 Timer Channel 3 Input Capture B, when PINMUX_PB[7] = 065 PB7 PC0 PIO Port C[0], when PINMUX_PC[0] = 066 TCIOA4 PC1 PIO Port C[1], when PINMUX_PC[1] = 067 TCIOB4 PC2 PIO Port C[2], when PINMUX_PC[2] = 069 TCIOA5 PC3 PIO Port C[3], when PINMUX_PC[3] = 070 TCIOB5 PC4 PIO Port C[4], when PINMUX_PC[4] = 071 TCLKA PC5 PIO Port C[5], when PINMUX_PC[5] = 073 TCLKB PC6 PIO Port C[6], when PINMUX_PC[6] = 074 TCLKC PC7 PIO Port C[7], when PINMUX_PC[7] = 075 TCLKD RXD0 UART Channel 0 Receive Data, when PINMUX_PD[0] = 076 PD0 TXD0 UART Channel 0 Transmit Data, when PINMUX_PD[1] = 078 PD1 RXD1 UART Channel 1 Receive Data, when PINMUX_PD[2] = 079 PD2 TXD1 UART Ch 1 Transmit Data, when PINMUX_PD[3] = 080 PD3 NCTS UART Ch 1 Clear to Send, when PINMUX_PD[4] = 082 PD4 NDSR UART Ch 1 Data Set Ready, when PINMUX_PD[5] = 083 PD5 NDCD UART Ch 1 Data Carrier Detect, when PINMUX_PD[6] = 084 PD6 NRI UART Ch 1 Ring Indicator, when PINMUX_PD[7] = 086 PD7 NDTR UART C 1 Data Terminal Ready, when PINMUX_PE[0] = 087 PE0 NRTS UART Ch 1 Ready to Send Data, when PINMUX_PE[1] = 088 PE1 SMDI Smart Card Interface Data In, when PINMUX_PE[2] = 090 PE2 SMDO I/O Smart Card Interface Data Out, when PINMUX_PE[3] = 091 PE3 PIO Port E[3], when PINMUX_PE[3] =1 SMCLK I/O Smart Card Interface Clock Out, when PINMUX_PE[4] = 092 PE4 PIO Port E[4], when PINMUX_PE[4] = 1

I/O

PIO Port B[6], when PINMUX_PB[6] = 1

I/O

PIO Port B[7], when PINMUX_PB[7] = 1

I/O

Timer Channel 4 Input Capture A, when PINMUX_PC[0] = 1

I/O

Timer Channel 4 Input Capture B, when PINMUX_PC[1] = 1

I/O

Timer Channel 5 Input Capture A, when PINMUX_PC[2] = 1

I/O

Timer Channel 5 Input Capture B, when PINMUX_PC[3] = 1

I/O

External Timer Clock Source A, when PINMUX_PC[4] = 1

I/O

External Timer Clock Source B, when PINMUX_PC[5] = 1

I/O

External Timer Clock Source C, when PINMUX_PC[6] = 1

I/O

External Timer Clock Source D, when PINMUX_PC[7] = 1

I/O

PIO Port D[0], when PINMUX_PD[0] = 1

I/O

PIO Port D[1], when PINMUX_PD[1] =1

I/O

PIO Port D[2], when PINMUX_PD[2] = 1

I/O

PIO Port D[3], when PINMUX_PD[3] =1

I/O

PIO Port D[4], when PINMUX_PD[4] = 1

I/O

PIO Port D[5], when PINMUX_PD[5] = 1

I/O

PIO Port D[6], when PINMUX_PD[6] = 1

I/O

PIO Port D[7], when PINMUX_PD[7] =1

I/O

PIO Port E[0], when PINMUX_PE[0] = 1

I/O

PIO Port E[1], when PINMUX_PE[1] = 1

I/O

PIO Port E[2], when PINMUX_PE[2] = 1

GDC21D601

Page 16

PIN NUMBER PIN NAME TYPE DESCRIPTION

SIN0 SSI Channel 0 Data In, when PINMUX_PE[5] = 0

I/O

PE5 PIO Port E[5], when PINMUX_PE[5] =1

BPROT0 SOUT0 SSI Channel 0 Data Out, when PINMUX_PE[6] = 0

I/O

AMNA BPROT[0] Signal, when PINMUX_PE[8] = 1

PE6 PIO Port E[6], when PINMUX_PE[6] = 1

BPROT1 SCLK0 SSI Channel 0 Clock Out, when PINMUX_PE[7] = 0

I/O

AMBA BPROT[1] Signal, when PINMUX_PE[8] = 1

PE7 PIO Port E[7], when PINMUX_PE[7] =1

BLOK SCS0 SSI Channel 0 Channel Control, when PINMUX_PF[0] = 0

I/O

AMBA BLOK Signal Out, when PINMUX_PE[8] = 1

PF0 PIO Port F[0], when PINMUX_PF[0] = 1

MemByte0 SIN1 SSI Channel 1 Data In, when PINMUX_PF[1] = 0

I/O

MemByte[0] Signal from EBI Block, when PINMUX_PF[8] = 1

PF1 PIO Port F[1], when PINMUX_PF[1] = 1

100

MemByte1 SOUT1 SSI Channel 1 Data Out, when PINMUX_PF[2] = 0

I/O

MemByte[1] Signal from EBI Block, when PINMUX_PF[8] = 1

PF2 PIO Port F[2], when PINMUX_PF[2] = 1

102

BTRANS0 SCLK1 SSI Channel 1 Clock Out, when PINMUX_PF[3] = 0

I/O

AMBA BTRANS[0] Signal, when PINMUX_PF[8] = 1

PF3 PIO Port F[3], when PINMUX_PF[3] = 1

103

BTRANS[1] SCS1 SSI Channel 1 Channel Control, when PINMUX_PF[4] = 0

I/O

AMBA BTRANS[1] Signal, when PINMUX_PF[8] = 1

PF4 PIO Port F[4], when PINMUX_PF[4] =1 BWAIT BCLKOUT AMBA BCLK Signal, when PINMUX_PF[5] = 0104 PF5 NFIQOUT AMBA NFIQ Signal, when PINMUX_PF[6] = 0105 PF6 NIRQOUT AMBA NIRQ Signal, when PINMUX_PF[7] = 0106 PF7

I/O

AMBA BWAIT Signal, when PINMUX_PF[8] = 1

PIO Port F[5], when PINMUX_PF[5] = 1

PIO Port F[6], when PINMUX_PF[6] =1

PIO Port F[7], when PINMUX_PF[7] = 1

108 I2CSDA0 I/O Data Signal for I2C Channel 0

Pins (108~110,112~114) are required to be pull-up externally.

When bus is free, this pin goes logical “HIGH” After reset, SDA pins enter Idle state

109 I2CSCL0 I/O Clock Signal for I2C Channel 0 110 I2CSDA1 I/O Data Signal for I2C Channel 1 112 I2CSCL1 I/O Clock Signal for I2C Channel 1 113 I2CSDA2 I/O Data Signal for I2C Channel 2 114 I2CSCL2 I/O Clock Signal for I2C Channel 2 116

Mode0 Boot Mode0, when TEST pin = 0

By default, 32-bit access

( MCU can boot from 32- bit Memory)

TREQA

TREQA Signal for TIC Test,

when TEST pin = 1 Mode1 Boot Mode 1117 TREQB

TREQB Signal for TIC Test

Mode[0:1] = 00 32-bit Mode[0:1] = 01 8-bit Mode[0:1] = 10 16-bit

Mode[0:1] = 11 Reserved

GDC21D601

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GDC21D601

PIN NUMBER PIN NAME TYPE DESCRIPTION

118

120 UCLKIN I UART Clock Oscillator Clock Input

121 UCLKOUT O UART Clock Oscillator Clock Output 123 TEST I Test Input Pin, Select 116~118 pin as Boot Mode or TIC Signal

125 NRESET I System Power On Reset Input

142 XIN I System Clock Input (<80MHz)

141 XOUT O System Clock Oscillator Output 144 NDRAMOE O DRAM Output Enable 145 NDRAMWE O DRAM Write Enable 147 NWR0 O Write Enable 0 for Static Memory(Byte) 148 NWR1 O Write Enable 1 for Static Memory(Byte) 149 NWR2 O Write Enable 2 for Static Memory(Byte) 151 NWR3 O Write Enable 3 for Static Memory(Byte)

Mode 2 Boot Mode 2 (BigEndian Pin)

TACK

NEXTREQ External Master Request Bus Mastership, when PINMUX_PG[0] = 0124 PG0

NEXTACK Bus Granted Signal for External Master, when PINMUX_PG[1] = 0127 PG1 NDREQ0 DMA Channel 0 Request, when PINMUX_PG[2] = 0128 PG2 NDACK0 DMA Channel 0 Acknowledge, when PINMUX_PG[3] = 0129 PG3 NDREQ1 DMA Channel 1 Request, when PINMUX_PG[4] = 0131 PG4 NDACK1 DMA Channel 1 Acknowledge, when PINMUX_PG[5] = 0132 PG5 NRAS0 DRAM Bank #0 RAS Signal, when PINMUX_PG[6] = 0133 PG6 NRAS1 DRAM Bank #1 RAS Signal, when PINMUX_PG[7] = 0135 PG7 NCAS0 DRAM CAS0 Signal, when PINMUX_PH[0] = 0136 PH0 NCAS1 DRAM CAS1 Signal, when PINMUX_PH[1] = 0137 PH1 NCAS2 DRAM CAS2 Signal, when PINMUX_PH[2] = 0138 PH2 NCAS3 DRAM CAS3 Signal, when PINMUX_PH[3] = 0139 PH3

I/O

Big-endian Selection Pin, when this pin = 1(HIGH)

Note) When this pin is HIGH, External Data will be transferred “Big-endian” format.

TACK Signal for TIC Test

UART block dedicated clock source supported.

(This clock source is used for UART and SMART Card Only)

I/O

PIO Port G[0], when PINMUX_PG[0] = 1

To ensure proper initialization after power is stable,

assert NRESET pin for at least 20µs

I/O

PIO Port G[1] = 1, when PINMUX_PG[1] = 1

I/O

PIO Port G[2], when PINMUX_PG[2] = 1

I/O

PIO Port G[3], when PINMUX_PG[3] = 1

I/O

PIO Port G[4], when PINMUX_PG[4] = 1

I/O

PIO Port G[5], when PINMUX_PG[5] = 1

I/O

PIO Port G[6], when PINMUX_PG[6] = 1

I/O

PIO Port G[7], when PINMUX_PG[7] = 1

I/O

PIO Port H[0], when PINMUX_PH[0] = 1

I/O

PIO Port H[1], when PINMUX_PH[1] = 1

I/O

PIO Port H[2], when PINMUX_PH[2] = 1

I/O

PIO Port H[3], when PINMUX_PH[3] = 1

External TTL oscillator input

Page 18

PIN NUMBER PIN NAME TYPE DESCRIPTION

152 NRD O Output Enable Signal for Static Memory 153 RDNWR O Read/Write Signal 155 EXPRDY I Ready Signal Input

When this pin is Low, current memory transfer extended.

156 EXPCLK O Clock Output Signal

Active only during external cycles.

Output is same phase and speed as the bus clock

157 NCS0 O Chip Select Signal for Bank #0

NCS pins are required to be Pull-up for proper operation.

All NCS pins are Active Low See Fig.1 memory Map(Section 2)

158 NCS1 O Chip Select Signal for Bank #1 159 NCS2 O Chip Select Signal for Bank #2 161 NCS3 O Chip Select Signal for Bank #3 162 NCS4 I/O Chip Select Signal for Bank #4, when PINMUX_PH[4] = 0

PH4 PIO Port H[4], when PINMUX_PH[4] = 1

165

166

167, 169~171,

NCS5 Chip Select Signal for Bank #5, when PINMUX_PH[5] = 0163 PH5 CS6 Chip Select Signal for Bank #6, when PINMUX_PH[6] = 0

PH6 CS7 Chip Select Signal for Bank #7, when PINMUX_PH[7] = 0

PH7 D[31:0] I/O Data Bus

I/O

PIO Port H[5], when PINMUX_PH[5] = 1

I/O

CS6 pin can be programmed active HIGH/LOW

PIO Port H[6], when PINMUX_PH[6] = 1

I/O

CS7 pin can be programmed active HIGH/LOW

PIO Port H[7], when PINMUX_PH[7] = 1

173~175, 177~180, 182~184, 186~188, 190~192, 194~196, 198~200, 202~204,

206~208

167, 169~171,

PJ[7:0] I/O PIO Port J[7:0], when PINMUX_PJ[7:0] = 1

173~175, 177

178~180, 182~184,

PI[7:0] I/O PIO Port I[7:0] , when PINMUX_PJ[7:0] = 1

186~187

3, 11, 18, 26, 38,

VDD I Power

46, 56, 64, 72, 81,

89, 97, 107, 115, 122, 130, 143, 150, 160, 168, 176, 185,

193, 201

7, 15, 22, 30, 35,

VSS I Ground

42, 50, 60, 68, 77,

85, 93, 101, 111, 119, 126, 134, 140, 146, 154, 164, 172,

181, 189, 197, 205

GDC21D601

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GDC21D601

Section 2. System Architecture

1. Internal Bus Architecture

The GDC21D601 take the advantage of the AMBA(Advanced Micro-controller Bus Architecture) as the internal Bus Architecture. The AMBA specification defines an on-chip communication standard for designing highperformance embedded micocontrollers. Two distinct buses are defined within the AMBA:

- the Advanced System Bus (ASB)

- the Advanced Peripheral Bus (APB)

The AMBA ASB is for high-performance system modules. The modules connected to ASB are DRAM Controller, Static Memory Controller, DMA Controller, On-Chip SRAM, ARM720T CPU Core, Arbiter, Decoder, APB Bridge, and TIC. The AMBA APB is for low-power peripherals. AMBA APB is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. The modules connected to APB are PIO, Interrupt Controller, PMU, WDT, RTC, Timer, UART, SSPI, and I2C. See also AMBA Specification Rev. D (ARM IHI 0001D), and AMBA Specification Rev. 2.0 (ARM IHI 0011A) for detail.

2. Arbiter

The AMBA bus specification is a multi-master bus standard. As a result, a bus arbiter is needed to ensure that only one bus master has an access to the bus at any particular point of time. Each bus master can request the bus; the Arbiter decides which has the highest priority and issues a grant signal accordingly. The GDC21D601 can have the four bus master: ARM720T CPU Core, DMA Controller, TIC, and External Bus Master.

Every system must have a default bus master which grants the use of bus during reset, when no other bus master requires the bus. During Power On Reset, the arbiter will grant the use of bus to the default bus master and hold all other grant signals inactive. The ARM720T Core, the default bus master will grant for the use of bus under the following conditions: Reset, standby, power-down, and no other master requesting the bus

The arbiter processes the requests of the ownership of the ASB and grants one ASB master according to the arbitration scheme. The arbitration scheme of this implementation is a simple priority encoded scheme where the highest priority master requesting the ASB is granted. The priority order is as follows:

Case 1) Aripri = ‘0’

1. TIC

2. DMA

3. External BUS Master

4. ARM (default bus master)

Case 2) Aripri = ‘1’

1. TIC

2. External BUS Master

3. DMA

4. ARM (default bus master)

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GDC21D601

3. System Decoder

The decoder in an AMBA system is used to perform a centralized address decoding function, which gives two main advantages:

- It improves the portability of peripherals, by making them independent of the system memory map.

- It simplifies the design of bus slaves, by centralizing the address decoding and bus control functions.

The decoder performs three main tasks:

- address decoder

- default transfer response

- protection unit

The decoder generates a select signal for each slave on the ASB bus and, under certain circumstances, will not select any slaves and provide the transac-tion response itself. The MCU System Memory Map is shown in Figure 1.

The decoder greatly simplifies the slave interface and removes the need for the slave to understand the different types of transfer that may occur on the bus.

4. Memory Map

The system decoder controls the memory map of the system and generates a slave select signal for each memory region.

The ReMap signal is used to provide a different memory map: ROM is required at address 0 when power on reset, and RAM also may be used at address 0 during normal operation. The ReMap signal is typically provided by a Power Management Unit (PMU) which drives ReMap to LOW at reset. The signal is only driven to HIGH after a particular register in the PMU is accessed (See Section. 9 Power Management Unot for detail). When ReMap is HIGH and isram signal is HIGH, then Memory Map Configuration is MODE A which the internal SRAM is located at address 0x00. And When ReMap is HIGH and drambank0 signal is HIGH, then Memory Map Configuration is Mode B which the DRAM bank #0 is located at address 0x00. The isram and drambank0 signal come from MCU Controller. See Section 8. MCU Controller for detail.

Figure 2. Memory map configuration shows both the Reset (MODE R) and the Normal (MODE B and MODE A) memory map

Figure 1. shows the system memory map.

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GDC21D601

5. Memory Format

The ARM720T CPU Core supports both the Big-Endian and Little-Endian format. And the GDC21D601 can also support the Big-Endian and Little-Endian memory format. The GDC21D601 can support the Little-Endian Format by default. When using the GDC21D601 as Big-Endian format: 1) set Boot Mode 2 pin to VDD, and 2) set the ARM720T as Big-Endian mode with using Coprocessor instruction. 3) set the Big-Endian flag of the compile options when compile. The example of the coprocessor instruction is in the below. It is noted that CP15 register (CPU control register) can only be accessed with MRC and MCR instructions in a Privileged mode. See the ARM720T Data Sheet (ARM DDI 0087D) for detail. The ARM720T Data Sheet is downloadable from ARM home page (http://www.arm.com).

For example :

MRC p15, 0, r3, c1, c1 ORR r3, r3, #0x80 MCR p15, 0, r3, c1, c1

Note : The GDC21D601 has a EBI (External Bus Interface) block which can copy the Byte or HalfWord of the lower position in data bus to higher data bus position, so you can use the GDC21D601 as BigEnd mode by only set the Boot Mode 2 pin to VDD and in this case you may not set the ARM720T as BigEnd Mode.

6. Boot Mode

The GDC21D601 can support 32/16/8 Bit Boot ROM. By default MCU can boot from 32 bit ROM. In this case Boot Mode[1:0] (pin number 116 and 117) are “00”. If you want use 16 bit Boot ROM, then you must set Boot Mode[1:0] are “10”. And in case of Booting from 8 bit ROM, you must set Boot Mode[1:0] are “01”. It is for reserved in case that Boot Mode[1:0] are “11” . See the Table 1. The Description of the Mode Pin. In all case of boot mode the wait cycle of Boot area is 3 cycles. If you want to know about boot mode for detail you must see the Section 6. Static Memory Controller.

Table 1. The Description of the Mode Pin

Mode[1:0] Bus width of Booting ROM

00 32 Bit 01 8 Bit 10 16 Bit 11 Reserved

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GDC21D601

Address

0x00FFFFFF

0x00000FFF

0x00000000

MODE R

MODE A

MODE B

0x01FFFFFF

0x2FFFFFF

nCS0

nCS1

nCS2

On-Chip RAM

nCS0 or

DRAM #0

nCS1

nCS2

nCS1

DRAM #0

7. Multi-Function Pin

The GDC21D601 has 80 Bit PIO pins with multiplexed by other functional pins. So you must use properly these multi-function pins by setting the PINMUX control registers in MCU controller. (See Section 8. MCU Controller for detail)

0XFFFF FFFF

0XFFFF F000

0XFFFF E000

0X0800 0000

0X0000 0000

APB Register

ASB Register

MEMORY AREA

Chip Select Area

0XFFFF FFFF

FD00

FC00 FB00

FA00 F900 F800

F700 F600

F500 F400 F300 F200 F100 F000 EF00 EE00 ED00 EC00 EB00

Reserved

PIO

I2C2 I2C1 I2C0

SSI

UART2/Smart

UART1 UART0

TIMER

RTC INTC

WDT PMU

DMAC DRAMC SMI MCUC

Figure 1. System Memory Map

0XFFFF EAFF

0X6000 0000 0X5000 0000

0X4000 0000

0X3000 0000

0X2000 0000

0X1000 1000 0X1000 0000

0X0800 0000 0X0700 0000 0X0600 0000 0X0500 0000 0X0400 0000 0X0300 0000 0X0200 0000 0X0100 0000 0X0000 0000

Reserved

ARM7 TEST REG

Reserved

DRAM BANK #1

DRAM BANK #0

WINDOW AREA

ON-CHIP RAM

WINDOW AREA

nCS7 nCS6 nCS5 nCS4 nCS3 nCS2 nCS1 nCS0

1. MODE R : Reset Mode : default mode from power-on reset (ReMap is LOW)

2. MODE A : On-Chip SRAM in 0x0000 ~ 0x07FF range : ReMap is HIGH and isram is HIGH

3. MODE B : DRAM Bank #0 in 0x00000000 ~ 0x00FFFFFF range : Remap is HIGH and drambank0 is HIGH

Figure 2. Memory Map Configuration

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GDC21D601

Section 3. ARM720T Core

1. General Description

ARM720T is 32bit microprocessor of general purpose with 8KB cache, enlarged write buffer and Memory Management Unit (MMU), which are combined in a single chip. The CPU within ARM720T is the ARM7TDMI. The ARM720T is software compatible with the ARM processor family. The ARM7TDMI is a member of the ARM family of general purpose 32bit microprocessors, which offers high performance for very low power consumption and price. This processor employs a unique architectural strategy known as THUMB, which makes it ideally suited to high volume applications with memory restrictions or applications where code density is an issue. The key idea behind THUMB is a super reduced instruction set. Essentially, the ARM7TDMI has two instruction sets, the standard 32bit ARM set and 16bit THUMB set. The THUMB set’s 16bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM`s performance advantage over a traditional 16bit processor by using 16bit registers. This is possible because THUMB code operates on the same 32bit register set as ARM code.

See also ARM720T Datasheet (ARM DDI 0087D) for detail.

2. Feature

• 32bit RISC architecture

• Low power consumption

• ARM7TDMI core with;

- On-chip ICEbreaker debug support

- 32bit x 8 hardware multiplier

- Thumb decompressor

• Utilizes the ARM7TDMI embedded processor

- High performance 32 bit RISC architecture

- High density 16 bit instruction set

• Fully static operation : 0 ~ 80MHz

• 3-stage pipeline architecture (Fetch, decode, and execution stage)

• Enhanced ARM software toolkit

• MMU, Write Buffer, 8KB I/D Cache

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GDC21D601

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

Virtual Address Bus

MMU

Data and

Address

Buffers

AMBA Interface

AMBA Bus

Interface

8KB Cache

Internal Data Bus

Control and

Clocking

Logic

ARM7TDMI

CPU

System Control

Coprocessor

Figure 1. ARM720T Block Diagram

JTAG Debug Interface

Coprocessor Interface

Page 25

3. Core Block Diagram

A [31:0]

ALE ABE

Address Register

P C b u

Incrementer

A L

U b

(31 x 32-bit registers)

(6 status registers)

Multiplier

b u s

Barrel Shifter

32-bit ALU

Write Data Register

nENOUT nENINDBE

32 x 8

Address

Instruction Pipeline

& Read Data Register

& Thumb Instruction Decoder

I n c r e

e n t e r

b u s

D [31:0]

Scan

Control

Instruction

Decoder

Control

Logic

DBGRQI BREAKPTI DBGACK ECLK nEXEC ISYNC BL [3:0] APE MCLK nWAIT

nIRQ nFIQ nRESET ABORT

SEQ LOCK nCPI CPA CPB nM [4:0] TBE TBIT HIGHZ

Core

ScanChain2

ICE

Breaker

Bus

Splitter

GDC21D601

RANGEOUT0 RANGEOUT1 ESTERN1 EXTERN0

nRW MAS [1:0] nTRANS nMREQ nOPC

A [0:31]

D [0:31] DIN [0:31] DOUT [0:31]

Scan

Chain 0

Scan

Chain 1

TAP Controller

TASPM [3:0]IR [3:0]SCREG [3:0]

Figure 2. ARM7TDMI Core Block Diagram

TCKTMSnTRSTTDITDO

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GDC21D601

Section 4. DRAM Controller

1. General Description

The DRAM controller interfaces the AMBA Advanced System Bus (ASB) to external DRAM memory banks. The DRAM controller provides the following features:

• Up to two banks of DRAM support.

• Fast page-mode sequential access support.

• EDO DRAM support

• Word, Half-word and Byte transaction support.

• Little / Big Endian Format support.

• DRAM refresh controller using CAS-before-RAS (CBR) refresh mode.

• Programmable refresh rate.

• Power-down mode where all DRAM accesses (including self-refresh) are disabled.

• Programmable DRAM timing control.

• Row/column addresses multiplexes according to DRAM capacity.

Chip PAD

nDRAMWE nDRAMOE nRAS[1:0]

nCAS[3:0]

nCASFB[3:0]

Aout[23:0]

DataOut[31:0]

DataIn[31:0] nOutEn[3:0]

DRAM Controller

Main State Machine

Address Generator

EBI Signal Control

nDRAMALatch

Control

Refresh

Timer & Controller

ASB Interface

nDRAMAMUX

nDRAMA[12:0]

nDRAMOutLEn

nDRAMInLEn[3:0]

nDRAMOutEn[3:0] Lat Lat

mux

Lat

nDRAMInEn

DRAMByte[1:0]

mux mux

ASB Bus

BCLK PDREQ

PDACK DSELDRAM DSELREG BnRES

BLAST BERROR BWAIT BWRITE

BSIZE[1:0] BA[29:0] BD[31:0]

BD[31:0]

Figure 1. DRAM Controller Module Block Diagram

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GDC21D601

2. Hardware Interface and Signal Description

The DRAM Controller module is connected to the ASB bus. Table 1. DRAM interface ASB signal descriptions shows the internal bus interface signals to the DRAM controller.

Table 1. DRAM Interface ASB Signal Descriptions

NAME DESCRIPTION

BA [27:0] System address bus (excluding high order bits). BCLK The ASB clock timing all bus transfers. BD [7:0] Bidirectional system data bus. BERROR Error slave response signal. It is driven to phase 1 if the DRAM controller is selected. This

signal will be asserted, when an access to the DRAM is attempted while the DRAM controller is in its Power Down mode.

BLAST Last transfer of burst slave response signal. It can be driven to phase 1 if the DRAM

controller is selected. It is asserted in order to indicate a 256-word boundary to force a non-

sequential access. BnRES These signals indicate the reset status of the ASB. BSIZE [1:0] These signals indicate the size of the transfer that may be byte, half-word, or word. BWAIT Wait slave response signal. It is driven to phase 1 when the DRAM controller is selected. It

is asserted while the DRAM transaction is uncompleted. BWRITE When this signal is HIGH, it indicates a write transfer and when LOW a read. DSELDRAM When this signal is HIGH, it indicates that the DRAM is selected. DSELREG When this signal is HIGH, it indicates that the DRAM configuration register is selected.

Table 2. DRAM interface External DRAM signal descriptions describes the DRAM controller connections to external devices of the system and to EBI (External Bus Interface) block .

Table 2. External DRAM Signal Descriptions

NAME DESCRIPTION

nRAS[1:0] Active LOW Row Address Strobes, one for each DRAM bank. NCAS[3:0] Active LOW Column Address Strobes, one for each byte. NDRAMOE Active LOW Output Enable. NDRAMWE Active LOW Write Enable. nCASFB[3:0] This is the nCAS[3:0] signal fed back from the output of the nCAS[3:0] pads. PDREQ Power Down Request. This signal indicates that the DRAM controller should enter into its

low-power state, causing the DRAMs to enter into self-refresh state if refresh is enabled.

When it is deasserted, the DRAM controller will exit from low power state. PDACK Power Down Acknowledge. This signal is asserted when the DRAM controller has

successfully entered into its low-power mode. At this point BCLK may be stopped safely. It

is deasserted when the DRAM controller has successfully exited from its low power state. DRAMAMUX DRAM Address Multiplex Select. When this signal is HIGH, it indicates to the EBI that the

DRAMA[12:0] address should be used to generate DRAMA[12:0]. This signal provides the

support for a shared EBI, and may not be needed in a system where the DRAM controller

does not share the EBI with other memory controllers. DRAMAMUX is LOW when

DRAM accesses are not performed.

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GDC21D601

NAME DESCRIPTION

NDRAMALatch DRAM Address Latch. When this signal is LOW, it opens the EBI address latch. This

signal is HIGH when DRAM operations do not occur. This signal provides support for a

shared EBI and may not be needed in a system where the DRAM controller does not share

the EBI with other memory controllers. DRAMA[12:0] These multiplexed address lines are connected to the DRAM Address. NDRAMInEn DRAM Input Enable. When this signal is LOW, it enables the EBI drivers from latched XD

to BD. This signal is HIGH when DRAM read operations are not performed. NDRAMInLEn[3:0] DRAM Input Latch Enable. When this signal is HIGH, it shuts the EBI latches on XD. This

signal is LOW when DRAM read operations are not performed. NDRAMOutEn DRAM Output Enable. When this signal is HIGH, it disables the EBI drivers from latched

BD to XD. This signal is low when DRAM write operations are not performed. NDRAMOutLen DRAM Output Latch Enable. When this signal is LOW, it opens the EBI latches on BD.

This signal is HIGH when DRAM write operations are not performed.

Accesses to the DRAM Controller module are generated as a result of the address decode put out on the ASB address bus by the current bus master (which could be the ARM CPU or the DMA engine, for example).

The following three diagrams show the timing of the external interface for read, write and refresh cycles (Figure 2, 3, 4).

BCLK

DRAMA[12:0]

nRAS[1:0]

nCAS[1:0]

XData[31:0]

nOE

nWE

row

Figure 2. DRAM External Signal Timing: Read Cycles

col row col1 col2

col3

Page 29

BCLK

GDC21D601

DRAMA[12:0]

nRAS[1:0]

nCAS[1:0]

XData[31:0]

nOE

nWE

BCLK

nRAS[1:0]

nCAS[1:0]

row

col row col1 col2

Data

Data1

col3

Data2 Data3

Figure 3. DRAM External Signal Timing: Write Cycles

nOE

nWE

Figure 4. DRAM Controller Refresh Cycle

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GDC21D601

3. Functional Description

3.1 Introduction

The DRAM controller provides connections allowing a direct interface to up to two banks of DRAM. Each bank is 32/16/8 bits wide and up to 256MB in size. Two RAS lines are provided (one per bank) and four CAS lines (one per byte line).

3.2 Functional BreakDown

The DRAM controller consists of four main blocks: the Main State Machine & Control Block, the EBI Signal Control Block, the ASB Interface & Address Generation Block, and the Refresh Timer & Counter Block.

3.3 Main State Machine

This block contains the main DRAM timing control state machine and the decode for the external strobe signals for the DRAM interface. The state machine generates the timing for the nCAS and nRAS strobes, and the multiplexing of the DRAM row and column address lines for standard DRAM cycles and refresh cycles. The nDRAMWE and nDRAMOE signals are asserted appropriately depending on the access type. Word, Half-word, and Byte accesses are decoded from the lower bits of the BA address bus in order to assert the appropriate nCAS line(s). For word accesses all four nCAS lines are asserted. Figure 5. Descibes the Main State Machine Diagram. Local arbitration for refresh cycles is also carried out here as refresh requests are received from the refresh timer block. The block also supports the self refresh DRAM; enter to and exit from this self refresh state are initiated by the PDRREQ signal. This is illustrated in Figure 6. DRAM signal timing: power down mode.

RefReq or !DSEL

r_IDLE

DSEL

r_RnR

CAS

r_RnC1

CAS

r_RnC2

r_RnC3

r_RnC4

!BWRITE

r_WAIT

RAS

r_CRWAIT

r_CWWAIT

BWRITE

r_WnR

r_WnC1

r_WnC2

r_WnC3

r_WnC4

Figure 5. Main State Machine Diagram

CAS

RefReq or !DSELD1

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GDC21D601

3.4 EBI Control Block

This also generates the control signals required by the EBI(External Bus Interface). The EBI control signals are divided into three main groups; those related to the control of the Address path, the DataIn path, and the DataOut path.

Address Path Control

There are three signazls related to the address path of the EBI: nDRAMALATCH used to open the address latch of the EBI. This can be used to hold the external address XA

while internal accesses are performed. When this signal is asserted (active LOW) the EBI address latch should be opened. When a DRAM access is not performed, the DRAM controller will de-assert this signal. In a shared EBI scheme, other memory controllers(Static Memory controller,...) must exhibit this behavior when they do not perform memory accesses.

DRAMAMUX used to select the DRAMA[12:0] address as the address to be used on XA. This signal will

be asserted (active HIGH) when a DRAM access occurs, and will be de-asserted when the transfer is completed.

DRAMA[12:0] the multiplexed row/column address used to access the DRAM.

DataIn and DataOut Path Control

There are four signals related to the data path of the EBI: nDRAMOUTEN used to enable the EBIs data drivers onto XData. When this signal is de-asserted (HIGH),

the EBI should disable its drive onto XData. This signal is de-asserted during read cycles and is asserted at other times. In a shared EBI scheme, other memory controllers must exhibit this behavior when they do not perform memory accesses.

nDRAMOUTLEN used to latch the value of BD into the EBIs data output latches. When this signal is asserted

(active LOW), the EBI data output latch is opened. This signal will be asserted during DRAM write transfers, and is de-asserted at other times.

nDRAMINEN used to enable the EBI data drivers onto BD. When this signal is asserted (active LOW), the

EBI should be driven onto BD. This signal is asserted during DRAM read transfers and is de-asserted at other times.

nDRAMINLEN[3:0] used to latch the value of XData into the EBI data input latches. When this signal is de-

asserted (HIGH), the EBI data input latch is shut. Four signals are provided to enable latching of byte / half-word data. nDRAMINLEN[0] is used to latch the data on M_D[7:0]. This signal is normally asserted and will be de-asserted during DRAM read transfers to latch the current data on XData.

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GDC21D601

3.5 Refresh Control Block

The refresh timer is a 7-bit timer counter which counts down and generates a refresh request when it reaches zero, at this point it is reloaded with the value in the refresh control register. This allows refresh frequencies from the Refresh Control Register and BCLK input clock.

3.6 ASB Interface Block

The ASB interface provides the interaction with the main AMBA bus. The DRAM controller will initiate a DRAM access when the DSELDRAM signal is asserted, or access the control registers when the DSELREG strobe is asserted. The timing of the ASB transfers is described in detail in the AMBA Specification rev. D. At a 256-word boundary, the BLAST signal will be asserted to indicate to the bus master that the burst sequence should be broken within the page boundary. This block also generates the row and column addresses. During burst mode accesses, the column address is provided by a 10-bit column address incrementor to provide adequate column address timing.

BCLK

PDREQ

PDACK

nRAS[1:0]

nCAS[3:0]

nOE

nWE

Figure 6. DRAM Signal Timing : Power Down Mode

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GDC21D601

4. Register Description

4.1 Memory Map

The base address (=DRAM REG Base) of the DRAM controller register bank is 0xFFFFED00.

Table 5. Memory Map of the Dram Controller Peripheral

ADDRESS WRITE LOCATION READ LOCATION INITIAL

Base + 0x0 DRAM Refresh Control Register (RCR) N/A 16’h0000 Base + 0x4 DRAM Control Register for CPU DRAM Control Register for CPU 7’ b0000000 Base + 0x8 DRAM Control Register for DMA DRAM Control Register for DMA 6’b000000 Base + 0xC DRAM Test Control Register (TCR) N/A 4’b0000

4.2 DRAM Refresh Control Register(RCR)

The DRAM refresh period register is an 16-bit write register which enables the refresh and selects the refresh period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the DRAM refresh period register is only cleared by a Power On Reset (BnRES = 0).

15 8 7 6 0

REFCNT

Figure 7. DRAM Controller Refresh Register

RFSHEN RFDIV

REFCNT DRAM Refresh Clock Divisor. Refresh Clock is setting by this bit field :

RefClock = BCLK/REFCNT

The REFCNT field should not be programmed with zero since this results in no initiated refresh cycles.

RFSHEN DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated by the DRAM

controller at the rate set by the RFDIV field. Setting this bit also enables self-refresh mode when the DRAM controller is in the power down state.

RFDIV This 7-bit field sets the DRAM refresh rate. The refresh period is deriven from internally generated

clock and is given by the following formula:

Frequency (KHz) = 2*[RefClock /(RFDIV + 1)]

RFDIV = ( RefClock / 0.5*Refresh frequency (KHz) ) - 1

The RFDIV field should not be programmed with zero since this results in no initiated refresh cycles.

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GDC21D601

4.3 DRAM Control Register for CPU (DRAMConCPU)

This Register controls the DRAM control signals when DRAM accessed by CPU. In normal condition, the DRAM access time is changed by the bus master is CPU or DMA Controller. In case of bus master is DMA Controller, the transfer timing should be properly set to the external I/O device and DRAM, so for the optimal system performance the DRAM access by the CPU is set in this DRAM Control Register for CPU (DRAMConCPU) and in case of the DRAM access by the DMA Controller DRAM control signals are controlled by the DRAM Control Register for DMA (DRAMConDMA).

15 7 6 5 4 3 2 1 0

Reserved DMAEn TRP TCP WaitCnt BankSize

Figure 8. DRAM Control Register for CPU (DRAMConCPU)

DMAEn If DMA transfer, then the DRAM control signals are controlled by DRAM Control Register for DMA

(DRAMDonDMA) by this bit setting. When this bit is ‘0’ , then the DRAM control signals are controlled by bit fields in this Control Register (DRAMConCPU) during DRAM access.

TRP Control the timing of difference between the RAS and CAS signal by this bit field setting. When this

bit is ‘0’ , then DRAM access are absolutely no wait, so DRAM access time is very short, but should be considered the operating frequency of the MCU and DRAM access time.

TCP Control the timing of the Low phase of CAS signals. When this bit is ‘1’ , then the Low phase of the

CAS signals are enlarged to one cycle of BCLK. When this bit is ‘0’ , then the Low phase of the CAS signals are half clock of BCLK.

WaitCnt This bit fields control the DRAM access time. The wait state is inserted in ASB BUS by the value of

these WaitCnt fields. (00=0-wait, 01=1-wait, 10=2-wait, 11=3-wait)

BankSize These bits indicate the data width of the DRAM Bank. The data width of the DRAM by BankSize are

shown Table 6.

Table 6. Data width of the DRAM by BankSize[1:0] fields

BankSize[1:0] Data Width of DRAM

00 Byte 01 Half Word 10 Word 11 Reserved

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GDC21D601

4.4 DRAM Control Register for DMA

This Register controls the DRAM control signals when DRAM accessed by DMA. Setting the register is effective only when the DMAEn bit set by DRAMConCPU(DRAM Control register from CPU).

15 6 5 4 3 2 1 0

Reserve TRP TCP WaitCnt BankSize

Figure 9. DRAM Control Register for DMA (DRAMConDMA)

4.5 DRAM Test Control(TCR)

The DRAM test control register is for test and should not be used during normal operation. It is a write-only register with the following format.

15 4 3 2 1 0

Reserved TESTINC FORCEADV FORCESIZE

Figure 10. DRAM Test Control Register

TESTINC Test increment (TESTINC). This bit puts the column address increment into a test mode. In

this mode each nibble of the column address increment increments independently. Resets it to

FORCEADV Force refresh advance (FORCEREFADV). This bit forces the refresh counter to advance every

BCLK. Resets it to 0.

FORCESIZE[1:0] Force access size. These bits force the size of accesses to the DRAM bank. When this is set to

10 (default), the ASB B_SIZE is used to determine the size of the access. When this is set to 00 or 01, a byte or half-word access is forced respectively. Resets it to 10.

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GDC21D601

Section 5. On-Chip SRAM

1. General Description

The GDC21D601 has 8-kbytes of on-chip RAM. The on-chip RAM is linked to the CPU and direct memory access controller(DMAC) with 32-bit data bus. The CPU and DMA Controller can write data into the on-chip RAM in byte, half-word, or word units.

2. Signal Description

Table 1. Signal Descriptions

NAME TYPE DESCRIPTION

BA[31:0] I System address bus. BD[31:0] I/O Bi-directional system data bus. BWAIT I/O LOW during phase one of BCLK. BLAST I/O LOW during phase one of BCLK. BERROR I/O LOW during phase one of BCLK. BWRITE I When this signal is HIGH, it indicates a write transfer and when LOW a read. DSELMEM I When this signal is HIGH, it indicates that on-chip RAM is selected. BnRES I These signals indicate the reset status of the ASB.

3. Function Description

On-Chip SRAM can read data from SRAM and can write data into SRAM in a single clock cycle through ASB bus. And SRAM is single module which have 32 bit data bus and control lines. The data in the On-chip RAM can always be accessed in one cycle that make the RAM ideal for use as a program area, stack area, or data area, which requires high-speed access. The contents of the on-chip RAM are held in both standby and power-down modes. Memory area 0x10000000 to 0x10001FFF is allocated to the on-chip RAM as default. When isram signal from MCU Controller is set to HIGH, memory area 0x00000000 to 0x00001FFF can be allocated to the on-chip RAM.

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GDC21D601

Section 6. Static Memory Controller

1. General Description

The Static Memory Controller interfaces the AMBA Advanced System Bus (ASB) to the External Bus Interface (EBI); controlling the external SRAM, ROM, Flash Memory or off-chip peripherals. Eight separate chip select banks are provided by this block. Each bank is 256MB in size and can be programmed individually to support:

• 8-, 16- or 32-bit wide, Little-Endian and Big-Endian Memory Format

• variable wait states (up to 16 waits)

• exchangeable active low/high chip select signal (only for CS6 and CS7)

• various type control signal timing

• bus transfers can be extended using the EXPRDY input signal. EXPRDY signal can be used by

exchangeablely active HIGH or LOW in according to control register setting.

Chip PAD

EXPRDY EXPCLK

MODE[1:0]

RnW nWEN[3:0] nSRAMOE nCS[5:0]

CS[7:6] nWEF[3:0]

Aout[23:0]

DataOut[31:0]

DataIn[31:0] nOutEn[3:0]

Static Memory Controller

Main State Machine

Bank Config. Reg.

ASB Interface

Chip Select encode

EBI Signal Control

MemByte[1:0]

nSRAMA[1:0]

nSRAMALatch

nSRAMAMUX

Lat Lat

mux

nSRAMInEn

nSRAMOutLEn

nSRAMInLEn[3:0]

nSRAMOutEn[3:0]

mux mux

Lat

BA[26:24, 4:0]

ASB Bus

BCLK BnRES DSELSMI DSELREG BTRAN[1:0]

BWRITE BSIZE[1:0]

BLAST BERROR BWAIT

BD[31:0]

Figure 1. Static Memory Controller Block Diagram

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GDC21D601

2. Signal Description

The Static Memory Controller module is connected to the ASB bus. In Table 1. Static Memory Controller ASB signal descriptions show the internal bus interface signals(AMBA signals) to the Static Memory Controller

Table 1. Static Memory Controller ASB Signal Descriptions

NAME TYPE DESCRIPTION

BA[26:24, 4:0] I System address bus. The SRAM controller only requires seven bits of this bus

to do the necessary encoding/decoding. BCLK I The ASB clock. BD[31:0] I/O Bi-directional system data bus. The data bus is driven by this block during read

transfers from configuration registers only. BERROR O LOW during phase one of BCLK when the Static Memory Controller is

selected. BLAST O LOW during phase one of BCLK when the Static Memory Controller is

selected. BWAIT O This slave response is driven during phase one of BCLK when the Static

Memory Controller is selected and is used to indicate if the memory has

completed its current transfer. BnRES I The reset status of the ASB. BSIZE[1:0] I The size of the transfer data which may be byte, half-word, or word. BTRAN[1:0] I These signals are used to determine sequential and non-sequential accesses. BWRITE I When this signal is HIGH, it indicates a write transfer and when LOW a read. DSELSRAM I When this signal is HIGH, it indicates that the Static Memory Controller is

selected. DSELREG I When HIGH, this signal indicates that one of the Bank Configuration registers

is selected.

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GDC21D601

Table 2. Static Memory Controller External Signal Descriptions

NAME TYPE DESCRIPTION

EXPRDY I Expansion channel ready. This signal is active LOW by default, When this

signal is LOW, it will force the current memory transfer to be extended. When

the RDON bit field in Configuration Register is set, then the polarity of the

EXPRDY signal is reversed to active HIGH. EXPCLK O Expansion clock output. Clock output at the same phase and speed as the bus

clock. Active only during SRAM/ROM cycles. nWEN[3:0] O These signals are active LOW write enables for each of the memory byte lanes

on the external bus. For example nWEN[0] controls the writes to D[7:0]. nWEF[3:0] I These optional connections use PADs feedback from the external side of the

nWEN[3:0] PADs. They are used to guarantee address and chip select hold

time when any write enable is LOW. If not used, they should be tied to HIGH. NSRAMOE O This is the active LOW output enable for devices on the external bus. This is

LOW during reads from external memory and during the time that the selected

bank should drive the external data bus. nCS[5:0] O Active LOW Chip Select CS[7:6] O Active HIGH Chip Select SRAMA [1:0] O These signals form the lower two bits of the external address bus. They are

used to control accesses to 16- or 8-bit memories when the AMBA bus

requests an access size larger than the memory (this is handled using multiple

external transfers). nSRAMALatch O This signal is an active LOW transparent address latch enable. It is normally

HIGH to prevent power wasting transitions on the external address bus. MemByteSeq[1:0] O These signals control the data path muxes which allow 16- or 8-bit memories to

read and write 32-bit values on the AMBA bus. nSRAMOutLEn O Active LOW transparent latch enable for the data out path (writes). nSRAMOutEn[1:0] O Active LOW byte lane data output driver enable. nSRAMInLEn[1:0] O Active LOW transparent latch enable for the data in path (reads). nSRAMInEn O Active LOW data input driver enable (to AMBA bus). Mode[1:0] I Booting mode configuration input. If these signals are “00” during BnRES

LOW then the SRAM Controller will select bank zero (nCS[0]) as 32-bit

memory. If these signals are “10” then select bank zero as 16-bit memory. If

these signals are “01” then bank zero as 8-bit memory.

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GDC21D601

Accesses to the Static Memory Controller module can be two basic types; control register accesses and memory area accesses. The following timing diagrams relate to the external pin timings for SRAM/ROM read and write cycles in minimum wait states.

BCLK

BTRAN[1:0]

BA[23:0]

DSELSRAM

BWAIT

BD[31:0]

EXPCLK

nCS[5:0]

nSRAMOE

A[23:0]

N_TRAN S_TRAN S_TRAN S_TRAN S_TRAN

address n

address n+4

address n+8

address n+4 address n+8

D[31:0]

EXPRDY

Deocde

Wait

Figure 2. ROM Read Timing

read

readread

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BCLK

GDC21D601

BTRAN[1:0]

BA[23:0]

DSELSRAM

BWAIT

BD[31:0]

EXPCLK

nWEN[3:0]

nCS[5:0]

XA[23:0]

N_TRAN S_TRAN S_TRAN S_TRAN

address n address n+4

address n

address n+4

XD[31:0]

EXPRDY

Deocde Wait

Figure 3. SRAM Write Timing

write data write data

write

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GDC21D601

3. Functional Description

The Static Memory Controller has following functions:

• memory bank select

• off-chip expansion clock driver

• wait states generation

• byte lane write control

• burst read access

• various type control signal generation

These are described below.

3.1 Memory Bank Select

The chip select signal generation is controlled by BA[26:24]. From Table 3 static memory bank select coding is shown that these signals coded to CS[7:6] and nCS[5:0].

Table 3. Static Memory Bank Select Coding (MODE R)

DSEL BA[26:24] CS[7:6] nCS[5:0] MEMORY CONFIGURATION

1 000 00 111110 nCS0 configuration 1 001 00 111101 nCS0 configuration 1 010 00 111011 nCS2 configuration 1 011 00 110111 nCS3 configuration 1 100 00 101111 nCS4 configuration 1 101 00 011111 nCS5 configuration 1 110 01 111111 CS6 configuration 1 111 10 111111 CS7 configuration

3.2 Off-Chip Expansion Clock Driver

In the Static Memory Controller, the system clock input BCLK is passed directly to EXPCLK during memory cycles if the expansion clock enable bit of the corresponding memory bank configuration is set.

3.3 Access Sequencing

Bank configuration also determines the width of the external memory devices. When the external memory bus is narrower than the transfer initiated from the current master, the internal transfer will take several external bus transfers to complete. For example, in case that bank zero is configured as 8-bit wide memory and a 32-bit read is initiated, the ASB bus will stall while the SRAM Controller reads four consecutive bytes from the memory. During these accesses the data path is controlled (using the MemByteSeq[1:0] signals) to de-multiplex these four bytes into one 32-bit word on the ASB bus.

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GDC21D601

3.4 Wait State Generation

The Static Memory Controller supports wait states for read and write accesses. This is configurable between one and 16 wait states for standard memory access and zero and 15 wait states for burst mode reads from ROMs.

Note

Wait state control refers to external transfer wait states. The number of cycles where an AMBA transfer completes is controlled by two other factors; access width and external memory width. The Static Memory Controller also allows transfers to be extended indefinitely, by asserting EXPRDY to LOW. To hold the current transfer EXPRDY must be asserted on the falling edge of BCLK before the last cycle of the access. The transfer cannot be completed until EXPRDY is HIGH for at least one cycle.

3.5 Burst Read Control

This supports sequential access burst reads of up to four consecutive locations in 8-, 16- or 32-bit memories. This feature supports burst mode ROM devices and increases the bandwidth by using a reduced (configurable) access time for three sequential reads following a quad-location boundary read. (Note that quad-location boundaries occur when A[1:0]=00 for byte wide memories.)

3.6 Byte Lane Write Control

This controls nWEN[1:0] according to AMBA transfer width (indicated by BSIZE[1:0]), external memory width, BA[1:0], and the access sequencing. The following table shows the basic coding assuming 32-bit external memory:

Table 4. nWEN Coding

BSIZE[1:0] BA[1:0] nWEN[3:0]

10 (word) XX 0000 01 (half-word) 1X 0011 01 (half-word) 0X 1100 00 (byte) 11 0111 00 (byte) 10 1011 00 (byte) 01 1101 00 (byte) 00 1110

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GDC21D601

4. Programmer’ s Model

4.1 Memory Map

The base address for the Static Memory Controller registers is 0xFFFFEC00

Table 5. Static Memory Controller Memory Map

ADDRESS DESCRIPTION INITIAL VALUE

SRAMRegBase + 00000 Memory Configuration Register 1 (MEMCFG1) 32’ h00000004 SRAMRegBase + 00004 Memory Configuration Register 2 (MEMCFG2) 32’ h00000000 SRAMRegBase + 00008 Memory Configuration Register 3 (MEMCFG3) 32’ h00000000

SRAMRegBase + 0000C Memory Configuration Register 4 (MEMCFG4) 32’ h00000000

4.2 Memory Configuration Registers

31 16 15 0

NCS[n+1] Configuration Register NCS[n] Configuration Register

Figure 4. Memory Configuration Register

Memory configuration register (MEMCFG1, 2, 3, 4) is a 32-bit read-write register which sets the configuration of the two expansion and ROM selects. Each select is configured with a two-byte field.

31 30 29 28 27 26 25 24 23 22 20 19 16

Reserved RDON CSCNTL FlashON CLKEN Mem Width BUREN Burst Wait Normal Wait

15 14 13 12 11 10 9 8 7 6 4 3 0

Reserved RDON CSCNTL FlashON CLKEN Mem Width BUREN Burst Wait Normal Wait

Figure 5. Two-Byte Fields in the Memory Configuration Register for CS[5:0]

(Note : Gray areas are reserved for another feature.)

15 14 13 12 11 10 9 8 7 6 4 3 0

Rsv. CSON RDON CSCNTL FlashON CLKEN Mem Width BUREN Burst Wait Normal Wait

Figure 6. Two-Byte Fields in the Memory Configuration Register for CS[6]

31 30 29 28 27 26 25 24 23 22 21 16

LCDON CSON RDON CSCNTL FlashON CLKEN Mem Width Reserved LCD Wait

Figure 7. Two-Byte Fields in the Memory Configuration Register for CS[7]

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GDC21D601

LCDON LCD enable. When the Bank 7 is connected to LCD panel for text display, setting this bit

enables LCD wait to access directly LCD device. LCD wait bit is 6 bits therefore wait cycle is from 1 to 64.

CSON nCS enable. Setting this bit is enables the CS6 and CS7 to be active low signal from active

high signal that supports various devices.

RDON select the polarity of EXPRDY. When this bit is set to 0, EXPRDY signal act as positive

active signal. When this bit is set to 1, EXPRDY signal act as negative active signal.

CSCNTL Make the control signals (Address, Data, CS, RnW, etc.) of external device to be similar

Motorolar type CPU.

FlashON Flash memory enable. When this bit is set to 1, memory control signals, nCS, nWEN[1:0],

and nSRAMOE, are adjusted to flash memory control signal timing.

CLKEN Expansion clock enable. Setting this bit enables the EXPCLK to be active during accesses to

the specified bank. This provides a timing reference for devices that need to extend bus cycles using the EXPRDY input. Back to back sequential accesses result in a continuous clock.

BUREN Burst enable. Setting this bit enables burst reads to take advantage of faster access time from

ROM devices that support burst mode.

Note

Banks using EXPCLK and EXPRDY for off-chip peripheral control should not enable burst mode, and should be designed and set up to use a specific number of wait states in each access. The peripheral should time the access by counting EXPCLK cycles (there is no explicit indication of access start or end) and determine the access direction and width by using nWEN[3:0].

Table 6. Values of the Mem Width Field Define the Bus Width Field.

Table 6. Values of the Mem Width Field

MEM WIDTH FIELD EXPANSION TRANSFER MODE

00 32-bit wide bus access 01 16-bit wide bus access 10 8-bit wide bus access 11 Reserved

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GDC21D601

Table 7. The values of the Normal Wait field define the values of the normal access wait state field. And the values of the LCD Wait define likely as Table 7.

Table 7. Values of the Normal Access Wait State Field.

VALUE NUMBER OF WAIT STATES

0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 15 1111 16

Table 8. Values of the Burst Wait field define the values of the burst read wait state field.

Table 8. Values of the Burst Read Wait State Field

VALUE NUMBER OF WAIT STATES

000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

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GDC21D601

Section 7. MCU Controller

1. General Description

Designing the Microcontroller unit (MCU), some control signals needed by any functional block, but not drive any other block, must be generated. So these control signals are generated in MCU Controller. The MCU Controller (MCUC) is composed of registers which are for selecting the function of multi-function pins, for defining the memory map structure, arbiter priority, MCU device code, and DRAM Power Down Req/Ack signals.

2. Signal Description

Table 1. Signal Descriptions

NAME TYPE DESCRIPTION

BCLK I System bus clock. BnRES I the reset status of the ASB BA[31:0] I System address bus BD[31:0] I/O Bi-directional system data bus. BWAIT O Low during phase one of BCLK BLAST O Low during phase one of BCLK BERROR O Low during phase one of BCLK BWRITE I When this signal is HIGH, it indicates a write transfer and when LOW a read. DSEL I When this signal is HIGH, it indicates that MCU Controller is selected. PwrDwnAck I This signal indicates that DRAM is entered into self-refresh mode PwrDwnReq O The request of entering the self-refresh node of DRAM Ari_pri O Determine Arbiter Priority. See Section.2 System Architecture for detail Isram O Allocate On-Chip SRAM address area at 0x00000000 Drambank0 O Allocate DRAM address area at 0x00000000 PINMUX_sigs O These signals are for Multi-function pin

Page 48

3. Register Description

3.1 Register Memory Map

The base address of MCU control Register is 0xFFFFEB00.

Table 2. MCU Controller Memory Map

GDC21D601

ADDRESS R/W

MCURegBase + 0x0000 R/W 0x00 MCU Control Register MCURegBase + 0x0004 R/W 0x00 PINMUX_PA Register, Multi-function pin MUX Control

MCURegBase + 0x0008 R/W 0x00 PINMUX_PB Register, Multi-function pin MUX Control

MCURegBase + 0x000C R/W 0x00 PINMUX_PC Register, Multi-function pin MUX Control

MCURegBase + 0x00010 R/W 0x00 PINMUX_PD Register, Multi-function pin MUX Control

MCURegBase + 0x00014 R/W 0x00 PINMUX_PE Register, Multi-function pin MUX Control

MCURegBase + 0x00018 R/W 0x00 PINMUX_PF Register, Multi-function pin MUX Control

MCURegBase +0x0001C R/W 0x00 PINMUX_PG Register, Multi-function pin MUX Control

MCURegBase + 0x00020 R/W 0x00 PINMUX_PH Register, Multi-function pin MUX Control

MCURegBase + 0x00024 R/W 0x00 PINMUX_PI Register, Multi-function pin MUX Control

MCURegBase + 0x00028 R/W 0x00 PINMUX_PJ Register, Multi-function pin MUX Control

MCURegBase +0x0002C R $LG601 MCU Device Code Register MCURegBase + 0x00030 R 0x0 DRAM Power Down Ack MCURegBase + 0x00034 W 0x0 DRAM Power Down Req

INITIAL VALUE

DESCRIPTION

signals for Port A[5:0]

signals for Port B[7:0]

signals for Port C[7:0]

signals for Port D[7:0]

signals for Port E[8:0]

signals for Port F[8:0]

signals for Port G[7:0]

signals for Port H[7:0]

signals for Port I[7:0]

signals for Port J[7:0]

3.2 MCUC_CON Register

31 2 1 0

Reserved Ari_Pri Isram Drambank0

drambank0 When this register is HIGH, DRAM memory address bank #0 area is located at 0. Isram When this register is HIGH, On-Chip SRAM address area is located at 0 Ari_pri Arbiter Priority control signal. See also Section 2 System Architecture for details.

Figure 1. MCU Controller Register

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3.3 PINMUX Register

GDC21D601

Table 3. PINMUX_PA Register

BIT NO. SIGNAL NAME

PINMUX_PA[0] IRQ0 PA0 45

PINMUX_PA[1] IRQ1 PA1 47

PINMUX_PA[2] IRQ2 PA2 48

PINMUX_PA[3] IRQ3 PA3 49

PINMUX_PA[4] IRQ4 PA4 51

PINMUX_PA[5] IRQ5 PA5 52

BIT NO. SIGNAL NAME

PINMUX_PB[0] TCIOA0 PB0 55

PINMUX_PB[1] TCIOB0 PB1 57

PINMUX_PB[2] TCIOA1 PB2 58

PINMUX_PB[3] TCIOB1 PB3 59

PINMUX_PB[4] TCIOA2 PB4 61

PINMUX_PB[5] TCIOB2 PB5 62

PINMUX_PB[6] TCIOA3 PB6 63

PINMUX_PB[7] TCIOB3 PB7 65

BIT NO. SIGNAL NAME

PINMUX_PC[0] PC0 TCIOA4 66

PINMUX_PC[1] PC1 TCIOB4 67

PINMUX_PC[2] PC2 TCIOA5 69

PINMUX_PC[3] PC3 TCIOB5 70

PINMUX_PC[4] PC4 TCLKA 71

PINMUX_PC[5] PC5 TCLKB 73

PINMUX_PC[6] PC6 TCLKC 74

PINMUX_PC[7] PC7 TCLKD 75

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Table 4. PINMUX_PB Register

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Table 5. PINMUX_PC Register

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Page 50

Table 6. PINMUX_PD Register

GDC21D601

BIT NO. SIGNAL NAME

PINMUX_PD[0] RXD0 PD0 76

PINMUX_PD[1] TXD0 PD1 78

PINMUX_PD[2] RXD1 PD2 79

PINMUX_PD[3] TXD1 PD3 80

PINMUX_PD[4] NCTS PD4 82

PINMUX_PD[5] NDSR PD5 83

PINMUX_PD[6] NDCD PD6 84

PINMUX_PD[7] NRI PD7 86

BIT NO. SIGNAL NAME

PINMUX_PE[0] NDTR PE0 87

PINMUX_PE[1] NRTS PE1 88

PINMUX_PE[2] SMDI PE2 90

PINMUX_PE[3] SMDO PE3 91

PINMUX_PE[4] SMCLK PE4 92

PINMUX_PE[5] SIN0 PE5 94

PINMUX_PE[6] SOUT0 PE6 95

PINMUX_PE[7] SCLK0 PE7 96

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Table 7. PINMUX_PE Register

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Table 8. PINMUX_PF Register

BIT NO. SIGNAL NAME

PINMUX_PF[0] SCS0 PF0 98

PINMUX_PF[1] SIN1 PF1 99

PINMUX_PF[2] SOUT1 PF2 100

PINMUX_PF[3] SCLK1 PF3 102

PINMUX_PF[4] SCS1 PF4 103

PINMUX_PF[5] BCLKOUT PF5 104

PINMUX_PF[6] NFIQOUT PF6 105

PINMUX_PF[7] NIRQOUT PF7 106

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Page 51

Table 9. PINMUX_PG Register

GDC21D601

BIT NO. SIGNAL NAME

PINMUX_PG[0] EXTREQ PG0 124

PINMUX_PG[1] EXTACK PG1 127

PINMUX_PG[2] DREQ0 PG2 128

PINMUX_PG[3] DACK0 PG3 129

PINMUX_PG[4] DREQ1 PG4 131

PINMUX_PG[5] DACK1 PG5 132

PINMUX_PG[6] RAS0 PG6 133

PINMUX_PG[7] RAS1 PG7 135

BIT NO. SIGNAL NAME

PINMUX_PH[0] CAS0 PH0 136

PINMUX_PH[1] CAS1 PH1 137

PINMUX_PH[2] CAS2 PH2 138

PINMUX_PH[3] CAS3 PH3 139

PINMUX_PH[4] CS4 PH4 161

PINMUX_PH[5] CS5 PH5 162

PINMUX_PH[6] CS6 PH6 165

PINMUX_PH[7] CS7 PH7 166

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Table 10. PINMUX_PH Register

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

Table 11. PINMUX_PI Register

BIT NO. SIGNAL NAME

PINMUX_PI[0] D16 PI0 187

PINMUX_PI[1] D17 PI1 186

PINMUX_PI[2] D18 PI2 184

PINMUX_PI[3] D19 PI3 183

PINMUX_PI[4] D20 PI4 182

PINMUX_PI[5] D21 PI5 180

PINMUX_PI[6] D22 PI6 179

PINMUX_PI[7] D23 PI7 178

PIN FUNCTION DESCRIPTION

When 0 When 1 PIN No.

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Table 12. PINMUX_PJ Register

GDC21D601

BIT NO. SIGNAL NAME

PINMUX_PJ[0] D24 PJ0 177

PINMUX_PJ[1] D25 PJ1 175

PINMUX_PJ[2] D26 PJ2 174

PINMUX_PJ[3] D27 PJ3 173

PINMUX_PJ[4] D28 PJ4 171

PINMUX_PJ[5] D29 PJ5 170

PINMUX_PJ[6] D30 PJ6 169

PINMUX_PJ[7] D31 PJ7 167

When 0 When 1 PIN No.

3.5 MCU Device Code Register

This Register is read only. Device Code Value is ‘$LG601’ Binary Value : 0000 0100 1100 0100 0111 0110 0000 0001

3.6 DRAM Power Down Acknowledge Register

This Register is 1 bit read only register. This register is set when DRAM is entered to power down mode.

3.7 DRAM Power Down Request Register

PIN FUNCTION DESCRIPTION

This Register is 1 bit read/write register. When this register bit is HIGH, request to DRAM Controller to enter into power down mode of the DRAM.

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Section 8. Power Management Unit

1. General Description

The PMU block provides:

• Clock distribution of all over system

• Reset, RUN and Power down modes control

Figure 1. shows the PMU Block Diagram.

GDC21D601

nPOR

WD_OF_IN

MAN_RESET_IN

P_A[7:0] P_D[15:0] P_SEL P_STB

P_WRITE

INT_REQ_IN

tfclk tbclk

SCLK_IN

PCLK_IN

SPCLK

Reset

Debounce

Digital Filter

PMU

Registers

BCLK

Freq.

Control

PCLK

Freq.

Control

Figure 1. PMU Block Diagram

Reset

Control

PMU

Control

FCLK, BCLK

Distribution

Control

PCLK

Distribution

Control

B_RESETn_OUT P_RESETn0_OUT P_RESETn1_OUT

RESETn_EXT WD_OF_OUT

nPDM FASTBUS REMAP

FCLK BCLK_XXX for ASB block

BCLK_XXX for Peripherals

PCLK_XXXX for Peripherals

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GDC21D601

2. Hardware Interface and Signal Description

The PMU block is connected to the APB bus. Table 1. describes the APB signals and clock signals used and produced.

Table 1. PMU Signal Descriptions

NAME TYPE DESCRIPTION

nPOR I External reset input. INT_REQ_IN I Interrupt request signal from the interrupt controller. WD_OF_IN I Watch dog timer overflow signal. MAN_RST_IN I S/W manual reset pin from watch dog timer.

P_D[15:0] I/O

P_A[7:0] I

P_WRITE I

P_STB I

P_SEL I SCLK_IN I System clock input . This is the clock input from external clock circuit .

PCLK_IN I UART clock. This is the clock input from external UART clock module. Tfclk I

Tbclk I

BCLK_XXX O PCLK_XXX O APB Peripheral Bus Clocks. All APB blocks are operated by the clocks.

FCLK O FCLK pin for ARM720T. It is used in standard mode, when FASTBUS is LOW. FASTBUS O

NPDM O REMAP O Indicates that the reset memory map is in operation.

WD_OF_OUT O Watch dog overflow output signal for external devices. B_RESETn O Reset signal for ASB devices P_RESETn0 O Reset signal for APB devices P_RESETn1 O Same as P_RESETn0, but in manual reset mode this is not asserted. RESETn_OUT O Reset signal for external devices.

This is the bi-directional peripheral data bus. This block drives the data bus during read cycle, when P_WRITE is LOW. This is the peripheral address bus, which uses individual peripheral for decoding register accesses to that peripheral. The addresses become valid before PSTB goes to HIGH and remain valid after PSTB goes to LOW. This signal indicates a write to a peripheral when it is HIGH and a read from a peripheral when LOW. It has the same timing as the peripheral address bus. This strobe signal is used to time all accesses on the peripheral bus. The falling edge of PSTB is coincident with the falling edge of BCLK When HIGH, this signal indicates that module has been selected by the APB bridge.

When it is in TIC test mode, this s the FCLK clock input signal. When TSTCR[1] is set to 1(HIGH) for entering TIC test mode. When it is in TIC test mode, BCLK clocks signal. First set the TSTCR[1] to 1 for entering TIC test mode. System Bus clock is generated from SCLK_IN. All ASB block and some APB blocks are operated by this clock.

ARM720T bus mode control signal. When it is LOW, it is in standard bus mode. When HIGH, fast bus mode. Indicates the PDM mode of PMU. When it is LOW, MCU entered in power down mode. When HIGH, normal operation mode.

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3. Operation Modes

3.1 Introduction

GDC21D601

The reset protocol guarantees that the multi-master system starts up with at most one bus driver enabled on each shared signal on the bus, and also permits a protocol reset mechanism for time-out or ‘watchdog’ reset support.

To improve power management, support for a power-saving mode where bus clocks may be disabled (or dropped to lower clock) is included.

3.2 Reset and Operation Modes

A set of four useful states or modes is defined as follows:

RESET

When it is power-on, watchdog timer overflow, watchdog timer manual reset or S/W reset, the MCU is initialized

Rower on Reset

The most severe form of reset which ensures that no more than one tri-state driver is enabled on each bus and initializes all system states to ensure that the power supply can in fact rise to normal operating voltage.

The reset and power-down mechanism provides:

• Stable power-up sequence

• Hard Initialization (Power On Reset)

• Soft Initialization (S/W Manual Restart)

Additionally a system bus, once operational, benefits from well-defined modes of operation:

• RUN in the Standard BUS mode

• RUN in the FAST BUS mode

• Power-down mode

Manual Reset / Software Reset

The manual reset, which may need to apply to allow all soft resetting of the bus for a number of clock cycles. In this reset states the PMU block initializes all the ASB blocks, Bus controller, DRAM Controller, DMA Controller, ARM CPU core, and Arbiter, Decode. However some APB blocks are all valid in warm reset.

Watchdog Timer Overflow and Manual Reset

The watchdog timer can generate reset signal, when timer overflows or sets the register value. Detailed information are in the watchdog timer manual, please refer to it.

This state should be forced by any on-chip poweron-reset cell or external power-on signal and maintained until bus clock is safe and stable.

The POR is forced to be in an asynchronous start-up condition and must be recognized by all master and

slave devices to disable output drives (and wait for a valid clock)

RUN - ARM720T Standard Mode.

The ARM720T works using the FCLK and BCLK. The FCLK is used for CPU operation clock, and the B_CLK is used for internal bus access, i.e. AMBA BUS. So CPU can operate very high frequency. This mode can control the clock of ASB and APB devices, so user can disable the clocks of unused devices or peripherals. It is possible to control the BCLK or PCLK mask register.

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GDC21D601

RUN -ARM720T Fast-bus Extension Mode.

The ARM720T works using only the BCLK. The CPU operation clock and AMBA bus access clock are the same. This mode can control the clock of ASB and APB devices, so user can disable the clock of devices or peripherals that are not using now. It is possible to control the BCLK mask register or PCLK mask register.

PDN – Power-Down Mode

When MCU system is in the PDN State, PMU block

S/W Control Man_reset

disables all of the blocks in the ASB and APB, so the power consumption of system is dramatically low. Although MCU is in the power down mode, user can set some blocks are working in the power down mode. It is possible control the BCLK or PCLK mask register for power-down.

Wake-up from the PDN Mode.

The Wake-up is a temporal state for wake-up from power down state through the interruption. After wake-up state, next state becomes RUN state automatically.

nPORWD_OF

RESET

Wake-up by nPOR

RUN

(use FCLK)

S/W Control

S/W Control Man_reset

S/W Control

RUN

(use B_CLK only)

Figure 2. Reset and Power Management State Machine.

Power Down

S/W Control

Wake-up by Interrupt

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GDC21D601

4. Register Description

The PMU supplies the clock to all of the blocks in the MCU.

4.1 PMU Control Register

This register controls the operation mode of PMU. When power on reset states, register value is initialized by Run State (00). The address of register is PMU_BASE(=0xFFFF F000) + 0x00h.

Table 2. PMUCR Bit Functions

BIT INITIAL NAME FUNCTION

7~0 0x0 PMUCR 0x0 - Clear PMU Status Register.

0x03 – Entering the PD(Power down) Mode the other values - None effect.

4.2 PMU Status Register

This register holds the previous status and reset state of PMU. The address of register is PMU_BASE + 0x00h.

Table 3. PMUSR Bit Functions

BIT INITIAL NAME FUNCTION

5, 4 00 PMUST[5:4]

Previous Reset Status bits

3, 2 00 PMUST[3:2]

Current Status bits

1, 0 00 PMUST[1:0]

Previous Status bits

00 - The Power-On reset state (nPOR). 01 - S/W Reset state using PMU. 10 - S/W Manual reset state using WDT. 11 - WD overflow reset state using WDT. 00 - Running (FAST, SLOW) after nPOR. 01 - Running (FAST, SLOW) after WD_OF. 10 - Running (FAST, SLOW) after Man_reset 00 - Start (FAST, SLOW) after nPOR. 01 - Start (FAST, SLOW) after WD_OF. 10 - Start (FAST, SLOW) after Man_reset 11 - Start (FAST, SLOW) after PD Mode.

4.3 REMAP Register

The REMAP register controls re-mapping operation when the reset (POR or MAN_RST) signal is asserted or S/W is reset by RSTCR. The address is PMU_BASE + 0x10h.

Table 4. REMAP Bit Functions

BIT INITIAL NAME FUNCTION

0 0 REMAP 0 – Reset operation mode map

1 – Normal operation mode map

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GDC21D601

4.4 BCLK and FCLK Control Register and BCLK Frequency Control Register

This register controls BCLK of ASB and FCLK of ARM720T. User can save the power by reduce of the clock speed. At any moment, user can change the BCLK speed but it may push the system into unstable stage, so user must change the clock speed only in BUS IDLE; this means there is no interaction between the devices used by BCLK and any other devices used by PCLK. User can control the bus mode that are standard-bus mode and fastbus mode. The BCLK is only used in the fast-bus mode and ARM720T uses the both clock FCLK and BCLK in the fast bus mode. The address is PMU_BASE + 0x04h.

Table 5. CLKCR Bit Functions

BIT INITIAL NAME FUNCTION

2 - 0 000 BCLKCR[2:0] Control register for BCLK selection

000 - BCLK is divided SYS_CLK by 2 001 - BCLK is divided SYS_CLK by 4 010 - BCLK is divided SYS_CLK by 8 011 - BCLK is divided SYS_CLK by 16 100 - BCLK is divided SYS_CLK by 32 101 - BCLK is divided SYS_CLK by 64 110 - BCLK is divided SYS_CLK by 128 111 - BCLK is SYS_CLK.

Table 6. CLKCR Bit Functions

BIT INITIAL NAME FUNCTION

3 1 BCLKCR[3] Control register to use in FCLK mode

1 – Fast-bus mode (not use the FCLK) 0 – Standard-bus mode use the FCLK that same the SYS_CLK

4.5 BCLK Mask Register for the RUN & PD Mode.

This register is used for masking BCLK of ASB devices in the RUN and PD mode. When each control bits are written to “1 or 0”, each clock of devices is controlled by enabled or disabled clock in the RUN and PD mode. The address of the mask control register are as follows.; BCLKMSK_RUN is PMU_BASE + 0x08h, BCLKMSK_PD is PMU_BASE + 0x0Ch. When this is 1, it is enable clock. When 0, disable clock.

Table 7. BCLKMSK Bit Functions for RUN Mode

BIT INITIAL NAME FUNCTION

15-13 1 BCLKMSK_RUN Reserved bit

12 1 APB Bridge clock mask bit 11 1 BUS Controller clock mask bit 10 1 DRAM Controller clock mask bit

9 1 DMA Controller clock mask bit 8 1 TEST Controller clock mask bit 7 1 SRAM clock mask bit

6 - 1 111111 Reserved bit

0 1 B_CLK Out mask bit

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GDC21D601

Table 8. BCLKMSK Bit Functions for PD Mode

BIT INITIAL NAME FUNCTION

15 0 BCLKMSK_PD ARM7TDMI core clock mask bit 14 0 AMBA Arbiter clock mask bit 13 0 AMBA Decoder clock mask bit 12 0 APB Bridge clock mask bit 11 0 BUS Controller clock mask bit 10 0 DRAM Controller clock mask bit

9 0 DMA Controller clock mask bit 8 0 TEST Controller clock mask bit 7 0 SRAM clock mask bit

6 - 1 000000 Reserved bit

0 0 B_CLK Out mask bit

4.6 PCLK Mask Register

These registers are used for masking PCLK or BCLK of APB devices in the RUN or PD mode. The default values are all the clocks of the APB devices enabled in the RUN mode, and the clocks of the APB devices disabled in the PD mode. WDT and TIMER are APB devices but they uses the BCLK for their operation. The address of the mask control register in RUN mode is PMU_BASE + 0x18h, and that of the power-down mask control register is PMU_BASE + 0x1Ch. When this is 1, it enables clock. When 0, disables clock.

Table 9. PCLKMSK Bit Functions in the RUN Mode

BIT INITIAL NAME FUNCTION

9 1 PCLKMSK_RUN Watch dog timer clock mask bit 8 1 I2 C 2 clock mask bit 7 1 I2 C 1 clock mask bit 6 1 I2 C 0 clock mask bit 5 1 SSPI 1 clock mask bit 4 1 SSPI 0 clock mask bit 3 1 UART 2 / SMART card I/F clock mask bit 2 1 UART 1 clock mask bit 1 1 UART 0 clock mask bit 0 1 Timer clock mask bit

Table 10. PCLKMSK Bit Functions in the PD Mode

BIT INITIAL NAME FUNCTION

9 0 PCLKMSK_PD Watch dog timer clock mask bit 8 0 I2 C 2 clock mask bit 7 0 I2 C 1 clock mask bit 6 0 I2 C 0 clock mask bit 5 0 SSPI 1 clock mask bit 4 0 SSPI 0 clock mask bit 3 0 UART 2 / SMART card I/F clock mask bit 2 0 UART 1 clock mask bit 1 0 UART 0 clock mask bit 0 0 Timer clock mask bit

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GDC21D601

4.7 PCLK Frequency Control Register

This register is used to selecting the frequency of PCLK in the APB at RUN mode. Default value is 0000. The address of access the register is PMU_BASE + 0x14h

Table 11. CLKMODE Bit Functions

BIT INITIAL NAME FUNCTION

2 - 0 000 PCLKCR Select the PCLK source

000 – PCLK is external PCLK source 001 – PCLK is the SCLK divided by 2 010 – PCLK is the SCLK divided by 4 011 – PCLK is the SCLK divided by 8 100 – PCLK is the SCLK divided by 16 101 – PCLK is the SCLK divided by 32 110 – PCLK is the SCLK divided by 64 111 – PCLK is the SCLK divided by 128

4.8 Reset Control Register

This register is used for generating the S/W reset operation. The MCU is entered in reset state, when this register is set to high, it is cleared automatically at the end of manual reset procedure. The address is PMU_BASE + 0x30h.

Table 12. RSTCR Bit Functions

BIT INITIAL NAME FUNCTION

0 0 RSTCR Manual reset control bits

0 - Normal , 1 - manual reset

4.9 Test Control Register

TSTCR controls the normal mode, PMU test mode or the TIC test mode. The address is PMU_BASE + 0x40h.

Table 13. TSTCR Bit Functions

BIT INITIAL NAME FUNCTION

1 0 TSTCR 0 – Normal operation mode

1 – TIC Test mode

0 0 0 – Normal operation mode

1 – PMU test mode

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GDC21D601

4.10 Test Register

This register is used to store some controls and data values for test mode. The TSTR0 is readable/writable register and the TSTR1 is a read only register. The address of TSTR0 is PMU_BASE + 0x48h and that of TSTR1 is PMU_BASE + 0x4Ch.

Table 14. TSTR0 Bit Functions

BIT INITIAL NAME FUNCTION

2 0 TSTR0 Test bit for INT_REQ_IN input 1 0 Test bit for WD_OF_IN input 0 0 Test bit for MAN_RESET_IN input

Table 15. TSTR1 Bit Functions

BIT INITIAL NAME FUNCTION

15 0 TSTR1 Test bit for BCLK_WDT 14 0 Test bit for PCLK_I2C2 13 0 Test bit for PCLK_I2C1 12 0 Test bit for PCLK_I2C0 11 0 Test bit for PCLK_SSPI 1 10 0 Test bit for PCLK_SSPI 0 9 0 Test bit for PCLK_UART 2, SMART Card 8 0 Test bit for PCLK_UART 1 7 0 Test bit for PCLK_UART 0 6 0 Test bit for BCLK_TIMER 5 0 Test bit for B_RESETn 4 0 Test bit for P_RESETn0 3 0 Test bit for P_RESETn1 2 0 Test bit for P_RESETn 1 0 Test bit for WD_OF_OUT 0 0 Test bit for REMAP

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GDC21D601

5. Power Management Unit Register Map

The base address of the PMU(Power Management Unit) is 0xFFFF F000. May be different for any particular system implementation. However, the offset address of registers is fixed.

Table 16. Register Map of the PMU

Address Name Description

PMU Base + 0x00 PMUCR / PMUSR In write operation, PMU operation mode controls register. In read

operation, PMU status register shows the just previous PMU state.

PMU Base + 0x04 BCLKCR BCLK frequency selection and BUS mode control(Standard / Fast

BUS mode) PMU Base + 0x08 BCLKMSK_RUN BCLK Masking controls register in the RUN mode. PMU Base + 0x0C BCLKMSK_PD BCLK Masking controls register in the PD mode. PMU Base + 0x10 REMAP REMAP register PMU Base + 0x14 PCLKCR PCLK control register PMU Base + 0x18 PCLKMSK_RUN PCLK masking controls register for the RUN mode. PMU Base + 0x1C PCLKMSK_PD PCLK masking controls register for the PD mode. PMU Base + 0x20 Reserved Reserved. PMU Base + 0x30 RSTCR Reset control register PMU Base + 0x40 TSTCR TIC test mode and PMU test control register PMU Base + 0x44 - Reserved PMU Base + 0x48 TSTR0 Test write register for external input signals PMU Base + 0x4C TSTR1 Test read register for clocks of ASB devices and reset signals

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GDC21D601

6. Test Mode Guide for MCU

6.1 TIC Test Mode

Step 1. Set-up TIC test environment, connect the TCLK to tbclk(=XPA[6]) pin and FCLK of fclkgen to

tfclk (=XPA[7]) pin. Until the mode of the PMU is changed to the TIC test mode, sys_clk has to feed same TCLK to the clock.

Step 2. Reset the MCU using pin nPOR low. Step 3. Then TIC becomes the bus master Step 4. Change the mode of PMU by setting the TSTCR to “10” and set TSTCR[1] to high. Step 5. Start TIC test using tbclk and tfclk pins.

Figure 3. shows TIC Test Environment of Internal Blocks.

TREQA

APB

TIC

TREQB TACK

TIC BOX

ASB

BCLK

ARM720T

FCLK

EBI

SYS_CLK

PCLK BCLK

SCLK_IN PCLK_IN tbclk

PMU

tfclk nPOR

Figure 3. Internal Blocks TIC Test Environment

FCLK

TBUS TCLK

FCLKGEN

Reset GEN

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GDC21D601

6.2. TIC Test for PMU Block

Step 1. Set-up TIC test environment, connect the TCLK to tbclk and FCLK of fclkgen to tfclk pin. Until the

mode of the PMU is changed to the TIC test mode, sys_clk has to feed the clock. It is easier to test the

sys_clk and the tbclk separately. Step 2. Reset the MCU using pin nPOR low. Step 3. Then TIC becomes the bus master Step 4. Change the mode of PMU by setting the TSTCR[1:0] to “11”. Step 5. Set value to TSTR0 for test vector, and read output value in the TSTR1 of the PMU and compare it with

desired test vector.

Figure 4. shows PMU TIC Test Environment

TREQA

APB

TIC

TREQB TACK

TIC BOX

ASB

BCLK

ARM720T

FCLK

EBI

SYS_CLK

PCLK BCLK

SCLK_IN PCLK_IN tbclk

PMU

tfclk nPOR

Figure 4. TIC Test Environment

FCLK

TBUS TCLK

TESTCLK

GEN

FCLKGEN

Reset GEN

Page 65

7. Signal Timing Diagram

The PMU signal timing is as shown below.

7.1 Power on Reset

S_CLK

RESETn_IN

B_RESETn

P_RESETn0/1

RESETn_OUT

Figure 5. Power on Reset Timing Diagram

7.2 Watch Dog Timer Overflow

GDC21D601

B_CLK

WD_OF_IN

WD_OF_OUT

B_RESETn

P_RESETn0/1

256 B_CLK

512 B_CLK

Figure 6. Watch Dog Timer Overflow Timing Diagram

7.3 Manual Reset

There are two manual reset cases. The first reset operation is switched by MAN_RST signal from WDT. Another case is called S/W reset.

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B_CLK

MAN_RST

GDC21D601

B_RESETn

512 B_CLK

P_RESETn0 P_RESETn1

High

Figure 7. Manual Reset (from WDT) Timing Diagram

B_CLK

RSTCR

B_RESETn

512 B_CLK

P_RESETn0 P_RESETn1

High

Figure 8. S/W Reset Timing Diagram

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Section 9. Watchdog Timer

TCNT : Timer Counter (8bit)

TRCR : Timer/Reset Control Register (8bit)

System clock

Module data bus

RSTSR

Clock

Generation

Clock

Selection

Internal

data bus

TCNT

TRCR

Overflow

Reset

Control

Interrupt

Control

logic

clock

MNRST

Bus Interface

1. General Description

The watchdog timer has:

• watchdog timer mode and interval timer mode

• interrupt signal INT_WDT to interrupt controller in the watchdog timer mode & interval timer mode

• output signal PORESET and MNRESET to PMU(Power Management Unit)

• eight counter clock sources

• selection whether to reset the chip internally or not

• two types of reset signal : power-on reset and manual reset

INT_WDT

GDC21D601

PORST

RSTSR : Reset Status Register (2bit)

Figure 1. Watchdog Timer Module Block Diagram

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2. Hardware Interface and Signal Description

The Watchdog Timer module is connected to the APB bus.

Table 1. APB Signal Descriptions

GDC21D601

NAME Type

B_CLK I Clock controller System (bus) clock. This clock times all bus transfers. The clock has

P_A[4:2] I APB Bridge This is the peripheral address bus used by an individual peripheral for

P_D[7:0] I/O APB Peripherals,

P_STB I APB Bridge This strobe signal is used to time all accesses on the peripheral bus.

P_WRITE I APB Bridge When this signal is HIGH, it indicates a write to a peripheral. When

P_SEL I APB Bridge When this signal is HIGH, it indicates that this module has been

nB_RES I Power

INT_WDT O Interrupt

MNRST O Power

PORST O Power

SOURCE/

DESTINATION

B_D bus

Management Unit

Controller

Management Unit

DESCRIPTION

two distinct phases - phase 1 when B_CLK is LOW, and phase 2 when B_CLK is HIGH.

decoding register accesses to that peripheral. The addresses become valid before P_STB goes to HIGH and remain valid after P_STB goes to LOW. This is the bi-directional peripheral data bus. The data bus is driven by this block during read cycles (when P_WRITE is LOW).

The falling edge of P_STB is coincident with the falling edge of B_CLK.

LOW, it indicates a read from a peripheral. This signal has the same timing as the peripheral address bus. It becomes valid before P_STB goes to HIGH and remains valid after P_STB goes to LOW.

selected by the APB bridge. This selection is a decode of the system address bus (ASB). See AMBA Peripheral Bus Controller for more details. Reset signal generated from the APB Bridge

When this signal is HIGH, it indicates that a system becomes uncontrolled, and the timer counter overflows without being rewritten correctly by the CPU or it overflows in the interval timer mode. When this signal is HIGH, this signal indicates that the manual reset signal has selected as the internal reset signal, and the timer counter overflows without being rewritten correctly by the CPU or it overflows in the interval timer mode.. When this signal is HIGH, this signal indicates that the power-on reset signal has selected as the internal reset signal.

Writes to the Watchdog Timer module are generated from the Peripheral Bus Controller module. Figure 2. Watchdog timer module APB write cycle summarizes this description.

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B_CLK

P_SEL

P_WRITE

P_STB

GDC21D601

P_D

P_A

B_CLK

P_SEL

P_WRITE

P_STB

P_D

P_A

Data

Address

Data

Figure 2. Watchdog Timer Module APB Write Cycle

Data

Address

Data

Figure 3. Watchdog Timer Module APB Read Cycle

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GDC21D601

3. Watchdog Timer Introduction

The GDC21D601 has a one-channel watchdog timer(WDT) for monitoring system operations. If a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the CPU, an reset signal is output to PMU.

When this watchdog function is not needed, the WDT can be used as an interval timer. In the interval timer operation, an interval timer interrupt is generated at each counter overflow.

The WDT has a clock generator which products eight counter clock sources. The clock signals are obtained by dividing the frequency of the system clock(B_CLK). Users can select one of eight internal clock sources for input to the TCNT by CKS2 - CKS0 in the TRCR.

Table 2. Internal Counter Clock Sources

BIT 2 - 0

(CKS2-CKS0)

000 The system clock is divided by 2 12.8 us 001 The system clock is divided by 8 51.2 us 010 The system clock is divided by 32 204.8 us 011 The system clock is divided by 64 409.6 us 100 The system clock is divided by 256 1.64 ms 101 The system clock is divided by 512 3.28 ms 110 The system clock is divided by 2048 13.11 ms 111 The system clock is divided by 8192 52.43 ms

CLOCK SOURCE

(SYSTEM CLOCK = 40 MHz)

OVERFLOW INTERVAL

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GDC21D601

4. Watchdog Timer Operation

The Watchdog Timer Mode

To use the WDT as a watchdog timer, set the WT/nIT and TMEN bits of the TRCR to 1. Software must prevent TCNT overflow by rewriting the TCNT value(normally by writing 0x00) before overflow occurs. If the TCNT fails to be rewritten and overflow due to a system crash or the like, INT_WDT signal and PORESET/MNRESET signal are output. The INT_WDT signal is not output if INTEN is disabled (INTEN = 0).

TCNT value

OxFF

WT/nIT = 1

Ox00

TMEN = 1

0x00 written in TCNT

WTOVF = 1

FAULT and internal reset generated

time

Figure 4. Operation in the Watchdog Timer Mode

If the RSTEN bit in the TRCR is set to 1, a signal to reset the chip will be generated internally when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTSEL bit.

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GDC21D601

The Interval Timer Mode

To use the WDT as an interval timer, clear WT/nIT to 0 and set TMEN to 1. A watchdog timer interrupt (INT_WDT) is generated each time the timer counter overflows. This function can be used to generate interval timer interrupts at regular intervals.

TCNT value

OxFF

WT/nIT = 0

Ox00

TMEN = 1

ITOVF = 1

WDTINT generated

Figure 5. Operation in the Interval Timer Mode

time

4.1 Timing of Setting and Clearing the Overflow Flag

Timing of setting the overflow flag

In the interval timer mode when the TCNT overflows, the ITOVF flag is set to 1 and an watchdog timer interrupt (INT_WDT) is requested.

In the watchdog timer mode when the TCNT overflows, the WTOVF bit of the SR is set to 1 and a WDTOUT signal is output. When RSTEN bit is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip.

Timing of clearing the overflow flag

When the Reset Status Register (RSTSR) is read, the overflow flag is cleared.

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GDC21D601

5. Watchdog Timer Memory Map

The WDT has five registers. They are used to select the internal clock source, switch to the WDT mode, control the reset signal, and test it. The base address of the watchdog timer is fixed to 0xFFFF F100 and the offset of any particular register from the base address is fixed.

Table 3. Memory Map of the Watchdog Timer APB Peripheral

ADDRESS READ LOCATION WRITE LOCATION

WdtBase + 0x00 Timer/Reset Control Timer/Reset Control WdtBase + 0x04 Reset Status WdtBase + 0x08 Timer Counter Timer Counter WdtBase + 0x10 Test Input WdtBase + 0x14 Test Output

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6. Watchdog Timer Register Descriptions

The following registers are provided for watchdog timer:

Timer Counter (TCNT)

8-bit readable and writable upcounter. When the timer is enabled, the timer counter starts counting pulse of the selected clock source. When the value of the TCNT changes from 0xFF-0x00(overflows), a watchdog timer overflow signal is generated in the both timer modes. The TCNT is initialized to 0x00 by a power-reset(nB_RES).

Timer/Reset Control Register (TRCR)

8-bit readable and writable register. The following functions are provided : Selecting the timer mode Selecting the internal clock source Selecting the reset mode Setting the timer enable bit Being enable interrupt request Being enable reset signal occurrence

The clock signals are obtained by dividing the frequency of the system clock.

Table 4. TRCR Bit Description

BIT

0 (clock select : CKS0) 0 000 = /2 select one of eight internal clock

1 (clock select : CKS1) 0 001 = /8 2 (clock select : CKS2) 0 010 = /32

3 (reset select : RSTSEL) 0 0 = poser-on reset

4 (reset enable : RSTEN) 0 0 = disable

5 (timer enable : TMEN) 0 0 = disable

6 (timer mode select : WT/nIT) 0 0 = interval timer mode

7 (Interrupt enable : INTEN) 0 0 = disable

INITIAL

VALUE

011 = /64 100 = / 256 101 = /512 110 = /2048 111 = /8192

1 = manual reset

1 = enable

1 = watchdog timer mode

1 = enable

FUNCTION

sources for input to the TCNT.

select the type of generated internal reset if the TCNT overflows in the watchdog timer mode. select whether to reset the chip internally or not if the TCNT overflows in the watchdog timer mode. enable or disable the timer

select whether to use the WDT as a watchdog timer or interval timer enable or disable the interrupt request

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GDC21D601

Reset Status Register (RSTSR)

Two-bit read only register. The RSTSR indicates whether TCNT is overflowed or not. The RSTSR is initialized to 0x0 by the reset signal, nB_RES. Bit 0 (WTOVF) indicates that the TCNT has overflowed in the watchdog timer mode. Bit 1 (ITOVF) indicates that the TCNT has overflowed in the interval timer mode.

Table 5. SR Bit Description

BIT

0 (watchdog timer overflow flag : WTOVF) 0 indicate that the TCNT has overflowed in the

1 (interval timer overflow flag : ITOVF) 0 indicate that the TCNT has overflowed in the

INITIAL VALUE

FUNCTION

watchdog timer mode.

interval timer mode

Page 76

7. Examples of Register Setting

7.1 Interval Timer Mode

TCNT = 0x00 TRCR = 0xA0

B_CLK

MAIN_CLOCK

P_SEL

P_WRITE

P_STB

B_RES[0]

B_RES[1]

P_A

P_D

TCNT

TCSR

RSTCSR

WDTINT

FAULT

PORESET

MNRESET

OVERFLOW

FD FE

00111000 10111000 00111000

GDC21D601

13 14

Figure 6. Interrupt Clear in the Interval Timer Mode

Page 77

7.2 Watchdog Timer Mode with Internal Reset Disable

¡-

TCNT = 0x00 (normally) TRCR = 0xE0

GDC21D601

B_CLK

MAIN_CLOCK

P_SEL

P_WRITE

P_STB

B_RES[0]

B_RES[1]

P_A

P_D

TCNT

RSTCSR

TCSR

WDTINT

FAULT

PORESET

MNRESET

OVERFLOW

¡-

¡¡-

¡-

FD FE

00011111 10011111 00011111

Figure 7. Interrupt Clear in the Watchdog Timer Mode with Reset Disable

01111000 01111000

¡¡-

¡¡¡-

¡-

¡¡-

¡¡¡-

13 14

Page 78

7.3 Watchdog Timer Mode with Power-on Reset

¡-

TCNT = 0x00 TRCR = 0xF0

GDC21D601

B_CLK

MAIN_CLOCK

P_SEL

P_WRITE

P_STB

B_RES[0]

B_RES[1]

P_A

P_D

TCNT

RSTCSR

TCSR

WDTINT

FAULT

PORESET

MNRESET

OVERFLOW

¡-

¡¡-

¡-

FD FE

01011111 11011111

Figure 8. Interrupt Clear in the Watchdog Timer Mode with Power-on Reset

01111000 00011000

¡¡-

¡-

¡¡¡¡-

¡-

¡¡-

¡-

¡¡¡¡-

11011111

01111000

00011111

Page 79

7.4 Watchdog Timer Mode with Manual Reset

¡-

TCNT = 0x00 TRCR = 0xF8

GDC21D601

B_CLK

MAIN_CLOCK

P_SEL

P_WRITE

P_STB

B_RES[0]

B_RES[1]

P_A

P_D

TCNT

RSTCSR

TCSR

WDTINT

FAULT

PORESET

MNRESET

OVERFLOW

¡-

¡¡-

¡-

FD FE

01111111 11111111 01111111

Figure 9. Interrupt Clear in the Watchdog Timer Mode with Manual Reset

01111000 01111000

¡¡-

¡-

¡¡¡¡-

¡-

¡¡-

¡¡¡-

13 14

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Section 10. Interrupt Controller

1. General Description

The interrupt controller has the following features :

• Asynchronous interrupt controller

• Six external interrupts

• Nineteen internal interrupts

• Low interrupt latency

• Selection of the active modes of all interrupt source inputs (Level or Edge trigger)

• Maskable for each interrupt source and output signal

• Selection of the output paths (IRQ or FIQ for each interrupt source)

GDC21D601

IRQ [25:0]

Control Block

0 1 2

3 4 5

6 7 8

Mask Register

Trigger Mode Register

Trigger Polarity Register

Direction Register

FIQ status Register

IRQ status Register

FIQ Mask Register

IRQ Mask Register

Status clear Register

Bus Interface

Figure 1. Interrupt Controller Module Block Diagram

nIRQ

nFIQ

Internal Data Bus

Page 81

2. Hardware Interface and Signal Description

The Interrupt Controller module is connected to the APB bus.

Table 1. APB Signal Descriptions

GDC21D601

NAME TYPE

P_A[5:2] I APB Bridge This is the peripheral address bus, which is used by an individual

P_D[26:0] I/O APB Peripherals,

P_STB I APB Bridge This strobe signal is used to time all accesses on the peripheral

P_WRITE I APB Bridge When this signal is HIGH, it indicates a write to a peripheral.

P_SEL I APB Bridge When this signal is HIGH, it indicates that this module has been

INTESource[25:0] I APB peripherals/

NFIQ O ARM CORE NFIQ interrupt input to the ARM core. NIRQ O ARM CORE NIRQ interrupt input to the ARM core. BnRES I PMU Reset signal generated from the Power Management Unit.

SOURCE/

DESTINATION

B_D bus

external world

DESCRIPTION

peripheral for decoding register accesses to that peripheral. The addresses become valid before P_STB goes to HIGH and remain valid after P_STB goes to LOW. This is the bidirectional peripheral data bus. The data bus is driven by this block during read cycles (when P_WRITE is LOW).

bus. The falling edge of P_STB is coincident with the falling edge of B_CLK.

When this signal is LOW, it indicates a read from a peripheral. This signal has the same timing as the peripheral address bus. It becomes valid before P_STB goes to HIGH and remains valid after P_STB goes to LOW.

selected by the APB bridge. This selection is a decode of the system address bus (ASB). See AMBA Peripheral Bus Controller (ARM DDI - 0044) for more details. FIQ/IRQ interrupt signals into the Interrupt module. These active HIGH signals indicate that interrupt requests have been generated (IRQESource[25] is internally generated in the Interrupt Controller module and used to provide a software triggered IRQ).

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GDC21D601

Writes to the Interrupt Controller module are generated from the Peripheral Bus Controller module. Figure 2. Interrupt control module APB write cycle summarizes this.

B_CLK

P_SEL

P_WRITE

P_STB

P_D

Data

P_A

Address

Data

Figure 2. Interrupt Control Module APB Write Cycle

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GDC21D601

3. Interrupt Controller

3.1 Introduction

The interrupt controller provides a interface between multiple interrupt source and the processor. The interrupt controller supports internal and external interrupt sources. Internally there are 19 peripheral interrupt sources. Externally there are 6 interrupt sources. Therefore certain interrupt bits can be defined for the basic functionality required in any system, while the remaining bits are available for use by other devices in any particular implementation.

Table 2. Interrupt Controller Default Setting Value

INT # INTERRUPT SOURCE

INT 0 EXTERNAL INT0 INT 1 EXTERNAL INT1 INT 2 EXTERNAL INT2 INT 3 EXTERNAL INT3 INT 4 EXTERNAL INT4 INT 5 EXTERNAL INT5 INT 6 COM TX INT 7 COM RX INT 8 DMA

INT 9 RTC INT 10 WDT INT 11 I2C0 INT 12 I2C1 INT 13 I2C2 INT 14 UART0 INT 15 UART1 INT 16 Smart Card Interface INT 17 SSI CHA INT 18 SSI CHB INT 19 TIMER CHA INT 20 TIMER CHB INT 21 TIMER CHC INT 22 TIMER CHD INT 23 TIMER CHE INT 24 TIMER CHF INT 25 Software Interrupt

The Users can set the active mode of all interrupt source inputs. The default mode is the falling-edge trigger mode. Any inversion or latching required to provide edge sensitivity must be provided at the generating source of the interrupt.

No hardware priority scheme or any form of interrupt vectoring is provided, but the priority can be determined using FIQ mask register and IRQ mask register under software control.

FIQ mask register and IRQ mask register are also provided to generate an interrupt under software control. Typically these registers may be used to determine either a FIQ interrupt or an IRQ interrupt.

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GDC21D601

3.2 Interrupt Control

The interrupt controller provides interrupt source status and interrupt request status. The interrupt mask registers are used to determine whether an active interrupt source should generate an interrupt request to the processor or not. A logic HIGH in the interrupt mask register indicates that the interrupt source is masked and then doesn’t generate a request.

FIQ mask register and IRQ mask register indicate whether the interrupt source causes a processor interrupt or not. The interrupt mode is configured by interrupt trigger mode register and interrupt trigger polarity register. And Interrupt direction register indicates whether each interrupt source drives IRQ or FIQ.

The FIQ and IRQ status register is used to reflect the status of all channels set to produce an FIQ interrupt or IRQ interrupt. And the status registers are cleared by writing ‘1’ to the status clear register at the edge trigger mode only.

IRQ source0 IRQ source1 IRQ source2 IRQ source3 IRQ source4 IRQ source5

: : : : : :

IRQ source20 IRQ source21 IRQ source22 IRQ source23 IRQ source24 IRQ source25

Source Mask Control

Mask

Control

26 26 26

Trigger Mode Control

Edge/ Level

Control

Figure 3. Interrupt Control Flow Diagram

Polarity Control

High/

Low, Rising/ Falling

Control

Clear Control

Direction Control

FIQ

IRQ

Status Control

FIQ

IRQ

Request Control

FIQ Mask

IRQ

Mask

nFIQ

nIRQ

TIC registers are used only for the production test. TIC input register is used to drive interrupt request sources by the CPU. When this register bit 26 is set, other bits of TIC input register are regarded as interrupt sources. This bit is cleared by system reset and should be cleared in normal operation.

Bit 25 is used as a software interrupt source. When source mask control register bit 25 is HIGH, an interrupt request occurs. To disable the software interrupt, Source Mask Control Register bit 25 should be Low. Software interrupt source input is fixed active HIGH and level sensitive.

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GDC21D601

4. Interrupt Controller Memory Map

The base address of the interrupt controller is 0xFFFF F200. The offset of any particular register from the base address is fixed.

Table 3. Memory Map of the Interrupt Controller APB Peripheral

ADDRESS READ LOCATION WRITE LOCATION

IntBase + 0x000 Mask Register Mask Register IntBase + 0x004 Trigger Mode Register Trigger Mode Register IntBase + 0x008 Trigger Polarity Register Trigger Polarity Register

IntBase + 0x00C Direction Register Direction Register

IntBase + 0x010 FIQ Status Register (Read-only) IntBase + 0x014 IRQ Status Register (Read-only) IntBase + 0x018 FIQ Mask Register FIQ Mask Register

IntBase + 0x01C IRQ Mask Register IRQ Mask Register

IntBase + 0x020 Status Clear Register (Write-only) IntBase + 0x024 TicInput Register IntBase + 0x028 TicOutputRegister

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GDC21D601

5. Interrupt Controller Register Descriptions

The following registers are provided for both FIQ and IRQ interrupt controllers:

(1) Mask Register

Readable and Writable. The interrupt mask register is used to mask the interrupt input sources and defines which active sources will generate an interrupt request to the processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the interrupt mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. Once a bit is masked, the corresponding bit in the status register is cleared. On reset, all interrupt input sources are masked.

‘1’ : Mask ‘0’ : Unmask Initial value : 0x3FFFFFF

25 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

(2) Trigger Mode Register

Readable and Writable. The interrupt trigger mode register is used to configure the interrupts with the interrupt trigger polarity register. Each interrupt can be configured to level or edge triggered. A bit value 0 indicates that the interrupt is configured to edge triggered and a bit value 1 indicates that the interrupt is configured to level triggered. On reset, all interrupt input sources are configured to edge triggered.

‘1’ : Level Trigger Mode ‘0’ : Edge Trigger Mode Initial value : 0x2000000

25 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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GDC21D601

(3) Trigger Polarity Register

Readable and Writable. The interrupt trigger polarity register is used to configure the interrupts with the interrupt trigger mode register. Each interrupt can be configured to rising/high or falling/low active. A bit value 0 indicates that the interrupt is configured to falling active for edge trigger mode and to low active for level trigger mode. A bit value 1 indicates that the interrupt is configured to rising active for edge trigger mode and to high active for level trigger mode. On reset, all interrupt input sources are configured to falling/low active.

‘1’ : Rising or High ‘0’ : Falling or Low Initial value : 0x2000000

25 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4. Interrupt Source Trigger Mode of the Interrupt Controller

TRIGGER MODE REGISTER TRIGGER POLARITY REGISTER DESCRIPTION

0 0 Falling-Edge (Default) 0 1 Rising-Edge 1 0 Low-Level 1 1 High-Level

(4) Direction Register

Readable and Writable. The interrupt direction register is used to determine whether each interrupt source drives IRQ or FIQ. A bit value 0 indicates that the interrupt is driven to IRQ and a bit value 1 indicates that the interrupt is driven to FIQ. On reset, all interrupt input sources drive IRQ.

‘1’ : Request FIQ ‘0’ : Request IRQ Initial value : 0x0000000

25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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GDC21D601

(5) FIQ Status Register

Read-only. The FIQ status register is used to reflect the status of all channels set to produce an FIQ interrupt (IDR(i) = 1). When an interrupt is set for an FIQ occurring, the corresponding bit is set in FIQ status register. The interrupt handler will examine this register to determine the channel(s) that caused the FIQ interrupt. When the status clear register is written to ‘1’ , the corresponding bit is cleared if that channel is configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor.

‘1’ : Interrupt Event Occur ‘0’ : No Interrupt Event Initial value : 0x0000000

25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(6) IRQ Status Register

Read-only. The IRQ status register is used to reflect the status of all channels set to produce an IRQ interrupt (IDR(i) = 0). When an interrupt is set for an IRQ occurring, the corresponding bit is set in IRQ status register. The interrupt handler will examine this register to determine the channel(s) that caused the IRQ interrupt. When the status clear register is written to ‘1’ , the corresponding bit is cleared if that channel is configured to edge trigger mode. A HIGH bit indicates that the interrupt is active and will generate an interrupt to the processor.

‘1’ : Interrupt Event Occur ‘0’ : No Interrupt Event Initial value : 0x0000000

25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(7) FIQ Mask Register

Readable and Writable. The FIQ request mask register is used to mask the request to generate an interrupt to a processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the FIQ request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all FIQ requests are unmasked.

‘1’ : Request Mask ‘0’ : Request Unmask Initial value : 0x0000000

25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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GDC21D601

(8) IRQ Mask Register

Readable and Writable. The IRQ request mask register is used to mask the request to generate an interrupt to a processor. If certain bits within the interrupt controller are not implemented, the corresponding bits in the IRQ request mask register must be masked. A bit value 0 indicates that the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the interrupt is masked. On reset, all IRQ requests are unmasked.

‘1’ : Request Mask ‘0’ : Request Unmask Initial value : 0x0000000

25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(9) Status Clear Register

Write-only. The status clear register is used to clear bits in the status register configured to the edge trigger mode. If the channels are configured to the level trigger mode, the corresponding bits in the FIQ status register and the IRQ status register have no effect. This register is cleared when the signal, P_STB, is LOW after this register is written to ‘1’ . When writing to this register, each data bit that is HIGH causes the corresponding bit in the status register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the status register. Note that the status clear register has an effect on the status register in the edge trigger mode.

‘1’ : Clear the status register ‘0’ : Not clear Initial value : 0x0000000

25 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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GDC21D601

Section 11. Real Time Clock

1. General Description

This module is a 32-bit counter clocked by a 32.768KHz clock. This clock needs to be provided by the system, since there is no oscillator inside the block. The clock is divided in the RTC core to provide a 1Hz clock used to drive a 32-bit counter which forms the Real Time Clock (RTC). It also contains a 32-bit match register which can be programmed to generate an interrupt signal when the time in the RTC matches the specific value written to this register (alarm function - RTC event). The RTC has one event output which is synchronized with PCLK. RTCIRQ is to be connected to the system interrupt controller.

from/to APB

from

xtal

oscillator

BnRES PCLK PSELRTC PSTB PWRITE

PA[4:2] PD[31:0]

CLK32K

APB

INTERFACE

RTC

CORE

(COUNTER + REGISTERS)

Figure 1. Real Time Clock Connections Diagram

RTCIRQ

synchronized

event output

interrupt

controller

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GDC21D601

2. Signal Description

The RTC module is connected to the APB bus. Table 1. APB signal descriptions describes the APB signals used and produced.

Table 1. APB Signal Descriptions

NAME TYPE

PCLK I Power

P_A[4:2] I APB Bridge This is the peripheral address bus, which is used by an individual

P_D[31:0] I/O APB

P_STB I APB Bridge This strobe signal is used to time all accesses on the peripheral bus.

P_WRITE I APB Bridge When this signal is HIGH, it indicates a write to a peripheral. When

P_SEL I APB Bridge When this signal is HIGH, it indicates that this module has been

BnRES I Power

RTCIRQ O Interrupt

SOURCE/

DESTINATION

Management Unit

Peripherals, B_D bus

Management Unit

Controller

DESCRIPTION

The slow APB clock used to re-synchronize data is transferred between the 32.768KHz clock and the APB.

peripheral for decoding register accesses to this peripheral. The addresses become valid before P_STB goes to HIGH and remain valid after P_STB goes to LOW. This is the bi-directional peripheral data bus. The data bus is driven by this block during read cycles (when P_WRITE is LOW).

The falling edge of P_STB is coincident with the falling edge of B_CLK.

this signal is LOW, it indicates a read from a peripheral. This signal has the same timing as the peripheral address bus. It becomes valid before P_STB goes to HIGH and remains valid after P_STB goes to LOW.

selected by the APB bridge. This selection is a decode of the system address bus (ASB). See AMBA Peripheral Bus Controller for more details. Reset signal generated from the PMU

Interrupt signal to the Interrupt module. When this signal is HIGH, it indicates a valid comparison between the counter value and the match register. It also indicates 1Hz interval with enable bit in control register.

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GDC21D601

3. Hardware Interface

The APB interface is fully APB-compliant. The APB is a non-pipelined low-power interface designed to provide a simple interface to slave peripherals.

B_CLK

P_SEL

P_WRITE

P_STB

P_D

P_A

B_CLK

P_SEL

P_WRITE

P_STB

P_D

P_A

Data

Address

Data

Figure 2. RTC Module APB Write Cycle

Data

Address

Data

Figure 3. RTC Module APB Read Cycle

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GDC21D601

4. Functional Description

The counter is loaded by writing it to the RTC data register. The counter will count up on each rising edge of the clock and loops back with 0 when the maximum value (0xFFFFFFFF) is reached. At any moment the counter value can be obtained by reading the RTC data register.

The value of the match register can also be read at any time, and the read does not affect the counter value. The status of the interrupt signal is available in the status register. The status bit is set if a comparator match event has occurred or 1 second has elapsed. Reading from the status register will clear the status register.

Data In

A P B

B u s

Data Out

Interface to APB

PCLK

RTC APB

registers

Match

Sync

Control

1Hz

RTC

Counter

Module core

RTCIRQ

32-bit

comparator

Ripple

CLK32K

Figure 4. RTC Block Diagram

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GDC21D601

5. Real Time Clock Memory Map

The base address of the RTC is fixed as 0xFFFF F300 and the offset of any particular register from the base address is fixed.

Table 2. RTC Memory Map

ADDRESS READ LOCATION WRITE LOCATION

RTC Base + 0x00 RTC data register (RTCDR) RTC data register (RTCDR) RTC Base + 0x04 RTC match register (RTCMR) RTC match register (RTCMR) RTC Base + 0x08 RTC status (RTCS) RTC Base + 0x0C RTC clock divider (RTCDV) RTC clock divider (RTCDV) RTC Base + 0x10 RTC control register (RTCCR) RTC control register (RTCCR) RTC Base + 0x14 RTC Tic selection register (RTCTS) RTC Base + 0x18 TicCLK32K RTC Base + 0x1C TicCLKPCLK

Note The RTC clock divider register may only be written to when in test mode.

6. Real Time Clock Register Descriptions

The following user registers are provided :

RTC Data Register (RTCDR)

Read/Write. Writing to this 32-bit register will load the counter. A read will give the current value of the counter.

RTC Match Register (RTCMR)

Read/Write. Writing to this 32-bit register will load the match register. This value can also be read back.

RTC Status Register (RTCS)

Read-only. When performing a read from this location the interrupt flag will be cleared. If a match event occurs, bit[1] will be set. For a second event, bit[0] will be set. This register is affected by the control register.

RTC Clock Divider (RTCDV)

Read/Write. The reads to the register will return only four bits of the clock divider output. Bits [3:0] will return bits (14, 11, 7, 3) of the divider output. Writing zero to bit[0] clears this divider.

RTC Control Register (RTCCR)

Read/Write. This register enables the interrupt. Bit[1] enables the match event interrupt (default disable = 0). Bit[0] enables second event interrupt (default disable = 0).

RTC Tic Selection (RTCTS)

Write-only. This register is for production test purposes. Bit[0] enables TicCLK32K for 32kHz clock replacement. Bit[1] enables TicCLKPCLK for PCLK clock replacement.

TicCLK32K

Write-only. This generates 32kHz clock for production test purposes.

TicCLKPCLK

Write-only. This generates PCLK clock for production test purposes.

Page 95

Section 12. General Purpose Timer Unit

16-bit timer channel1

16-bit timer channel0

16-bit timer channel2

16-bit timer channel3

16-bit timer channel4

Bus Interface

1. General Description

The general-purpose timer unit has:

• Six channels with 16bit counter

• 12 different pulse outputs and 12 different pulse inputs

• Independent function with 12 general registers

• Compare match waveform output function

• Input capture function

• Counter-clearing function at compare match or input capture mode

• Synchronizing mode

• PWM mode

• 18 interrupt sources

• Selectable 4 internal clock sources and 4 external clock sources

EXT_CLK1- EXT_CLK4

Clock

pclk

Generation

Selection

Clock

GDC21D601

TINT0 - TINT5

TCIO0A - TCIO5A TCIO0B - TCIO5B

Figure 1. General-purpose Timer Unit Module Block Diagram

Control

Module data bus

TSTARTR

TSYNR

TPWMR

Internal data bus

Page 96

2. Hardware Interface and Signal Description

The General-purpose Timer Unit module is connected to the APB bus.

Table 1. APB Signal Descriptions

GDC21D601

NAME TYPE

PCLK I PMU Peripheral clock. This clock times all bus transfers. BnRES I PMU Reset signal generated from the PMU PA[7:2] I APB Bridge This is the peripheral address bus, which is used by an individual

PD[31:0] I/O APB Peripherals,

PSTB I APB Bridge This strobe signal is used to time all accesses on the peripheral bus.

PWRITE I APB Bridge When this signal is HIGH, it indicates a write to a peripheral. When

PSEL I APB Bridge When this signal is HIGH, it indicates that the APB bridge has

EXT_CLK1 I External External clock1 input. This signal is selected independently from

EXT_CLK2 I External External clock2 input. This signal is selected independently from

EXT_CLK3 I External External clock3 input. This signal is selected independently from

EXT_CLK4 I External External clock4 input. This signal is selected independently from

TCIO0A I/O External This signal is used as GRA0 input in input capture mode, GRA0

TCIO0B I/O External This signal is used as GRB0 input in input capture mode, GRB0

TCIO1A I/O External This signal is used as GRA1 input in input capture mode, GRA1

TCIO1B I/O External This signal is used as GRB1 input in input capture mode, GRB1

TCIO2A I/O External This signal is used as GRA2 input in input capture mode, GRA2

TCIO2B I/O External This signal is used as GRB2 input in input capture mode, GRB2

SOURCE/

DESTINATION

B_D bus

DESCRIPTION

peripheral for decoding register accesses to that peripheral. The addresses become valid before PSTB goes to HIGH and remain valid after PSTB goes to LOW. This is the bi-directional peripheral data bus. This block drives the data bus during read cycles (when PWRITE is LOW).

The falling edge of PSTB is coincident with the falling edge of PCLK.

this signal is LOW, it indicates a read from a peripheral. This signal has the same timing as the peripheral address bus. It becomes valid before PSTB goes to HIGH and remains valid after PSTB goes to LOW.

selected this module. This selection is a decode result of the system address bus (ASB). See AMBA Peripheral Bus Controller for more details.

EXT_CLK2, EXT_CLK3, and EXT_CLK4.

EXT_CLK1, EXT_CLK3, and EXT_CLK4.

EXT_CLK1, EXT_CLK2, and EXT_CLK4

EXT_CLK1, EXT_CLK2, and EXT_CLK3.

output in output compare mode, and PWM output in PWM mode.

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GDC21D601

NAME TYPE

TCIO3A I/O External This signal is used as GRA3 input in input capture mode, GRA3

TCIO3B I/O External This signal is used as GRB3 input in input capture mode, GRB3

TCIO4A I/O External This signal is used as GRA4 input in input capture mode, GRA4

TCIO4B I/O External This signal is used as GRB4 input in input capture mode, GRB4

TCIO5A I/O External This signal is used as GRA5 input in input capture mode, GRA5

TCIO5B I/O External This signal is used as GRB5 input in input capture mode, GRB5

TINT0 O Interrupt

TINT1 O Interrupt

TINT2 O Interrupt

TINT3 O Interrupt

TINT4 O Interrupt

TINT5 O Interrupt

SOURCE/

DESTINATION

Controller

DESCRIPTION

output in output compare mode, and PWM output in PWM mode.

output in output compare mode, and PWM output in PWM mode. Interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in channel0. Interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in channel1. Interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in channel2. Interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in channel3. Interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in channel4. Interrupt signal to the Interrupt Controller module. This signal indicates that an interrupt has been generated in channel5.

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PCLK

PSEL

PWRITE

PSTB

PDPARegister

Address

Data

The writes to the General-purpose Timer Unit module are generated from the Peripheral Bus Controller module. Figure 2. General-purpose timer unit module APB write cycle summarizes this.

B_CLK

P_SEL

P_WRITE

P_STB

P_D

P_A

Figure 2. General-Purpose Timer Unit Module APB Read Cycle

Data

Address

Data

Figure 3. General-Purpose Timer Unit Module APB Write Cycle

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3. General Purpose Timer Unit Introduction

The GDC21D601 has a general-purpose timer unit (GPTU) with six channels of 16-bit timer. There are two counter operation modes: a free running mode and a periodic mode. And each channel has independent operating modes. There are common functions for each channel: counter operation, input capture, compare match, PWM, and synchronized clear and write.

It is possible to select one of eight counter clock sources for all channels.

• Internal clock : counting at falling edge

BCLK / 2 BCLK / 4 BCLK / 16 BCLK / 64

• External clock: counting at rising, falling, or both edge that are user-selectable.

There are four kinds of counter clear sources which can be selected by user’s setting.

• None : never clear until overflow for free running mode

• GRA match or TPA input capture

• GRB match or TPB input capture

• Synchronous clear

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4. General Purpose Timer Unit Operation

The operation modes are described below.

Free Running Mode

Each channel can run from 0 to FFFF repeatedly. When it reaches FFFF, the interrupt signal is generated as user's setting.

Compare Match Mode

Each channel has 2 general registers and user can read or write from/to the registers. If user wrote some values to general register, and the counter reached that value, the channel generates interrupt and external output by user's setting. The output value can be '1', '0', or toggle value. The counter can be cleared by user's setting when the match with general register is detected.

Input Capture Mode

When set to input capture mode and rising any event at TPA or TPB, the counter value is transferred to GRA or GRB respectively. The interrupt can be generated and the external event may be rising edge, falling edge or any edge by user's setting. The counter can be cleared by user's setting when the event at TPA or TPB is detected.

Synchronized Clear & Write Mode

When some channels are set to synchronization mode, and one of them is cleared by compare match or input capture, the other channels can be cleared simultaneously by user's setting. When some channels are set to synchronization mode and user would write any value to one of them, the other channels can be written with same value simultaneously by user's setting.

PWM Mode

When a channel is set to PWM mode, the channel operates like a compare match mode and the output on compare match event is generated only at TPA. The TPA value is '1' when it is the match with GRA, and '0' when it is the match with GRB.

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