Ver: 1.1
Jul 26, 2002
TEL: 886-3-5788833
http://www.gmt.com.tw
6
G696/G697
Global Mixed-mode Technology Inc.
Pin Description
PIN NAME FUNCTION
RESET
(G696L/G697L)
RESET
Output remains low while VCC is below the reset threshold, and for delay time set by CD
after V
CC
rises above the reset threshold.
1
RESET (G696H)
RESET Output remains high while V
CC
is below the reset threshold, and for delay time set by CD
after V
CC
rises above the reset threshold.
2 VCC Supply Voltage (+5V, +3.3V, +3.0V)
3 GND Ground
4 N.C. No Connection.
5 CD External Programmable time delay is set by the capacitor connect to CD pin.
Detailed Description
A microprocessor’s (µP’s) reset input starts the µP in a
known state. The G697L/G696L/G696H assert reset to
prevent code-execution errors during power-up,
power-down, or brownout conditions. They assert a
reset signal whenever the V
CC
supply voltage declines
below a preset threshold (V
TH-
), keeping it asserted for
time delay set by capacitor connected to C
D
pin, after
V
CC
has risen above the high reset threshold V
TH+
(V
TH-+VHYS
). The G697L uses an open-drain output,
and the G696L/G696H have a push-pull output stage.
Connect a pull-up resistor on the G697L’s
RESET out-
put to any supply between 0 and 5.5V.
The time delay is set by external capacitor C
D
, and
internal pull up resistor R
D
. When the voltage at CD
pin exceeds the buffer threshold, typically 0.675 V
CC
,
the
RESET output high (RESET output low). The
voltage detector and buffer have built-in hysterisis to
prevent erratic reset operation. The formula of time
delay is T (ms) ≅ 1685 C
D
(µF). Fig1 and Fig2 show a
timing deagram and a Functional Block.
Figure3.
RESET
Valid to VCC = Ground Circuit
Ensuring a Valid Reset Output Down to V
CC
= 0
When V
CC
falls below 0.8V, the G696 RESET output
no longer sinks current—it becomes an open circuit.
Therefore, high-impedance CMOS logic inputs con-
nected to
RESET can drift to undetermined voltages.
This presents no problem in most applications since
most µP and other circuitry is inoperative with
VCC
below 0.8V. However, in applications where RESET
must be valid down to 0V, adding a pull-down resistor
to
RESET causes any stray leakage currents to flow
to ground, holding
RESET low (Figure 4). R1’s value
is not critical; 100kΩ is large enough not to load
RESET and small enough to pull RESET to ground.
A 100kΩ pull-up resistor to V
CC
is also recommended
for the G697L if
RESET is required to remain valid
for V
CC
< 0.8V.
Figure 4. Interfacing to µPs with Bidirectional Reset
I/O
Figure 5. G697L Open-Drain
RESET
Output Allows
Use with Multiple Supplies
V
CC
RESET
GND
G696
R1
100k
V
CC
RESET
GND
G696
R1
100k
RESET
INPUT
GND
µP
V
CC
RESET
GND
G697
V
CC
V
CC
MOTOROLA
68HCXX
R
PULL-UP
RESET
INPUT
GND
µP
V
CC
RESET
GND
G697
V
CC
V
CC
MOTOROLA
68HCXX
R
PULL-UP
RESET
INPUT
GND
5V SYSTEM
V
CC
RESET
GND
G697
V
CC
R
PULL-UP
+3.3V
+5.0
RESET
INPUT
GND
5V SYSTEM
V
CC
V
CC
R
PULL-UP
+3.3V
+5.0V
RESET
INPUT
GND
5V SYSTEM
V
CC
RESET
GND
G697
V
CC
R
PULL-UP
+3.3V
+5.0
RESET
INPUT
GND
5V SYSTEM
V
CC
V
CC
R
PULL-UP
+3.3V
+5.0V