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FQD2N60C / FQU2N60C

N-Channel QFET® MOSFET

600 V, 1.9 A, 4.7 Ω

FQD2N60C / FQU2N60C — N-Channel QFET

November 2015

Features

• 1.9 A, 600 V, R
I

= 0.95 A

D

• Low Gate Charge (Typ. 8.5 nC)

• Low Crss (Typ. 4.3 pF)

• 100% Avalanche Tested

•RoHS Compliant

= 4.7 Ω (Max.) @ VGS = 10 V,

DS(on)

Description

This N-Channel enhancement mode power MOSFET is
produced using Fairchild Semiconductor’s proprietary
planar stripe and DMOS technology. This advanced
MOSFET technology has been especially tailored to reduce
on-state resistance, and to provide superior switching
performance and high avalanche energy strength. These
devices are suitable for switched mode power supplies,
active power factor correction (PFC), and electronic lamp
ballasts.

D

D

G

S

D-PAK

G

D

S

I-PAK

G

S

Absolute Maximum Ratings T

= 25°C unless otherwise noted.

C

Symbol Parameter FQD2N60CTM / FQU2N60CTU Unit

V

DSS

I

D

I

DM

V

GSS

E

AS

I

AR

E

AR

Drain-Source Voltage

Drain Current

- Continuous (T

- Continuous (T

Drain Current - Pulsed

Gate-Source Voltage

Single Pulsed Avalanche Energy

Avalanche Current

Repetitive Avalanche Energy

dv/dt Peak Diode Recovery dv/dt

Power Dissipation (TA = 25°C)*

P

D

Power Dissipation (T

= 25°C)

C

- Derate above 25°C

, T

T

J

STG

T

L

Operating and Storage Temperature Range
Maximum lead temperature for soldering purposes,
1/8" from case for 5 seconds

= 25°C)

C

= 100°C)

C

(Note 1)

(Note 2)

(Note 1)

(Note 1)

(Note 3)

600 V

1.9 A

1.14 A

7.6 A

± 30 V

120 mJ

1.9 A

4.4 mJ

4.5 V/ns

2.5 W

44 W

0.35 W/°C

-55 to +150 °C

300 °C

®

MOSFET

Thermal Characteristics

Symbol Parameter

R

θJC

R

θJA

©2003 Fairchild Semiconductor Corporation
FQD2N60C / FQU2N60C Rev. 1.4

Thermal Resistance, Junction-to-Case, Max. 2.87
Thermal Resistance, Junction-to-Ambient (minimum pad of 2 oz copper), Max. 110

Thermal Resistance, Junction-to-Ambient (* 1 in

2

pad of 2 oz copper), Max.

1

FQD2N60CTM /

FQU2N60CTU

50

Unit

°C/W

www.fairchildsemi.com

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FQD2N60C FQD2N60CTM D-PAK 330 mm 16 mm 2500 units

FQU2N60C FQU2N60CTU I-PAK Tube N/A 70 units

FQD2N60C / FQU2N60C — N-Channel QFET

Electrical Characteristics T

= 25°C unless otherwise noted.

C

Symbol Parameter Test Conditions Min Typ Max Unit

Off Characteristics

V

BV

DSS

ΔBV

DSS

/ ΔT

I

DSS

I

GSSF

I

GSSR

Drain-Source Breakdown Voltage

Breakdown Voltage Temperature
Coefficient

J

Zero Gate Voltage Drain Current

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

= 0 V, ID = 250 μA 600 -- -- V

GS

= 250 μA, Referenced to 25°C -- 0.6 -- V/°C

I

D

= 600 V, VGS = 0 V

V

DS

= 480 V, TC = 125°C

V

DS

V

= 30 V, VDS = 0 V -- -- 100 nA

GS

V

= -30 V, VDS = 0 V -- -- -100 nA

GS

-- -- 1 μA

-- -- 10 μA

On Characteristics

V

V

GS(th)

R

DS(on)

g

FS

Gate Threshold Voltage

Static Drain-Source
On-Resistance

Forward Transconductance

= VGS, ID = 250 μA2.0--4.0V

DS

V

= 10 V, ID = 0.95 A -- 3.6 4.7 Ω

GS

= 40 V, ID = 0.95 A -- 5.0 -- S

V

DS

Dynamic Characteristics

C

iss

C

oss

C

rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

= 25 V, VGS = 0 V,

V

DS

f = 1.0 MHz

-- 180 235 pF

-- 20 25 pF

-- 4.3 5.6 pF

Switching Characteristics

V

t

d(on)

t

r

t

d(off)

t

f

Q

Q

Q

Turn-On Delay Time

Turn-On Rise Time

= 300 V, ID = 2 A,

DD

= 25 Ω

R

G

Turn-Off Delay Time

Turn-Off Fall Time

V

g

gs

gd

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

= 480 V, ID = 2 A,

DS

= 10 V

V

GS

(Note 4)

(Note 4)

-- 9 28 ns

-- 25 60 ns

-- 24 58 ns

-- 28 66 ns

-- 8.5 12 nC

-- 1.3 -- nC

-- 4.1 -- nC

®

MOSFET

Drain-Source Diode Characteristics and Maximum Ratings

I

S

I

SM

V

SD

t

rr

Q

rr

NOTES:

1. Repetitive Rating : Pulse width limited by maximum junction temperature.

2. L = 56 mH, I

3. I

SD

4. Essentially independent of operating temperature.

©2003 Fairchild Semiconductor Corporation
FQD2N60C / FQU2N60C Rev.1.4

Maximum Continuous Drain-Source Diode Forward Current

Maximum Pulsed Drain-Source Diode Forward Current

Drain-Source Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

= 2 A, VDD = 50 V, RG = 25 Ω, starting TJ = 25°C.

AS

≤ 2 A, di/dt ≤ 200 A/μs, VDD ≤ BV

starting TJ = 25°C.

DSS,

V

= 0 V, IS = 1.9 A -- -- 1.4 V

GS

V

= 0 V, IS = 2 A,

GS

dI

/ dt = 100 A/μs

F

-- -- 1.9 A

-- -- 7.6 A

-- 230 -- ns

-- 1.0 -- μC

2

www.fairchildsemi.com

Typical Performance Characteristics

10

-1

10

0

10

1

10

-2

10

-1

10

0

V

GS

Top : 15. 0 V

10.0 V

8.0 V

7.0 V

6.5 V

6.0 V

5.5 V

5.0 V

Bottom : 4.5 V

※ Notes :

1. 250μ s Pulse Test

2. T

C

= 25℃

I

D

, Drain Current [A]

VDS, Drai n-Source Voltage [V]

246810

10

-1

10

0

10

1

150oC

25oC

-55oC

※ Notes :

1. V

DS

= 40V

2. 250μ s Pulse Test

I

D

, Drain Current [A]

VGS, Gate-Source Volt age [V]

012345

0

2

4

6

8

10

12

VGS = 20V

VGS = 10V

※ Note : T

J

= 25℃

R

DS(ON)

[Ω ],

Drain-Source On-Resistance

ID, Drai n Curr ent [A]

0.2 0.4 0.6 0.8 1.0 1.2 1.4

10

-1

10

0

150℃

※ Notes :

1. V

GS

= 0V

2. 250μ s Pulse Test

25℃

I

DR

, Reverse Drain Current [A]

VSD, Source-Drain voltage [ V]

10

-1

10

0

10

1

0

50

100

150

200

250

300

350

400

450

500

C

iss

= Cgs + Cgd (Cds = shorted)

C

oss

= Cds + C

gd

C

rss

= C

gd

※ Notes ;

1. V

GS

= 0 V

2. f = 1 MHz

C

rss

C

oss

C

iss

Capacitance [pF]

VDS, Drain- Source Voltage [V]

0246810

0

2

4

6

8

10

12

VDS = 300V

VDS = 120V

VDS = 480V

※ Note : I

D

= 2A

V

GS

, Gate-Source Voltage [V]

QG, Total Gate Charge [nC]

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

FQD2N60C / FQU2N60C — N-Channel QFET

Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage

Drain Current and Gate Voltage Variation vs. Source Current

and Temperatue

Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics

®

MOSFET

©2003 Fairchild Semiconductor Corporation
FQD2N60C / FQU2N60C Rev.1.4

3

www.fairchildsemi.com

Typical Performance Characteristics (Continued)

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2

※ Notes :

1. V

GS

= 0 V

2. I

D

= 250 μA

BV

DSS

, (Normalized)

Drain-Source Breakdown Voltage

TJ, Junct ion Temperature [oC]

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

※ Notes :

1. V

GS

= 10 V

2. I

D

= 0.95 A

R

DS(ON)

, (Normalized)

Drain-Source On-Resistance

TJ, Junction Temperature [oC]

10

0

10

1

10

2

10

3

10

-2

10

-1

10

0

10

1

100 ms

DC

10 ms

1 ms

100 μs

Operation in This Area
is Limited by R

DS(on)

※ Notes :

1. T

C

= 25 oC

2. T

J

= 150 oC

3. Single Pulse

I

D

, Drain Current [A]

VDS, Drain-Source Vol tage [V]

25 50 75 100 125 150

0.0

0.4

0.8

1.2

1.6

2.0

I

D

, Drain Current [A]

TC, Case Temperature [ ]℃

10

-5

10

-4

10

-3

10

-2

10

-1

10

0

10

1

10

-1

10

0

※ No tes :

1. Z

θ JC

(t) = 2 .87 /W M ax.℃

2. D uty Fa cto r, D= t1/t

2

3. TJM - TC = PDM * Z

θ JC

(t)

single pulse

D=0.5

0.02

0.2

0.05

0.1

0.01

Z

θ JC

(t), Thermal Response

t1, Squ a re W av e Puls e D u ra tion [s e c]

t

1

P

DM

t

2

Z

θJC

(t), Thermal Response [

o

C/W]

Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation

vs. Temperature vs. Temperature

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

FQD2N60C / FQU2N60C — N-Channel QFET

®

MOSFET

©2003 Fairchild Semiconductor Corporation
FQD2N60C / FQU2N60C Rev.1.4

Figure 11. Transient Thermal Response Curve

4

www.fairchildsemi.com

V

GS

V

DS

10%

90%

t

d(on)tr

t

on

t

off

t

d(off )

t

f

V

DD

10V

V

DS

R

L

DUT

R

G

V

GS

V

GS

V

DS

10%

90%

t

d(on)tr

t

on

t

off

t

d(off )

t

f

V

DD

10V

V

DS

R

L

DUT

R

G

V

GS

Charge

V

GS

10V

Q

g

Q

gs

Q

gd

3mA

V

GS

DUT

V

DS

300nF

50KΩ

200nF

12V

Same Type

as DUT

Charge

V

GS

10V

Q

g

Q

gs

Q

gd

3mA

V

GS

DUT

V

DS

300nF

50KΩ

200nF

12V

Same Type

as DUT

IG = const.

E

AS

=LI

AS

2

---­2

1

-------------------­BV

DSS-VDD

BV

DSS

V

DD

V

DS

BV

DSS

t

p

V

DD

I

AS

V

DS

(t)

I

D

(t)

Time

10V

DUT

R

G

L

I

D

t

p

E

AS

=LI

AS

2

---­2

1

E

AS

=LI

AS

2

---­2

1

---­2

1

-------------------­BV

DSS-VDD

BV

DSS

V

DD

V

DS

BV

DSS

t

p

V

DD

I

AS

V

DS

(t)

I

D

(t)

Time

10V

DUT

R

G

LL

IDI

D

t

p

Figure 12. Gate Charge Test Circuit & Waveform

Figure 13. Resistive Switching Test Circuit & Waveforms

FQD2N60C / FQU2N60C — N-Channel QFET

®

MOSFET

V

GS

V

V

GS

GS

©2003 Fairchild Semiconductor Corporation
FQD2N60C / FQU2N60C Rev.1.4

Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms

5

www.fairchildsemi.com

DUT

V

DS

+

_

Driver

R

G

Same Type

as DUT

V

GS

• dv/dt controlled by R

G

•ISDcontrolled by pulse period

V

DD

L

I

SD

10V

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

V

DD

Body Diode

Forward Voltage Drop

V

SD

IFM, Body Diode Forward Current

Body Diode Reverse Current

I

RM

Body Diode Recovery dv/dt

di/dt

D =

Gate Pulse Width
Gate Pulse Period

--------------------------

DUT

V

DS

+

_

Driver

R

G

Same Type

as DUT

V

GS

• dv/dt controlled by R

G

•ISDcontrolled by pulse period

V

DD

LL

I

SD

10V

V

GS

( Driver )

I

SD

( DUT )

V

DS

( DUT )

V

DD

Body Diode

Forward Voltage Drop

V

SD

IFM, Body Diode Forward Current

Body Diode Reverse Current

I

RM

Body Diode Recovery dv/dt

di/dt

D =

Gate Pulse Width
Gate Pulse Period

--------------------------

D =

Gate Pulse Width
Gate Pulse Period

--------------------------

Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

FQD2N60C / FQU2N60C — N-Channel QFET

®

MOSFET

©2003 Fairchild Semiconductor Corporation
FQD2N60C / FQU2N60C Rev.1.4

6

www.fairchildsemi.com

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ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf
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