Datasheet FQD2N60C, FQU2N60C Datasheet (Fairchild)

Page 1
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
FQD2N60C/FQU2N60C
600V N-Channel MOSFET
• 1.9A, 600V, R
• Low gate charge (typical 8.5 nC)
• Low Crss (typical 4.3 pF)
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant
DS(on)
GS
= 4.7Ω @V
D-PAK
FQD Series
GS
D
= 10 V
GSD
January 2009
QFET
®
Description
These N-Channel enhancement mode power field effect transis­tors are produced using Fairchild’s proprietary, planar stripe, DMOS technology.
This advanced technology has been especially tailored to mini­mize on-state resistance, provide superior switching perfor­mance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high effi­ciency switched mode power supplies, active power factor cor­rection, electronic lamp ballasts based on half bridge topology.
D
!!!!
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◀◀◀◀
▲▲▲▲
▲▲▲▲
●●●●
I-PAK
FQU Series
!!!!
!!!!
G
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S
Absolute Maximum Ratings
Symbol Parameter FQD2N60C / FQU2N60C Units
V
DSS
I
D
I
DM
V
GSS
E
AS
I
AR
E
AR
dv/dt Peak Diode Recovery dv/dt
P
D
, T
T
J
STG
T
L
Drain-Source Voltage 600 V
Drain Current - Continuous (TC = 25°C) 1.9 A
- Continuous (T
Drain Current - Pulsed
= 100°C) 1.14 A
C
(Note 1)
7.6 A
Gate-Source Voltage ± 30 V
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
(Note 2)
(Note 1)
(Note 1)
(Note 3)
120 mJ
1.9 A
4.4 mJ
4.5 V/ns
Power Dissipation (TA = 25°C)* 2.5 W
Power Dissipation (T
= 25°C) 44 W
C
- Derate above 25°C 0.35 W/°C
Operating and Storage Temperature Range -55 to +150 °C
Maximum lead temperature for soldering purposes,
300 °C
1/8" from case for 5 seconds
Thermal Characteristics
Symbol Parameter Typ Max Units
R
θJC
R
θJA
R
θJA
* When mounted on the minimum pad size recommended (PCB Mount)
Thermal Resistance, Junction-to-Case -- 2.87 °C/W Thermal Resistance, Junction-to-Ambient* -- 50 °C/W Thermal Resistance, Junction-to-Ambient -- 110 °C/W
©2009 Fairchild Semiconductor Corporation
FQD2N60C/FQU2N60C Rev. B3
1
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Page 2
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FQD2N60C FQD2N60C D-PAK - -
FDU2N60C FDU2N60C I-PAK - -
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
Electrical Characteristics
TC = 25°C unless other wise not ed
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
∆BV ∆T
I
DSS
I
GSSF
I
GSSR
DSS
J
Drain-Source Breakdown Voltage VGS = 0 V, I
/
Breakdown Voltage Temperature
DSS
I
= 250 µA, Referenced to 25°C -- 0.6 -- V/°C
D
Coefficient
Zero Gate Voltage Drain Current VDS = 600 V, V
V
DS
Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA
Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA
On Characteristics
V
GS(th)
R
DS(on)
Gate Threshold Voltage VDS = VGS, I
Static Drain-Source
VGS = 10 V, I
On-Resistance
g
FS
Forward Transconductance VDS = 40 V, ID = 0.95 A
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance VDS = 25 V, VGS = 0 V,
Output Capacitance -- 20 25 pF
f = 1.0 MHz
Reverse Transfer Capacitance -- 4.3 5.6 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn-On Delay Time VDD = 300 V, ID = 2 A,
R
Turn-On Rise Time -- 25 60 ns
G
Turn-Off Delay Time -- 24 58 ns
Turn-Off Fall Time -- 28 66 ns
Total Gate Charge VDS = 480 V, ID = 2 A,
V
Gate-Source Charge -- 1.3 -- nC
GS
Gate-Drain Charge -- 4.1 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 56mH, I
3. I
≤ 2A, di/dt ≤ 200A/µs, VDD ≤ BV
SD
4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%
5. Essentially independent of operating temperature
Maximum Continuous Drain-Source Diode Forward Current -- -- 1.9 A
Maximum Pulsed Drain-Source Diode Forward Current -- -- 7.6 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.9 A -- -- 1.4 V
Reverse Recovery Time VGS = 0 V, IS = 2 A,
dI
Reverse Recovery Charge -- 1.0 -- µC
= 2A, VDD = 50V, R
AS
= 25 Ω, Starting T
G
Starting TJ = 25°C
DSS,
= 25°C
J
F
= 480 V, T
= 25 Ω
= 10 V
/ dt = 100 A/µs
= 250 µA 600 -- -- V
D
= 0 V -- -- 1 µA
GS
= 125°C -- -- 10 µA
C
= 250 µA2.0--4.0V
D
= 0.95 A -- 3.6 4.7 Ω
D
(Note 4)
-- 5.0 -- S
-- 180 235 pF
-- 9 28 ns
(Note 4, 5)
-- 8.5 12 nC
(Note 4, 5)
-- 230 -- ns
(Note 4)
FQD2N60C/FQU2N60C Rev. B3
2
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Page 3
Typical Performance Characterist ics
Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics
-55oC
※
1. VDS = 40V
2. 250µ s Pulse Test
0
10
-1
10
, Drain Current [A]
D
I
-2
10
10
V Top : 15.0 V
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
5.0 V Bottom : 4.5 V
-1
GS
0
10
VDS, Drain-Source Voltage [V]
Notes :
※
1. 250µ s Pulse Test = 25
℃
2. T
C
1
10
1
10
150oC
0
10
25oC
, Drain Current [A]
D
I
-1
10
246810
VGS, Gate-Source Volt age [V]
Figure 3. On-Resistance Variation vs. Figure 4. Body Diode Forward Voltage
Drain Current and Gate Voltage Variation vs. Source Current
and Temperatue
12
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
Notes :
10
8
[Ω ],
6
DS(ON)
R
4
Drain-Source On-Resistance
2
0
012345
ID, Drai n Current [A]
VGS = 10V
※
Note : T
VGS = 20V
= 25
J
0
℃
10
150
, Reverse Drain Current [A]
DR
I
-1
10
0.2 0.4 0.6 0.8 1.0 1.2 1.4
℃
Notes :
※
25
℃
1. VGS = 0V
2. 250µ s Pul se Test
VSD, Source-Drain voltage [V]
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
500
450
400
350
300
250
200
150
Capacitance [pF]
100
50
0
C
= Cgs + Cgd (Cds = shorted)
iss
C
= Cds + C
oss
gd
C
= C
rss
gd
C
iss
C
oss
Notes ;
※
C
rss
-1
10
0
10
1. VGS = 0 V
2. f = 1 MHz
1
10
VDS, Drain- Source Voltage [V]
12
10
VDS = 300V
8
6
4
, Gate-Source Voltage [V]
GS
2
V
0
0246810
VDS = 480V
QG, Total Gate Charge [nC]
VDS = 120V
※
Note : I
= 2A
D
FQD2N60C/FQU2N60C Rev. B3
3
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Page 4
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
Typical Performance Characterist ics
(Continued)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
1.2
1.1
1.0
, (Normalized)
DSS
BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
Not es :
※
1. VGS = 0 V
2. I
= 250 µ A
D
TJ, Junct ion Temperat ure [oC]
3.0
2.5
2.0
1.5
, (Normalized)
1.0
DS(ON)
R
Drain-Source On-Resistance
0.5
0.0
-100 -50 0 50 100 150 200
TJ, Junct ion Temperature [oC]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
1
10
Operation in This Area is Limited by R
DS(on)
2.0
1.6
100 µs
DC
100 ms
2
10
10 ms
1 ms
3
10
0
10
-1
, Drain Current [A]
10
D
I
-2
10
0
10
1
10
Notes :
※
1. TC = 25 oC
2. T
= 150 oC
J
3. Single Pulse
VDS, Drain-Source Voltage [V]
1.2
0.8
, Drain Current [A]
D
I
0.4
0.0 25 50 75 100 125 150
TC, Case Temperature [ ]
Notes :
※
1. VGS = 10 V
2. I
= 0.95 A
D
℃
Figure 11. Typical Drain Current Slope Figure 12. Typical Drain-Source Voltage
vs. Gate Resistance Slope vs. Gate Resistance
(t), Thermal Response
Z
FQD2N60C/FQU2N60C Rev. B3
D=0.5
0
10
0.2
0.1
0.05
0.02
-1
10
0.01
θ JC
-5
10
single pulse
-4
10
-3
10
-2
10
Notes :
※
1. Z
(t) = 2.87 /W Max.
θ JC
2. Du ty Fa ctor, D =t1/t
3. TJM - TC = PDM * Z
P
DM
-1
10
℃
t
1
t
2
10
2
(t)
θ JC
0
1
10
t1, Square Wave P ulse Duration [sec]
4
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Page 5
12V
12V
200nF
200nF
3mA
3mA
50KΩ
50KΩ
V
V
Gate Charge Test Circuit & Waveform
V
V
GS
GS
GS
300nF
300nF
Same Type
Same Type
as DUT
as DUT
DUT
DUT
V
V
DS
DS
GS
10V
10V
Resistive Switching Test Circuit & Waveforms
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
Q
Q
g
g
Q
Q
gs
gs
Q
Q
gd
gd
Charge
Charge
10V
10V
10V
10V
R
R
L
DUT
DUT
L
V
V
DD
DD
V
V
DS
DS
V
V
GS
GS
R
R
G
G
V
V
DS
DS
90%
90%
10%
10%
V
V
GS
GS
t
t
d(on)tr
d(on)tr
t
t
on
on
t
t
d(off)
d(off)
t
t
f
f
t
t
off
off
Unclamped Inductive Switching Test Circuit & Waveforms
BV
BV
DSS
L
LL
V
V
DS
DS
BV
BV
DSS
V
V
DSS
I
I
AS
AS
DD
DD
I
IDI
D
D
R
R
G
G
DUT
DUT
t
t
p
p
V
V
DD
DD
1
1
1
1
----
----
----
----
E
=LI
E
=LI
=LI
E
AS
AS
AS
2
2
2
2
2
2
2
AS
AS
AS
I
I
(t)
(t)
D
D
t
t
p
p
DSS
--------------------
-------------------­BV
BV
DSS-VDD
DSS-VDD
Time
Time
V
(t)
V
(t)
DS
DS
FQD2N60C/FQU2N60C Rev. B3
5
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Page 6
Peak Diode Recovery dv/dt Test Circuit & Waveforms
+
DUT
DUT
I
I
SD
SD
Driver
Driver
R
R
G
G
V
V
GS
GS
+
V
V
DS
DS
_
_
L
LL
Same Type
Same Type
as DUT
as DUT
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontrolled by pulse period
•ISDcontrolled by pulse period
G
G
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
V
V
DD
DD
V
V
GS
GS
( Driver )
( Driver )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
Gate Pulse Width
Gate Pulse Width
Gate Pulse Width
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, Body Diode Forward Current
IFM, Body Diode Forward Current
I
I
RM
RM
Body Diode Reverse Current
Body Diode Reverse Current
Body Diode Recovery dv/dt
Body Diode Recovery dv/dt
V
V
SD
SD
Body Diode
Body Diode
Forward Voltage Drop
Forward Voltage Drop
di/dt
di/dt
10V
10V
V
V
DD
DD
FQD2N60C/FQU2N60C Rev. B3
6
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Page 7
Mechanical Dimensions
TO-252 (DPAK) (FS PKG Code 36)
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
millimeters
Part Weight per unit (gram): 0.33
FQD2N60C/FQU2N60C Rev. B3
7
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Page 8
Mechanical Dimensions
FQD2N60C/FQU2N60C 600V N-Channel MOSFET
I - PAK
FQD2N60C/FQU2N60C Rev. B3
Dimensions in Millimeters
8
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Page 9
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tm
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®
*
®
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* EZSWITCH™ and FlashWriter
®
are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
®
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®
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tm
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Programmable Active Droop™
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Saving our world, 1mW /W /kW at a time™ SmartMax™ SMART START™
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FQD2N60C/FQU2N60C 600V N-Channel MOSFET
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
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.
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PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
FQD2N60C/FQU2N60C Rev. B3
Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I37
9
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