Datasheet FDMS7606 Datasheet (Fairchild)

FDMS7606

Power 56

S2

S2

S2

G2

D1

D1

D1

G1

D1

S1/D2

Top

Bottom

Pin1

S2

S2

S2

G2

D1

D1

D1

G1

4

3

2

1

5

6

7

8

Q2

Q1

Dual N-Channel PowerTrench® MOSFET

Q1: 30 V, 12 A, 11.4 mΩ Q2: 30 V, 22 A, 11.6 mΩ

FDMS7606 Dual N-Channel PowerTrench

May 2011

Features

Q1: N-Channel

 Max r
 Max r

Q2: N-Channel

 Max r
 Max r

 RoHS Compliant

= 11.4 mΩ at VGS = 10 V, ID = 11.5 A

DS(on)

= 15.7 mΩ at VGS = 4.5 V, ID = 10 A

DS(on)

= 11.6 mΩ at VGS = 10 V, ID = 12 A

DS(on)

= 17.2 mΩ at VGS = 4.5 V, ID = 9.5 A

DS(on)

General Description

This device includes two specialized N-Channel MOSFETs in a
dual MLP package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
MOSFET (Q2) have been designed to provide optimal power
efficiency.

Applications

 Computing
 Communications
 General Purpose Point of Load
 Notebook Charger

®

MOSFET

MOSFET Maximum Ratings T

Symbol Parameter Q1 Q2 Units

V

DS

V

GS

I

D

E

AS

P

D

TJ, T

STG

Drain to Source Voltage 30 30 V
Gate to Source Voltage (Note 3) ±20 ±20 V
Drain Current -Continuous (Package limited) TC = 25 °C 12 22

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 50 60
Single Pulse Avalanche Energy (Note 4) 25 33 mJ
Power Dissipation for Single Operation TA = 25°C 2.2
Power Dissipation for Single Operation T
Operating and Storage Junction Temperature Range -55 to +150 °C

= 25°C unless otherwise noted

A

= 25 °C 41 39

C

= 25 °C 11.5

A

= 25°C 1.0

A

1a

1a
1c

12

2.5

1.0

1b

1b
1d

A

W

Thermal Characteristics

R

θJA
θJA

R

θJC

Package Marking and Ordering Information

©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDMS7606 Rev.C

Device Marking Device Package Reel Size Tape Width Quantity

FDMS7606 FDMS7606 Power 56 13 ” 12

Thermal Resistance, Junction to Ambient 57
Thermal Resistance, Junction to Ambient 125
Thermal Resistance, Junction to Case 4.6 4.7

1a

1c

mm 3000 units

50

120

1b

1d

°C/WR

FDMS7606 Dual N-Channel PowerTrench

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Off Characteristics

BV

ΔBV
ΔT

I

DSS

I

GSS

DSS

DSS
J

Drain to Source Breakdown Voltage I
Breakdown Voltage Temperature

Coefficient
Zero Gate Voltage Drain Current V

Gate to Source Leakage Curent

= 250 μA, VGS = 0 V

D

I

= 250 μA, referenced to 25°C

D

= 24 V, V

DS

V

= 20 V, V

GS

V

= ±20 V, V

GS

= 0 V

GS

= 0 V

DS

= 0 V

DS

Q1Q230

30

Q1
Q2

Q1
Q2

Q1
Q2

V

16
20

±100

mV/°C

1
1

100

On Characteristics

V

GS(th)

ΔV
ΔT

r

DS(on)

g

FS

GS(th)

J

Gate to Source Threshold Voltage VGS = VDS, I
Gate to Source Threshold Voltage

Temperature Coefficient

Static Drain to Source On Resistance

Forward Transconductance

I

= 250 μA, referenced to 25°C

D

= 10 V, ID = 11.5 A

V

GS

V

= 4.5 V, ID = 10 A

GS

V

= 10 V, ID = 11.5 A, T

GS

V

= 10 V, ID = 12 A

GS

V

= 4.5 V, I= 9.5 A

GS

V

= 10 V, ID = 12 A, T

GS

V

= 5 V, ID = 11.5 A

DD

V

= 5 V, ID = 12 A

DD

= 250 μA

D

= 125°C

J

= 125°C

J

Q1Q21.0

Q1
Q2

Q1

Q2

Q1
Q2

1.0

2.1

1.9

-6

-5.5

9.2

12.6

11.8

9.7

12.8

12.3
53

47

3.0

3.0
mV/°C

11.4

15.7

14.7

11.6

17.2

15.4

μA

nA

V

mΩ

S

®

MOSFET

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

Gate Resistance

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q

Q

Q

Q

g(TOT)

g(TOT)

gs

gd

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

Total Gate Charge V

Total Gate Charge V

Gate to Source Charge

Gate to Drain “Miller” Charge

1050

Q1:

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q2:

= 15 V, VGS = 0 V, f = 1 MHZ

V

DS

Q1
Q2

Q1
Q2

Q1
Q2

Q1Q20 . 2

0.2

1400

947

1260

295

395

191

255

32

13150200

1.6

4 . 0

1.0

2.5

pF

pF

pF

Ω

7

18
19

16
19

10

14
12

10
10

33
34

10
10

22
27

11
15

ns

ns

ns

ns

nC

nC

6
3

3

3
3

8

nC

nC

Q1
V

= 15 V, ID = 11.5 A, R

DD

Q2
V

= 15 V, ID = 12 A, R

DD

= 0V to 10 V

GS

= 0V to 5 V

GS

GEN

Q1
V

= 15 V,

DD

I

= 11.5 A

D

Q2
V

= 15 V,

DD

I

= 12 A

D

GEN

= 6 Ω

= 6 Ω

Q1
Q2

Q1
Q2

Q1
Q2

Q1
Q2

Q1
Q2

Q1
Q2

Q1
Q2

Q1
Q2

3.2

2.6

2.0

4.2

©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDMS7606 Rev.C

Electrical Characteristics T

= 25°C unless otherwise noted

J

Symbol Parameter Test Conditions Type Min Typ Max Units

Drain-Source Diode Characteristics

22
18

7
6

1.2

1.2

1.2

1.2

35
33

13
12

is determined by

θCA

V

= 0 V, IS = 2 A (Note 2)

GS

V

= 0 V, IS = 11.5 A (Note 2)

V

SD

t

rr

Q

rr

Notes:

1.R

is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. bo ard of FR-4 material. R

θJA

the user's board design.

Source-Drain Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

GS

V

= 0 V, IS = 2 A (Note 2)

GS

V

= 0 V, IS = 12 A (Note 2)

GS

Q1

= 11.5 A, di/dt = 100 A/s

I

F

Q2
I

= 12 A, di/dt = 100 A/s

F

Q1
Q1
Q2
Q2

0.76

0.87

0.75

0.85

Q1
Q2

Q1
Q2

is guaranteed by design while R

θJC

FDMS7606 Dual N-Channel PowerTrench

V

ns

nC

a. 57 °C/W when mounted on

2

a 1 in

pad of 2 oz copper

c. 125 °C/W when mounted on a
minimum pad of 2 oz copper

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied

4. Q1: E
Q2: E

of 25 mJ is based on starting TJ = 25 oC, L = 0.3 mH, IAS = 13 A, VDD = 27 V, VGS = 10 V.

AS

of 33 mJ is based on starting TJ = 25 oC, L = 0.3 mH, IAS = 15 A, VDD = 27 V, VGS = 10 V.

AS

b. 50 °C/W when mounted on
a 1 in

d. 120 °C/W when mounted on a
minimum pad of 2 oz copper

2

pad of 2 oz copper

®

MOSFET

©2011 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com
FDMS7606 Rev.C

FDMS7606 Dual N-Channel PowerTrench

0.00.51.01.52.0

0

10

20

30

40

50

V

GS

= 6 V

V

GS

= 4 V

V

GS

= 10 V

V

GS

= 4.5 V

V

GS

= 3.5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 1020304050

0

1

2

3

4

5

VGS = 6 V

VGS = 3.5 V

PULSE DURA TION = 80 μs
DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTA NCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 11.5 A
V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

8

16

24

32

TJ = 125 oC

ID = 11.5 A

TJ = 25 oC

V

GS

, GATE TO S O URCE VOLTAGE (V )

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

1.5 2.0 2.5 3.0 3.5 4.0 4.5

0

10

20

30

40

50

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001

0.01

0.1

1

10

50

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q1 N-Channel) T

Figure 1.

On Region Characteristics Figure 2.

= 25°C unless otherwise noted

J

Nor mali zed O n-R esis tanc e

vs Drain Current and Gate Voltage

®

MOSFET

Figur e 3. No rma liz ed On R esist anc e

vs Junction Temperature

©2011 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com
FDMS7606 Rev.C

Figure 5. Transfer Characteristics

Figure 4.

On-Resi stance v s Gate to

Source Voltage

Figure 6.

Source t o Drain Diode

Forward Voltage vs Source Current

FDMS7606 Dual N-Channel PowerTrench

0 3 6 9 12 15 18

0

2

4

6

8

10

ID = 11.5 A

V

DD

= 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

10

100

1000

2000

f = 1 MHz
V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTA G E (V)

C

rss

C

oss

C

iss

0.001 0.01 0.1 1 10 40

1

10

20

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

10

20

30

40

50

R

θJC

= 4.6 oC/W

V

GS

= 4.5 V

Limited by Package

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 100200

0.01

0.1

1

10

60

100 μs

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY r

DS(on)

SINGLE PULSE
T

J

= MAX RATED

R

θJA

= 125

o

C/W

T

A

= 25

o

C

10s

10-410-310-210

-1

110

100 1000

0.5

1

10

100

500

SINGLE PULSE
R

θJA

= 125 oC/W

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q1 N-Channel) T

Figure 7.

Gate Charge Characteristics Figure 8.

= 25°C unless otherwise noted

J

Cap a cita n ce v s Drai n

to Source Voltage

®

MOSFET

Figure 9.

Uncl a m ped I n ducti v e

Switching Capability

©2011 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com
FDMS7606 Rev.C

Figure 11. Forward Bias Safe

Op

erating Area

Figure 10.

Ma ximum Continuous Dr ai n

Current vs Case Temperature

Figure 12.

Si ngle Pulse Maximum

Power Dissipation

FDMS7606 Dual N-Channel PowerTrench

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

2

SINGLE PULSE
R

θJA

= 125 oC/W

(Note 1c)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PU L SE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t1/t

2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

Typical Characteristics (Q1 N-Channel) T

Figure 13.

Junction-to-Ambient Transient Thermal Response Curve

= 25°C unless otherwise noted

J

®

MOSFET

©2011 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com
FDMS7606 Rev.C

FDMS7606 Dual N-Channel PowerTrench

0.00.51.01.52.0

0

10

20

30

40

50

60

V

GS

= 4 V

V

GS

= 6 V

V

GS

= 10 V

V

GS

= 4.5 V

V

GS

= 3.5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

I

D

, DRAIN CURRENT (A)

V

DS

, DRAIN TO SOURCE VOLTAGE (V)

0 102030405060

0

1

2

3

4

5

VGS = 6 V

VGS = 3.5 V

PULSE DURA TION = 80 μs
DUTY CYCLE = 0.5% MAX

NORMALIZED

DRAIN TO SOURCE ON-RESISTANCE

I

D

, DRAIN CURRENT (A)

V

GS

= 4 V

VGS = 4.5 V

V

GS

= 10 V

-75 -50 -25 0 25 50 75 100 125 150

0.6

0.8

1.0

1.2

1.4

1.6

ID = 12 A
V

GS

= 10 V

NORMALIZED

DRAIN TO SOURCE ON-RESI ST ANCE

T

J

, JUNCTION TEMPERATURE (

o

C)

246810

4

8

12

16

20

24

28

32

36

40

TJ = 125 oC

ID = 12 A

TJ = 25 oC

V

GS

, GATE TO SOURCE VOLTA GE (V)

r

DS(on)

,

DRAIN TO

SOURCE ON-RESISTANCE

(mΩ)

PULSE DURA TION = 80 μs
DUTY CYCLE = 0.5% MAX

12345

0

10

20

30

40

50

60

TJ = 150 oC

V

DS

= 5 V

PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I

D

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.01

0.1

1

10

100

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

V

GS

= 0 V

I

S

, REVERSE DRAIN CURRENT (A)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q2 N-Channel) T

Figure 14.

On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain

= 25 °C unless otherwise noted

J

Current and Gate V oltage

®

MOSFET

Figure 16. Normalized On-Resistance

vs Junction Temperature

©2011 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com
FDMS7606 Rev.C

Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode

Figure 17. On-Resistance vs Gate to

Source Voltage

Forward Voltage vs Source Current

FDMS7606 Dual N-Channel PowerTrench

0 5 10 15 20

0

2

4

6

8

10

ID = 12 A

V

DD

= 20 V

V

DD

= 10 V

V

GS

, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 30

50

100

1000

2000

f = 1 MHz
V

GS

= 0 V

CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

rss

C

oss

C

iss

0.001 0.01 0.1 1 10 40

1

10

30

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I

AS

, AVALANCHE CURRENT (A)

25 50 75 100 125 150

0

10

20

30

40

Limited by Package

R

θJC

= 4.7 oC/W

V

GS

= 4.5 V

V

GS

= 10 V

I

D

, DRAIN CURRENT (A)

T

C

, CASE TEMPERATURE (

o

C)

0.01 0.1 1 10 100200

0.01

0.1

1

10

70

100 μs

DC

100 ms

10 ms

1 ms

1s

I

D

, DRAIN CURRENT (A)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY r

DS(on)

SINGLE PULSE
T

J

= MAX RA TED

R

θJA

= 120

o

C/W

T

A

= 25

o

C

10s

10-410-310-210-1110

100 1000

0.5

1

10

100

500

SINGLE PULSE
R

θJA

= 120 oC/W

P(

PK

), PEAK TRANSIENT POWER (W)

t, PULSE WIDTH (sec)

Typical Characteristics (Q2 N-Channel) T

Figure 20. Gate Charge Characteristics

= 25°C unless otherwise noted

J

Figure 21. Capacitance vs Drain

to Source Voltage

®

MOSFET

Figure 22. Unclamped Inductive

Switching Capability

©2011 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com

FDMS7606 Rev.C

Fi gure 24. Forward Bias Safe

Operating Area

Fig ure 23. Max imum Cont inu ous Dra in

Current vs Case Temperature

Figure 25. Single Pulse Maximum Power

Dissipation

10

-4

10

-3

10

-2

10

-1

110

100 1000

0.001

0.01

0.1

1

2

SINGLE PULSE
R

θJA

= 120 oC/W

(Note 1d)

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE,

Z

θJA

t, RECTANGULAR PU L SE DURATION (sec)

D = 0.5

0.2

0.1

0.05

0.02

0.01

P

DM

t

1

t

2

NOTES:
DUTY FACTOR: D = t

1/t2

PEAK TJ = PDM x Z

θJA

x R

θJA

+ T

A

FDMS7606 Dual N-Channel PowerTrench

Typical Characteristics (Q2 N-Channel) T

Figure 26. Junction-to-Ambient Transient Thermal Response Curve

= 25 °C unless otherwise noted

J

®

MOSFET

©2011 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com

FDMS7606 Rev.C

6.30

0.63

1.27

1.27

(OPTION 2 - ISOLATED LEADS)

(OPTION 1 - FUSED LEADS 5,6,7)

0.20

0.340 4X

RECOMMENDED LA ND PATTERN

2.67

4.00

0.65 TY P

12 3 4

5

6 7 8

0.92

0.66

0.54

0.40

0.65 (5X)

0.63

3.81

1.27

6.0

5.0

PIN#1 QUADRANT

0.80 MAX

0.25 0

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER

E. DRAWING FILE NAME : MKT-MLP08Prev1

A. DOES NOT FULLY CONFORM TO

JEDEC REGISTRATION, MO-229.

ASME Y14.5M, 1994

TOP VIEW

BOTTOM VIEW

RECOMMENDED LA ND PATTERN

0.08 C

B

A

0.10 C

2X

0.10 C

2X

SIDE VIEW

(0.20)

SEATING
PLA NE

0.10 C A B

0.10 C

12

3

4

5 6 7 8

6.30

2.67

4.00

0.65 TY P

PIN #1 IDENT

0.05 C

1

2

3

4

5

6 7 8

0.05

0.00

2.72

2.62

3.85

3.75

0.48

0.38

(5X)

0.97

0.87

0.56

0.46

(5X)

0.92

0.66

0.66

0.55

0.54

0.40

0.45

D. L AND PATTERN RECOMMENDATION IS

BASED ON FSC DESIGN ONLY

Dimensional Outline and Pad Layout

FDMS7606 Dual N-Channel PowerTrench

®

MOSFET

©2011 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com

FDMS7606 Rev.C

TRADEMARKS

tm

®

tm

tm

The following includes registered and unregistered trademarks and se rvice marks, owned by Fairchild Semiconductor and/o r its global subsidia ries, and is not
intended to be an exhaustive list of all such trademarks.

AccuPower™
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®

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EfficentMax™
ESBC™

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®

®

®

®

®

®

*

®

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®

FRFET
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Motion-SPM™
mWSaver™
OptiHiT™
OPTOLOGIC
OPTOPLANAR

®

®

®

PDP SPM™

Power-SPM™
PowerTrench
PowerXS™

SM

Programmable Active Droop™
QFET
QS™
Quiet Series™
RapidConfigure™

Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
SMART START™
SPM
STEALTH™
SuperFET
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS
SyncFET™
Sync-Lock™
®*

®

®

™

®

®

®

The Power Franchise
The Right Technology for Your Success™

®

TinyBoost™
TinyBuck™
TinyCalc™

®

TinyLogic
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™

®

TranSiC
TriFault Detect™
TRUECURRENT
μSerDes™

®

UHC
Ultra FRFET™
UniFET™
VCX™
VisualMax™
XS™

®

®

*

FDMS7606 Dual N-Channel PowerTrench

®

MOSFET

*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used here in:

1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufact ures of semiconductor products are experiencin g counterfeiting of their

parts. Customers who inadvertently purchase counterfe it parts e xp erien ce many prob lems such a s loss of b rand rep utati on, substa nda rd perf orman ce, fa iled
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to prot ect oursel ve s and our customers from the
proliferation of counterfeit parts. Fairch ild strongly encourage s cust omers to purch ase Fair chil d parts either dire ctly from Fairchild or from Author ized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is
committed to combat this global problem and encourage o ur customers to do their part in stopping this practice b y buying direct or from authorized dist ributors.

PRODUCT STATUS DEFINITIONS
Definition of Terms

.

2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.

Datasheet Identification Product Status Definition

Advance Information Formative / In Design

Preliminary First Production

No Identification Needed Full Production

Obsolete Not In Production

Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.

Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time withou t
notice to improve design.

Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.

Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.

Rev. I54

©2011 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com

FDMS7606 Rev.C