Datasheet FDC87W22 Datasheet (Standard Microsystems Corporation)

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Page 1

FDC87W22

Power I/O Controller

FEATURES

• 5 Volt Operation

• Floppy Disk Controller (FDC)

- Compatible with IBM PC/AT Disk Drive Systems

- Variable Write Pre-Compensation with Track Selectable Capability

- DMA Enable Logic

- Non-Burst Mode DMA Option

- Supports Floppy Disk Drives and Tape

Drives

- Detects All Overrun and Underrun Conditions

- Data Rate and Drive Control Registers

- Built-in Address Mark Detection Circuit to

Simplify the Read Electronics

- IBM PC System Address Decoder

- Supports up to Two Embedded Hard

Disk Drives (IDE AT BUS)

- Single 24 MHz Crystal Input

- FDD Anti-Virus Functions With Software

Write Protect and FDD Write Enable Signal, Write Data Signal Force Inactive

- Supports up to Four 3.5-Inch or 5.25Inch Floppy Disk Drives

- Completely Compatible with Industry Standard 82077

- 360Kbps/720K/1.2M/1.44M/2.88M Format

- 250Kbps, 300Kbps, 500Kbps, 1 Mbps Data Transfer Rate

- Supports Vertical Recording Format

- 16-Byte Data FIFOs

• Serial Ports

- Two High-speed 16550 Compatible UARTs with 16-Byte Send/Receive FIFOs

- MIDI Compatible

- Fully Programmable Serial-Interface

Characteristics:

- 5, 6, 7 or 8-Bit Characters

- Even, Odd or No Parity Bit

Generation/Detection

- 1, 1.5 or 2 Stop Bits Generation

- Internal Diagnostic Capabilities:

- Loop-Back Controls for

Communications Link Fault Isolation

- Break, Parity, Overrun, Framing Error Simulation

- Programmable Baud Generator Allows Division of 1.8461 MHz and 24 MHz by 1 to (216-1)

• Parallel Port

- Compatible with IBM Parallel Port

- Supports Parallel Port with Bidirectional

Lines

- Supports Enhanced Parallel Port (EPP)

- Compatible with IEEE 1284

Specification

- Supports Extended Capabilities Port (ECP)

- Compatible with IEEE 1284 Specification

- Extension FDD Mode Supports Disk Drive B Through Parallel Port

- Extension Adapter Mode Supports Pocket Devices Through Parallel Port

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- Extension 2FDD Mode Supports Disk Drives A And B Through Parallel Port

- JOYSTICK Mode Supports Joystick Through Parallel Port

• Programmable Configuration Settings

• Immediate or Automatic Power-Down Mode

for Power Management

• ISA Host Interface

• All Hardware Power-On Settings Have

Internal Pull-Up or Pull-Down Resistors as Default Value

• Configurable Plug and Play Registers

• Infrared Communication Port

• 100 Pin QFP Package

GENERAL DESCRIPTION

The FDC87W22 integrates a disk drive adapter, serial port (UART), parallel port, IDE bus interface, and game port decoder onto a single chip. The FDC87W22 also has additional powerful features such as configurable plugand-play registers for the whole chip and infrared support in one of the serial ports.

The disk drive adapter functions of the FDC87W22 include a floppy disk drive controller compatible with the industry standard 82077/765 data separator, write precompensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated into the FDC87W22 greatly reduces the number of components required for interfacing with floppy disk drives. The FDC87W22 supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/S, 300 Kb/S, 500 Kb/S, and 1 Mb/S.

The FDC87W22 provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system.

The FDC87W22 supports one PC-compatible printer port. Additional bidirectional I/O

capability is available by hardware control or software programming. The parallel port also supports the Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). The FDC87W22 supports two embedded hard disk drive (AT bus) interfaces and a game port with decoded read/write output. The chip's Extension FDD Mode and Extension 2FDD Mode allow one or two external floppy disk drives to be connected to the computer through the printer interface pins in notebook computer applications.

The Extension Adapter Mode of the FDC87W22 allows pocket devices to be installed through the printer interface pins in notebook computer applications according to a protocol set by SMSC, but with upgraded performance. The JOYSTICK mode allows a joystick to be connected to a parallel port with a signal switching cable. The configuration registers support mode selection, function enable/disable, and power down function selection. Moreover, the configurable PnP registers are compatible with the plug-and-play feature in Windows 95TM, which makes system resource allocation more efficient than ever.

Standard Microsystems is a registered trademark and SMSC is a trademark of Standard Microsystems Corporation. Other product and company names are trademarks or registered trademarks of their respective holders.

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TABLE OF CONTENTS

FEATURES....................................................................................................................................... 1

GENERAL DESCRIPTION ................................................................................................................ 2

PIN CONFIGURATION...................................................................................................................... 5

PIN DESCRIPTION .......................................................................................................................... 6

HOST INTERFACE.............................................................................................................................. 6

SERIAL PORT INTERFACE ................................................................................................................... 7

GAME PORT/POWER DOWN INTERFACE...............................................................................................9

MULTI-MODE PARALLEL PORT .......................................................................................................... 10

IDE AND FDC INTERFACE ............................................................................................................... 18

FDC FUNCTIONAL DESCRIPTION................................................................................................. 20

FDC87W22 FDC.......................................................................................................................... 20

AT INTERFACE............................................................................................................................... 20

FIFO (DATA)................................................................................................................................. 20

DATA SEPARATOR .......................................................................................................................... 21

WRITE PRECOMPENSATION .............................................................................................................. 21

PERPENDICULAR RECORDING MODE .................................................................................................. 21

FDC CORE ................................................................................................................................... 22

FDC COMMANDS............................................................................................................................ 23

REGISTER DESCRIPTIONS................................................................................................................. 32

STATUS REGISTER A (SA REGISTER) (READ BASE ADDRESS + 0).......................................................... 33

STATUS REGISTER B (SB REGISTER) (READ BASE ADDRESS + 1).......................................................... 35

DIGITAL OUTPUT REGISTER (DO REGISTER) (WRITE BASE ADDRESS + 2)............................................... 37

TAPE DRIVE REGISTER (TD REGISTER) (READ BASE ADDRESS + 3)........................................................ 37

MAIN STATUS REGISTER (MS REGISTER) (READ BASE ADDRESS + 4)..................................................... 38

DATA RATE REGISTER (DR REGISTER) (WRITE BASE ADDRESS + 4) ...................................................... 39

FIFO REGISTER (R/W BASE ADDRESS + 5) ........................................................................................ 40

STATUS REGISTER 0 (ST0).............................................................................................................. 41

STATUS REGISTER 1 (ST1).............................................................................................................. 41

STATUS REGISTER 2 (ST2).............................................................................................................. 42

STATUS REGISTER 3 (ST3).............................................................................................................. 42

DIGITAL INPUT REGISTER (DI REGISTER) (READ BASE ADDRESS + 7) ...................................................... 42

CONFIGURATION CONTROL REGISTER (CC REGISTER) (WRITE BASE ADDRESS + 7) ................................. 44

IDE.................................................................................................................................................. 45

IDE DECODE DESCRIPTION..............................................................................................................45

UART PORT ................................................................................................................................... 46

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)............................................ 46

UART CONTROL REGISTER (UCR) (READ/WRITE).............................................................................49

UART STATUS REGISTER (USR) (READ/WRITE)................................................................................ 50

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HANDSHAKE CONTROL REGISTER (HCR) (READ/WRITE)...................................................................... 51

HANDSHAKE STATUS REGISTER (HSR) (READ/WRITE) ........................................................................ 52

UART FIFO CONTROL REGISTER (UFR) (WRITE ONLY)..................................................................... 53

INTERRUPT STATUS REGISTER (ISR) (READ ONLY).............................................................................. 54

INTERRUPT CONTROL REGISTER (ICR) (READ/WRITE) ........................................................................ 56

PROGRAMMABLE BAUD GENERATOR (BLL/BHL) (READ/WRITE)............................................................ 56

USER-DEFINED REGISTER (UDR) (READ/WRITE) ................................................................................ 57

PARALLEL PORT.......................................................................................................................... 58

PRINTER INTERFACE LOGIC .............................................................................................................. 58

ENHANCED PARALLEL PORT (EPP)................................................................................................... 61

DATA SWAPPER ............................................................................................................................. 61

PRINTER STATUS BUFFER................................................................................................................61

PRINTER CONTROL LATCH AND PRINTER CONTROL SWAPPER ............................................................... 62

EPP ADDRESS PORT......................................................................................................................63

EPP DATA PORT 0-3...................................................................................................................... 63

EPP OPERATION............................................................................................................................ 65

EXTENDED CAPABILITIES PARALLEL (ECP) PORT................................................................................. 65

EXTENSION FDD MODE (EXTFDD)..................................................................................................74

EXTENSION 2FDD MODE (EXT2FDD).............................................................................................. 74

SPECIFICATIONS..........................................................................................................................116

ABSOLUTE MAXIMUM RATINGS.................................................................................................116

DC CHARACTERISTICS................................................................................................................116

AC CHARACTERISTICS................................................................................................................118

TIMING WAVEFORMS ..................................................................................................................124

APPLICATION CIRCUITS..............................................................................................................136

PACKAGE DIMENSIONS ..............................................................................................................139

80 Arkay Drive Hauppauge, NY 11788 (516) 435-6000 FAX (516) 273-3123

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PIN CONFIGURATION

81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

nINDEX

nSTEP

nDSA nDSB

nWE nWD

nRWC

nHEAD

nDIR GND

nIDBEN

IRQ_B

nIRQIN

nCS0 nCS1

IRQ_A

nDACK_B

IRQ_F

DRQ_B

nMOB

nMOA

nTRAK0

NWP

nDSKCHG

A10

nRDATAD7D6D5D4D3D2D1D0

GND

nIOW

nIOR

AENA9A8A7A6A5VDDA4A3A2A1

8079787776757473727170696867666564636261605958575655545352

nRIB nDCDB nDSRB nCTSB nDTRB nRTSB IRQ_C SOUTB SINB nGMRD GND nGMWR SOUTA IRQ_D nRTSA nDTRA nCTSA nDSRA nDCDA nRIA

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

1234567891011121314151617181920212223242526272829

nRESIDE

nCS

nPDCIN

DRQ_C

IOCHRDY

XTAL1

XTAL2

PD0

PD1

PD2

PD3

PD4

PD5

VDD

PD6

PD7

nDACK_C

nSTB

nAFD

nINIT

nSLIN

IRQ_E

BUSY

GND

nACK

SLCT

nERR

SINA

FDC87W22

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PIN DESCRIPTION

I/O8t TTL level bidirectional pin with 8 mA source-sink capability I/O12t TTL level bidirectional pin with 12 mA source-sink capability I/O24t TTL level bidirectional pin with 24 mA source-sink capability

OUT8t TTL level output pin with 8 mA source-sink capability

OUT12t TTL level output pin with 12 mA source-sink capability

OD12 Open-drain output pin with 12 mA sink capability OD24 Open-drain output pin with 24 mA sink capability

INt TTL level input pin

INc CMOS level input pin

INcs CMOS level schmitt-triggered input pin

Note: Refer to DC CHARACTERISTICS section for details.

Host Interface

SYMBOL PIN I/O FUNCTION

D0−D7

66-73 I/O

24t

System data bus bits 0-7

A0−A9

51-55 57-61

System address bus bits 0-9

A10 75 IN

In ECP Mode, this pin is the A10 address input.

IOCHRDY 5 OD

In EPP Mode, this pin is the IO Channel Ready output to extend the host read/write cycle.

MR 6 IN

Master Reset. Active high. MR is low during normal operations.

nCS 2 IN

Active low chip select signal

AEN 62 IN

System address bus enable

nIOR 63 IN

CPU I/O read signal

nIOW 64 IN

CPU I/O write signal

DRQ_B 100 OUT

12t

DMA request signal B

nDACK_B 98 IN

DMA Acknowledge signal B

DRQ_C 4 OUT

12t

DMA request signal C

nDACK_C 18 IN

DMA Acknowledge signal C

TC 97 IN

Terminal Count. When active, this pin indicates termination of a DMA transfer.

nIRQIN 93 IN

Interrupt request input IRQ_A/ GIO1

96 OUT

12t

I/O

12t

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port

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SYMBOL PIN I/O FUNCTION

IRQ_B/ GIO0

92 OUT

12t

I/O

12t

When CR16 Bit 4 (GOIQSEL) = 0: Interrupt request signal

When CR16 Bit 4 (GOIQSEL) = 1: General Purpose I/O port

IRQ_C 44 OUT

12t

Interrupt request signal C IRQ_D 37 OUT

12t

Interrupt request signal D IRQ_E 23 OUT

12t

Interrupt request signal E IRQ_F 99 OUT

12t

Interrupt request signal F XTAL1 7 IN

XTAL oscillator input XTAL2 8 OUT

XTAL oscillator output

Serial Port Interface

SYMBOL PIN I/O FUNCTION

nCTSA nCTSA

34 47

Clear To Send is the modem control input.

The function of these pins can be tested by reading Bit 4 of

the handshake status register. nDSRA

nDSRB

33 48

Data Set Ready. An active low indicates the modem or data

set is ready to establish a communication link and transfer

data to the UART. nDCDA nDCDB

32 49

Data Carrier Detect. An active low indicates the modem or

data set has detected a data carrier. nRIA

nRIB

31 50

Ring Indicator. An active low indicates that a ring signal is

being received by the modem or data set. SINA

SINB/IRRX1

30 42

Serial Input. Used to receive serial data from the

communication link. SOUTA/

PIRIDE

38 I/O

UART A Serial Output. Used to transmit serial data out to

the communication link.

During power-on reset, this pin is pulled up internally and is

defined as PIRIDE, which provides the power-on value for

CR16 bit 1 (IRIDE). A 47 kΩ is recommended when intends

to pull down at power-on reset. SOUTB/ IRTX1/ PGMDRQ

43 I/O

UART B Serial Output. Used to transmit serial data out to

the communication link.

During power-on reset, this pin is pulled up internally and is

defined as PGMDRQ, which provides the power-on value for

CR16 bit 3 (GMDRQ). A 47 kΩ is recommended when

intends to pull down at power-on reset.

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SYMBOL PIN I/O FUNCTION

nDTRA PHEFRAS

35 I/O

UART A Data Terminal Ready. An active low informs the

modem or data set that the controller is ready to

communicate.

During power-on reset, this pin is pulled down internally and

is defined as PHEFRAS, which provides the power-on value

for CR16 bit 0 (HEFRAS). A 47 kΩ is recommended when

intends to pull up at power-on reset. nDTRB 46 O

UART B Data Terminal Ready. An active low informs the

modem or data set that controller is ready to communicate. nRTSA

PPNPCVS

36 I/O

UART A Request To Send. An active low informs the

modem or data set that the controller is ready to send data.

During power-on reset, this pin is pulled up internally and is

defined as PPNPCVS, which provides the power-on value

for CR16 bit 2 (PNPCVS). A 47 kΩ is recommended when

intends to pull down at power-on reset. nRTSB PGOIQSEL

45 I/O

UART B Request To Send. An active low informs the

modem or data set that the controller is ready to send data.

During power-on reset, this pin is pulled down internally and

is defined as PGOIQSEL, which provides the power-on

value for CR16 bit 4 (GOIQSEL). A 47 kΩ is recommended

when intends to pull up at power-on reset.

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Game Port/Power Down Interface

If Bit 3 of CR16 (GMDRQ) is 1, Bit 4 of CR3 (GMODS0) determines whether the game port is

in Adapter mode or Portable mode (default is Adapter mode). If Bit 3 of CR16 is 0, pin 39 and 41 are used for DMA A operation.

SYMBOL PIN I/O FUNCTION

nGMRD PFDCEN

nDACK_A

41 OUT

OUT

When CR16 Bit 3 (GMDRQ) = 1:

Adapter mode: Game port read control signal.

Portable mode: When parallel port is selected as Extension

FDD/Extension 2FDD mode, this pin will be active. The active

state is dependent on bit 7 of CRA (PFDCACT), and default is

low active.

When CR16 Bit 3 (GMDRQ) = 0:

DMA acknowledge signal A. nGMWR PEXTEN

DRQ_A

39 OUT

OUT

When CR16 Bit 3 (GMDRQ) = 1:

Adapter mode: Game port write control signal.

Portable mode: When a particular extended mode is selected

for the parallel port, this pin will be active. The extended

modes include Extension Adapter mode, EPP mode, ECP

mode, and ECP/EPP mode, which are selected using bit 3 -

bit 0 of CRA. The active state is dependent on bit 6 of CRA

(PEXTACT); the default is low active.

When CR16 Bit 3 (GMDRQ) = 0:

DMA request signal A. PDCIN 3 IN

This input pin controls the chip power down. When this pin is

active, the clock supply to the chip will be inhibited and the

output pins will be tri-stated as defined in CR4 and CR6. The

PDCIN is pulled down internally. Its active state is defined by

bit 4 of CRA (PDCHACT). Default is high active.

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Multi-Mode Parallel Port

The following pins have eight functions, which are controlled by bits PRTMOD0, PRTMOD1, and PRTMOD2 of CR0 and CR9 (refer to the Extended Functions section).

SYMBOL PIN I/O FUNCTION

BUSY 24 IN

PRINTER MODE: BUSY

An active high input indicates that the printer is not ready to

receive data. This pin is pulled high internally. Refer to the

description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE: nMOB2

This pin is for Extension FDD B; the function of this pin is the

same as that of the nMOB pin.

EXTENSION ADAPTER MODE: XIRQ

This pin is an interrupt request generated by the Extension

Adapter and is an active high input.

EXTENSION 2FDD MODE: nMOB2

This pin is for Extension FDD A and B; the function of this pin

is the same as that of the nMOB pin.

JOYSTICK MODE: NC pin. nACK 26 IN

PRINTER MODE: nACK

An active low input on this pin indicates that the printer has

received data and is ready to accept more data. This pin is

pulled high internally. Refer to the description of the parallel

port for the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDSB2

This pin is for the Extension FDD B; its functions are the

same as those of the nDSB pin.

EXTENSION ADAPTER MODE: XDRQ

DMA request generated by the Extension Adapter. An active

high input.

EXTENSION 2FDD MODE: nDSB2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nDSB pin.

JOYSTICK MODE: NC pin.

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SYMBOL PIN I/O FUNCTION

PE 27 IN

OUT

12t

PRINTER MODE: PE

An active high input on this pin indicates that the printer has

detected the end of the paper. This pin is pulled high

internally.

Refer to the description of the parallel port for the definition of

this pin in ECP and EPP mode.

EXTENSION FDD MODE: nWD2

This pin is for Extension FDD B; its function is the same as

that of the nWD pin.

EXTENSION ADAPTER MODE: XA0

This pin is system address A0 for the Extension Adapter.

EXTENSION 2FDD MODE: nWD2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nWD pin.

JOYSTICK MODE: NC pin. SLCT 28 IN

OUT

12t

PRINTER MODE: SLCT

An active high input on this pin indicates that the printer is

selected. This pin is pulled high internally. Refer to the

description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE: nWE2

This pin is for Extension FDD B; its functions are the same as

those of the nWE pin.

EXTENSION ADAPTER MODE: XA1

This pin is system address A1 for the Extension Adapter.

EXTENSION 2FDD MODE: nWE2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nWE pin.

JOYSTICK MODE: NC pin.

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SYMBOL PIN I/O FUNCTION

nERR 29 IN

OUT

12t

PRINTER MODE: nERR

An active low input on this pin indicates that the printer has

encountered an error condition. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nHEAD2

This pin is for Extension FDD B; its function is the same as

that of the nHEAD pin.

EXTENSION ADAPTER MODE: XA2

This pin is system address A2 for the Extension Adapter.

EXTENSION 2FDD MODE: nHEAD2

This pin is for Extension FDD A and B; its function is the

same as that of the nHEAD pin.

JOYSTICK MODE: NC pin.

nSLIN 22 OD

OUT

12t

OUT

12t

PRINTER MODE: nSLIN

Output line for detection of printer selection. This pin is pulled

high internally. Refer to the description of the parallel port for

the definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nSTEP2

This pin is for Extension FDD B; its function is the same as

that of the nSTEP pin.

EXTENSION ADAPTER MODE: XTC

This pin is the DMA terminal count for the Extension Adapter.

The count is sent by TC directly.

EXTENSION 2FDD MODE: nSTEP2

This pin is for Extension FDD A and B; its function is the

same as that of the nSTEP pin .

JOYSTICK MODE: VDD for joystick.

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SYMBOL PIN I/O FUNCTION

nINIT 21 OD

OUT

12t

OUT

12t

PRINTER MODE: nINIT

Output line for the printer initialization. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nDIR2

This pin is for Extension FDD B; its function is the same as

that of the nDIR pin.

EXTENSION ADAPTER MODE: nXDACK

This pin is the DMA acknowledge output for the Extension

Adapter; the output is sent directly from nPDACKX.

EXTENSION 2FDD MODE: nDIR2

This pin is for Extension FDD A and B; its function is the

same as that of the nDIR pin.

JOYSTICK MODE: VDD for joystick.

nAFD 20 OD

OUT

12t

OUT

12t

PRINTER MODE: nAFD

An active low output from this pin causes the printer to auto

feed a line after a line is printed. This pin is pulled high

internally. Refer to the description of the parallel port for the

definition of this pin in ECP and EPP mode.

EXTENSION FDD MODE: nRWC2

This pin is for Extension FDD B; its function is the same as

that of the nRWC pin.

EXTENSION ADAPTER MODE: nXRD

This pin is the I/O read command for the Extension Adapter.

When the Extension Adapter base address is written to the

Extension Adapter address register, nXRD and nXWR go low

simultaneously so that the command register on the

Extension Adapter can latch the same base address.

EXTENSION 2FDD MODE: nRWC2

This pin is for Extension FDD A and B; its function is the

same as that of the nRWC pin.

JOYSTICK MODE: VDD for joystick.

Page 14

SYMBOL PIN I/O FUNCTION

nSTB 19 OD

OUT

12t

OUT

12t

PRINTER MODE: nSTB

An active low output is used to latch the parallel data into the

printer. This pin is pulled high internally. Refer to the

description of the parallel port for the definition of this pin in

ECP and EPP mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: nXWR

This pin is the I/O write command for the Extension Adapter.

When the Extension Adapter base address is written to the

Extension Adapter address register, nXRD and nXWR go low

simultaneously so that the command register on the

Extension Adapter can latch the same base address.

EXTENSION 2FDD MODE: This pin is a tri-state output.

JOYSTICK MODE: VDD for joystick.

PD0 9 I/O

24t

I/O

24t

I/O

24t

PRINTER MODE: PD0

Parallel port data bus bit 0. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nINDEX2

This pin is for Extension FDD B; the function of this pin is the

same as that of the nINDEX pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD0

This pin is system data bus D0 for the Extension Adapter.

EXTENSION 2FDD MODE: nINDEX2

This pin is for Extension FDD A and B; this function of this pin

is the same as nINDEX pin. This pin is pulled high internally.

JOYSTICK MODE: JP0

This pin is the paddle 0 input for joystick.

Page 15

SYMBOL PIN I/O FUNCTION

PD1 10 I/O

24t

I/O

24t

I/O

24t

PRINTER MODE: PD1

Parallel port data bus bit 1. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nTRAK02

This pin is for Extension FDD B; the function of this pin is the

same as that of the nTRAK0 pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD1

This pin is system data bus D1 for the Extension Adapter.

EXTENSION. 2FDD MODE: nTRAK02

This pin is for Extension FDD A and B; this function of this pin

is the same as nTRAK0 pin. This pin is pulled high internally.

JOYSTICK MODE: JP1

This pin is the paddle 1 input for joystick.

PD2 11 I/O

24t

I/O

24t

PRINTER MODE: PD2

Parallel port data bus bit 2. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nWP2

This pin is for Extension FDD B; the function of this pin is the

same as that of the nWP pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD2

This pin is system data bus D2 for the Extension Adapter.

EXTENSION. 2FDD MODE: nWP2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nWP pin. This pin is pulled high

internally.

JOYSTICK MODE: NC pin

Page 16

SYMBOL PIN I/O FUNCTION

PD3 12 I/O

24t

I/O

24t

PRINTER MODE: PD3

Parallel port data bus bit 3. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nRDATA2

Motor on B for Extension FDD B; the function of this pin is the

same as that of the nRDATA pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD3

This pin is system data bus D3 for the Extension Adapter.

EXTENSION 2FDD MODE: nRDATA2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nRDATA pin. This pin is pulled high

internally.

JOYSTICK MODE: NC pin

PD4 13 I/O

24t

I/O

24t

PRINTER MODE: PD4

Parallel port data bus bit 4. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE: nDSHCHG2

Drive select B for Extension FDD B; the function of this pin is

the same as that of nDSHCHG pin. This pin is pulled high

internally.

EXTENSION ADAPTER MODE: XD4

This pin is system data bus D4 for the Extension Adapter.

EXTENSION 2FDD MODE: nDSKCHG2

This pin is for Extension FDD A and B; this function of this pin

is the same as that of the nDSKCHG pin. This pin is pulled

high internally.

JOYSTICK MODE: JB0

This pin is the button 0 input for the joystick.

Page 17

SYMBOL PIN I/O FUNCTION

PD5 14 I/O

24t

I/O

24t

PRINTER MODE: PD5

Parallel port data bus bit 5. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD5

This pin is system data bus D5 for the Extension Adapter

EXTENSION 2FDD MODE:

This pin is a tri-state output.

JOYSTICK MODE: JB1

This pin is the button 1 input for the joystick.

PD6 16 I/O

24t

I/O

24t

PRINTER MODE: PD6

Parallel port data bus bit 6. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD6

This pin is system data bus D6 for the Extension Adapter

EXTENSION. 2FDD MODE: nMOA2

This pin is for Extension FDD A; its function is the same as

that of the nMOA pin.

JOYSTICK MODE: NC pin

PD7 17 I/O

24t

I/O

24t

PRINTER MODE: PD7

Parallel port data bus bit 7. Refer to the description of the

parallel port for the definition of this pin in ECP and EPP

mode.

EXTENSION FDD MODE:

This pin is a tri-state output.

EXTENSION ADAPTER MODE: XD7

This pin is system data bus D7 for the Extension Adapter.

EXTENSION 2FDD MODE: nDSA2

This pin is for Extension FDD A; its function is the same as

that of the nDSA pin.

JOYSTICK MODE: NC pin

Page 18

IDE and FDC Interface

SYMBOL PIN I/O FUNCTION

nRESIDE/ IRQ_G

1 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: Active low reset signal for

IDE;

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal G.

nIDBEN/ IRQ_H

91 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: Active low enable signal for

IDE;

When CR16 Bit 1 (IRIDE) = 1: Interrupt request signal H.

nCS1/

IRTX2

95 OUT

12t

OUT

12t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the

IDE

controller. nCS1 decodes the HDC addresses specified in

CR22.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed

transmission data line.

nCS0/

IRRX2

94 OUT

12t

When CR16 Bit 1 (IRIDE) = 0: This pin is used to select the

IDE

controller. nCS0 decodes HDC addresses specified in

CR21.

When CR16 Bit 1 (IRIDE) = 1: Function as a InfraRed

receiving line.

nWE 85 OD

Write enable. An open drain output.

nDIR 89 OD

Direction of the head step motor. An open drain output.

Logic 1 = outward motion

Logic 0 = inward motion

nHEAD 88 OD

Head select. This open drain output determines which disk

drive head is active.

Logic 1 = side 0

Logic 0 = side 1

nRWC 87 OD

Reduced write current. This signal can be used on two-

speed disk drives to select the transfer rate. An open drain

output.

Logic 0 = 250 Kb/s

Logic 1 = 500 Kb/s

When bit 5 of CR9 (EN3MODE) is set to high, the three-

mode FDD function is enabled, and the pin will have a

different definition. Refer to the EN3MODE bit in CR9.

nWD 86 OD

Write data. This logic low open drain writes

precompensation serial data to the selected FDD. An open

drain output.

nSTEP 82 OD

Step output pulses. This active low open drain output

produces a pulse to move the head to another track.

Page 19

SYMBOL PIN I/O FUNCTION

nINDEX 81 IN

This schmitt input from the disk drive is active low when the

head is positioned over the beginning of a track marked by

an index hole. This input pin is pulled up internally by an

approximately 1K ohm resistor. The resistor can be

disabled by bit 4 of CR6 (FIPURDWN).

nTRAK0 78 IN

Track 0. This schmitt input from the disk drive is active low

when the head is positioned over the outermost track. This

input pin is pulled up internally by an approximately 1K

ohm resistor. The resistor can be disabled by bit 4 of CR6

(FIPURDWN).

nWP 77 IN

Write protected. This active low schmitt input from the disk

drive indicates that the diskette is write-protected. This

input pin is pulled up internally by an approximately 1K

ohm resistor. The resistor can be disabled by bit 4 of CR6

(FIPURDWN).

nRDATA 74 IN

The read data input signal from the FDD. This input pin is

pulled up internally by an approximately 1K ohm resistor.

The resistor can be disabled by bit 4 of CR6 (FIPURDWN).

nDSKCHG 76 IN

Diskette change. This signal is active low at power on and

whenever the diskette is removed. This input pin is pulled

up internally by an approximately 1K ohm resistor. The

resistor can be disabled by bit 4 of CR6 (FIPURDWN).

nMOA 79 OD

Motor A On. When set to 0, this pin enables disk drive 0.

This is an open drain output.

nMOB 80 OD

Motor B On. When set to 0, this pin enables disk drive 1.

This is an open drain output.

nDSA 83 OD

Drive Select A. When set to 0, this pin enables disk drive A.

This is an open drain output.

nDSB 84 OD

Drive Select B. When set to 0, this pin enables disk drive B.

This is an open drain output.

VDD 15, 56 +5 power supply for the digital circuitry GND 25, 40

65, 90

Ground

Page 20

FDC FUNCTIONAL DESCRIPTION

FDC87W22 FDC

The floppy disk controller of the FDC87W22 integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to 1 M bits/sec data rate.

The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital Data Separator, FIFO, and FDC Core.

AT Interface

The interface consists of the standard asynchronous signals: nRD, nWR, A0-A3, IRQ, DMA control, and a data bus. The address lines select between the configuration registers, the FIFO and control/status registers. This interface can be switched between PC/AT, Model 30, or

PS/2 normal modes. The PS/2 register sets are a superset of the registers found in a PC/AT.

FIFO (Data)

The FIFO is 16 bytes in size and has programmable threshold values. All command parameter information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and DIO bits in the Main Status Register.

The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the CONFIGURE command. The advantage of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following tables give several examples of the delays with a FIFO. The data are based upon the following formula:

THRESHOLD # × (1/DATA/RATE) *8 - 1.5 µS = DELAY

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 500K BPS

Data Rate

1 Byte

1 × 16 µS - 1.5 µS = 14.5 µS

2 Byte

2 × 16 µS - 1.5 µS = 30.5 µS

8 Byte

8 × 16 µS - 1.5 µS = 6.5 µS

15 Byte

15 × 16 µS - 1.5 µS = 238.5 µS

FIFO THRESHOLD MAXIMUM DELAY TO SERVICING AT 1M BPS

Data Rate

1 Byte

1 × 8 µS - 1.5 µS = 6.5 µS

2 Byte

2 × 8 µS - 1.5 µS = 14.5 µS

8 Byte

8 × 8 µS - 1.5 µS = 62.5 µS

15 Byte

15 × 8 µS - 1.5 µS = 118.5 µS

Page 21

At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.

An overrun and underrun will terminate the current command and the data transfer. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered.

DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the DRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid.

Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above operation is performed by using the new VERIFY command. No DMA operation is needed.

Data Separator

The function of the data separator is to lock onto the incoming serial read data. When a lock is achieved the serial front end logic of the chip is provided with a clock which is synchronized to the read data. The synchronized clock, called the Data Window, is used to internally sample the serial data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel conversion logic separates the read data into clock and data bytes.

The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking. The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on speed. A digital integrator is used to keep track of the speed changes in the input data stream.

Write Precompensation

The write precompensation logic is used to minimize bit shifts in the RDDATA stream from the disk drive. Shifting of bits is a known phenomenon in magnetic media and is dependent on the disk media and the floppy drive.

The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known. Depending upon the pattern, the bit is shifted either early or late relative to the surrounding bits.

Perpendicular Recording Mode

The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into the same area.

FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write perpendicular media. Some manufacturers offer drives that can read and write standard and perpendicular media in a perpendicular media drive.

Page 22

A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk.

FDC Core

The FDC87W22 FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-

byte transfer back to the microprocessor. Each command consists of three phases: command, execution, and result. Command The microprocessor issues all required information to the controller to perform a specific operation. Execution The controller performs the specified operation. Result After the operation is completed, status information and other housekeeping information is provided to the microprocessor.

Page 23

FDC Commands

Command Symbol Descriptions: C: Cylinder number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0, step out DIR = 1, step in DS0: Disk Drive Select 0 DS1: Disk Drive Select 1 DTL: Data Length EC: Enable Count EOT: End of Track EFIFO: Enable FIFO EIS: Enable Implied Seek EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset MFM: MFM or FM Mode MT: Multitrack N: The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark SRT: Step Rate Time ST0: Status Register 0 ST1: Status Register 1 ST2: Status Register 2 ST3: Status Register 3 WG: Write gate alters timing of WE

Page 24

(1) Read Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 0 1 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior to command

execution W W

---------------------- R ------------------------

---------------------- N -----------------------W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD and system

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

Page 25

(2) Read Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 0 1 1 0 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior

to command

execution

W W

---------------------- R ------------------------

---------------------- N -----------------------W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD and system

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

Page 26

(3) Read A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 0 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID information prior to

command execution W W

---------------------- R ------------------------

---------------------- N -----------------------W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD and system; FDD reads contents of all cylinders from index hole to EOT

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command execution

Page 27

(4) Read ID

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 0 1 0 Command codes

W 0 0 0 0 0 HDS DS1 DS0

Execution The first correct ID

information on the cylinder is stored in Data Register

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Disk status after

the command has

been completed

(5) Verify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM SK 1 0 1 1 0 Command codes

W EC 0 0 0 0 HDS DS1 DS0 W W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior to

command

execution W W

---------------------- R ------------------------

---------------------- N -----------------------W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL/SC -------------------

Execution No data transfer

takes place

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

Page 28

(6) Version

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 0 0 Command code Result R 1 0 0 1 0 0 0 0 Enhanced

controller

(7) Write Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 0 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior to

Command

execution

W W

---------------------- R ------------------------

---------------------- N -----------------------W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

W -------------------- DTL -----------------------

Execution Data transfer

between the FDD and system

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after Command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

Command

execution

Page 29

(8) Write Deleted Data

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W MT MFM 0 0 1 0 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W

---------------------- C ------------------------

---------------------- H ------------------------

Sector ID

information prior to

command

execution W W

---------------------- R ------------------------

---------------------- N -----------------------W W W

-------------------- EOT -----------------------

-------------------- GPL -----------------------

-------------------- DTL -----------------------

Execution Data transfer

between the FDD and system

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information after command

execution R R R R

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Sector ID

information after

command

execution

(9) Format A Track

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 MFM 0 0 1 1 0 1 Command codes

W 0 0 0 0 0 HDS DS1 DS0 W W

---------------------- N ------------------------

--------------------- SC -----------------------

Bytes/Sector

Sectors/Cylinder W W

--------------------- GPL ---------------------

---------------------- D ------------------------

Gap 3

Filler Byte

Execution for Each Sector Repeat:

W W W W

---------------------- C ------------------------

---------------------- H ------------------------

---------------------- R ------------------------

---------------------- N ------------------------

Input Sector

Parameters

Result R

R R

-------------------- ST0 -----------------------

-------------------- ST1 -----------------------

-------------------- ST2 -----------------------

Status information

after command

execution

R R R R

---------------- Undefined -------------------

Page 30

(10) Recalibrate

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 1 1 Command codes

W 0 0 0 0 0 0 DS1 DS0

Execution Head retracted to

Track 0 Interrupt

(11) Sense Interrupt Status

PHASE R/W D7 76 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 0 0 0 Command code Result R

---------------- ST0 -------------------------

---------------- PCN -------------------------

Status information at the end of each seek operation

(12) Specify

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 0 1 1 Command codes

W W

| ---------SRT ----------- | --------- HUT ---------- |

|------------ HLT ----------------------------------| ND

(13) Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 1 Command codes

W W

0 0 0 0 0 HDS DS1 DS0

-------------------- NCN -----------------------

Execution R Head positioned

over proper cylinder on diskette

(14) Configure

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 1 Configure

information W W W

0 0 0 0 0 0 0 0

0 EIS EFIFO POLL | ------ FIFOTHR ----|

| --------------------PRETRK ---------------------- |

Execution Internal registers

written

Page 31

(15) Relative Seek

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 1 DIR 0 0 1 1 1 1 Command codes

W W

0 0 0 0 0 HDS DS1 DS0

| -------------------- RCN ---------------------------- |

(16) Dumpreg

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 1 1 1 0 Registers placed

in FIFO

Result R

R R R R R R R R R

-------------------- PCN-Drive 0-----------------

-------------------- PCN-Drive 1 ----------------

-------------------- PCN-Drive 2-----------------

-------------------- PCN-Drive 3 ----------------

-------SRT ----------------- | --------- HUT --------

------------ HLT -------------------------------------| ND

-------------------- SC/EOT --------------------

LOCK 0 D3 D2 D1 D0 GAP WG

0 EIS EFIFO POLL | ------ FIFOTHR --------

--------------------PRETRK ---------------------

(17) Perpendicular Mode

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 1 0 0 1 0 Command Code

W OW 0 D3 D2 D1 D0 GAP WG

(18) Lock

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W LOCK 0 0 1 0 1 0 0 Command Code Result R 0 0 0 LOCK 0 0 0 0

(19) Sense Drive Status

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS

Command W 0 0 0 0 0 1 0 0 Command Code

W 0 0 0 0 0 HDS DS1 DS0

Result R ---------------- ST3 ------------------------- Status information

about disk drive

Page 32

(20) Invalid

PHASE R/W D7 D6 D5 D4 D3 D2 D1 D0

REMARKS

Command W ------------- Invalid Codes ----------------- Invalid codes (no

operation - FDC goes into standby state)

Result R -------------------- ST0 ---------------------- ST0 = 80H

There are several status, data, and control registers in FDC87W22. These registers are defined below:

ADDRESS REGISTER

OFFSET READ WRITE

base address + 0 base address + 1 base address + 2 base address + 3

SA REGISTER

SB REGISTER

TD REGISTER

DO REGISTER

TD REGISTER base address + 4 MS REGISTER DR REGISTER base address + 5 DT (FIFO) REGISTER DT (FIFO) REGISTER base address + 7 DI REGISTER CC REGISTER

Page 33

Status Register A (SA Register) (Read base address + 0)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:

INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.

nDRV2 (Bit 6): 0 A second drive has been installed 1 A second drive has not been installed

STEP (Bit 5): This bit indicates the complement of nSTEP output.

nTRAK0 (Bit 4): This bit indicates the value of nTRAK0 input.

HEAD (Bit 3): This bit indicates the complement of nHEAD output. 0 side 0 1 side 1

nINDEX (Bit 2): This bit indicates the value of nINDEX output.

nWP (Bit 1): 0 disk is write-protected 1 disk is not write-protected

DIR (Bit 0) This bit indicates the direction of head movement. 0 outward direction 1 inward direction

34567

nWP nINDEX

HEAD nTRAK0 STEP nDRV2

INIT PENDING

DIR

Page 34

In PS/2 Model 30 mode, the bit definitions for this register are as follows:

INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output.

DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5): This bit indicates the complement of latched nSTEP output.

TRAK0 (Bit 4): This bit indicates the complement of nTRAK0 input.

nHEAD (Bit 3): This bit indicates the value of nHEAD output. 0 side 1 1 side 0

INDEX (Bit 2): This bit indicates the complement of nINDEX output.

WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected

nDIR(Bit 0) This bit indicates the direction of head movement. 0 inward direction 1 outward direction

34567

WP INDEX nHEAD TRAK0 STEP F/F DRQ

INIT PENDING

nDIR

Page 35

Status Register B (SB Register) (Read base address + 1)

This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows:

34567

MOT EN A

WE RDATA Toggle

WDATA Toggle

Drive SEL0

MOT EN B

Drive SEL0 (Bit 5): This bit indicates the status of DO REGISTER bit 0 (drive select bit 0).

WDATA Toggle (Bit 4): This bit changes state at every rising edge of the nWD output pin.

RDATA Toggle (Bit 3): This bit changes state at every rising edge of the nRDATA output pin.

WE (Bit 2): This bit indicates the complement of the nWE output pin.

MOT EN B (Bit 1) This bit indicates the complement of the nMOB output pin.

Page 36

MOT EN A (Bit 0) This bit indicates the complement of the nMOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows:

nDRV2 (Bit 7): 0 A second drive has been installed 1 A second drive has not been installed

nDSB (Bit 6): This bit indicates the status of nDSB output pin.

nDSA (Bit 5): This bit indicates the status of nDSA output pin.

WD F/F(Bit 4): This bit indicates the complement of the latched nWD output pin at every rising edge of the nWD output pin.

RDATA F/F(Bit 3): This bit indicates the complement of the latched nRDATA output pin .

WE F/F (Bit 2): This bit indicates the complement of latched nWE output pin. nDSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected

nDSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected

34567

nDSC nDSD WE F/F

RDATA F/F nDSA

nDSB

nDRV2

WD F/F

Page 37

Digital Output Register (DO Register) (Write base address + 2)

The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows:

7 6

5 4

1-0

Drive Select: 00 select drive A

01 select drive B 10 select drive C

11 select drive D Floppy Disk Controller Reset Active low resets FDC DMA and INT Enable Active high enable DRQ/IRQ Motor Enable A. Motor A on when active high Motor Enable B. Motor B on when active high Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high

Tape Drive Register (TD Register) (Read base address + 3)

This register is used to assign a particular drive number to the tape drive support mode of the data separator. This register also holds the media ID, drive type, and floppy boot drive information of the floppy disk drive. In normal floppy mode, this register includes only bit 0 and 1. The bit definitions are as follows:

34567

Tape sel 0

Tape sel 1

X X

X X X X

If three mode FDD function is enabled (EN3MODE = 1 in CR9), the bit definitions are as follows:

34567

Floppy boot drive 0

Floppy boot drive 1

Drive type ID0 Drive type ID1 Media ID0 Media ID1

Tape Sel 0

Tape Sel 1

Page 38

Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2.

Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the bits of CR7. Which two bits are reflected depends on the last drive selected in the DO REGISTER.

Floppy Boot drive 1, 0 (Bit 3, 2): These two bits reflect the value of CR8 bit 1, 0.

Tape Sel 1, Tape Sel 0 (Bit 1, 0): These two bits assign a logical drive number to the tape drive. Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive.

TAPE SEL 1 TAPE SEL 0 DRIVE SELECTED

0 0 None 0 1 1 1 0 2 1 1 3

Main Status Register (MS Register) (Read base address + 4)

The Main Status Register is used to control the flow of data between the microprocessor and the controller. The bit definitions for this register are as follows:

FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode. FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.

FDC Busy, (CB). A read or write command is in the process when CB = HIGH. Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the execution phase in non-DMA mode. Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register.

Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.

3 2 1

FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.

FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.

Page 39

Data Rate Register (DR Register) (Write base address + 4)

The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and not by the DR REGISTER. The real data rate is determined by the most recent write to either of the DR REGISTER or CC REGISTER.

34567

DRATE0 DRATE1 PRECOMP0

PRECOMP1 PRECOMP2

POWER DOWN

S/W RESET

S/W RESET (Bit 7): This bit is the software reset bit.

POWER-DOWN (Bit 6): 0 FDC in normal mode 1 FDC in power-down mode

PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits.

Page 40

PRECOM

2 1 0 PRECOMPENSATION DELAY

0 0 0 Default Delays 0 0 1 41.67 nS 0 1 0 83.34 nS 0 1 1 125.00 nS 1 0 0 166.67 nS 1 0 1 208.33 nS 1 1 0 250.00 nS 1 1 1 0.00 nS (disabled)

DATA RATE DEFAULT PRECOMPENSATION DELAYS

250 KB/S 125 nS 300 KB/S 125 nS 500 KB/S 125 nS

1 MB/S 41.67 nS

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control.

00 500 KB/S (MFM), 250 KB/S (FM), nRWC = 1. 01 300 KB/S (MFM), 150 KB/S (FM), nRWC = 0. 10 250 KB/S (MFM), 125 KB/S (FM), nRWC = 0. 11 1 MB/S (MFM), Illegal (FM), nRWC = 1.

FIFO Register (R/W base address + 5)

The Data Register consists of four status registers in a stack with only one register presented to the data bus at a time. This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the FDC87W22, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command.

Page 41

Status Register 0 (ST0)

Status Register 1 (ST1)

7-6 5

3 2 1-0

US1, US0 Drive Select:

00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D selected

HD Head address:

1 Head selected 0 Head selected

NR Not Ready:

1 Drive is not ready 0 Drive is ready

EC Equipment Check:

1 When a fault signal is received from the FDD or the track 0 signal fails to occur after 77 step pulses 0 No error

SE Seek end:

1 seek end 0 seek error

IC Interrupt Code:

00 Normal termination of command 01 Abnormal termination of command 10 Invalid command issue

11 Abnormal termination because the ready signal from FDD changed state during command execution

Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted.

NW (Not Writable). 1 If a write Protect signal is detected from the diskette drive during execution of write data.

ND (No DATA). 1 If specified sector cannot be found during execution of a read, write or verifly data. Not used. This bit is always 0. OR (Over Rum). 1 If the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field.

Not used. This bit is always 0.

EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder.

234567

Page 42

Status Register 2 (ST2)

234

7 0

BC (Bad Cylinder)

MD (Missing Address Mark in Data Field). 1 If the FDC cannot find a data address mark (or the address mark has been deleted) when reading data from the media 0 No error

1 Bad Cylinder 0 No error SN (Scan Not satisfied)

1 During execution of the Scan command 0 No error SH (Scan Equal Hit)

1 During execution of the Scan command, if the equal condition is satisfied 0 No error WC (Wrong Cylinder) 1 Indicates wrong Cylinder DD (Data error in the Data field)

1 If the FDC detects a CRC error in the data field

0 No error CM (Control Mark) 1 During execution of the read data or scan command 0 No error Not used. This bit is always 0

Status Register 3 (ST3)

US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready

WP Write Protected

FT Fault

Digital Input Register (DI Register) (Read base address + 7)

The Digital Input Register is an 8-bit read-only register used for diagnostic purposes. In a PC/XT or AT only Bit 7 is checked by the BIOS. When the register is read, Bit 7 shows the complement of nDSKCHG, while other bits of the data bus remain in tri-state. Bit definitions are as follows:

xxx

01234

567

Reserved for the hard disk controller During a read of this register, these bits are in tri-state

DSKCHG

Page 43

In the PS/2 mode, the bit definitions are as follows:

DSKCHG (Bit 7): This bit indicates the complement of the nDSKCHG input.

Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1):

These two bits select the data rate of the FDC. Refer to the DR register bits 1 and 0 for the settings corresponding to the individual data rates.

nHIGH DENS (Bit 0): 0 500 KB/S or 1 MB/S data rate (high density FDD) 1 250 KB/S or 300 KB/S data rate

In the PS/2 Model 30 mode, the bit definitions are as follows:

DSKCHG (Bit 7): This bit indicates the status of nDSKCHG input.

Bit 6-4: These bits are always a logic 1 during a read.

34567

nHIGH DENS DRATE0

DRATE1

DSKCHG

1 111

34567

DRATE0

DRATE1

nDSKCHG

NOPREC DMAEN

0 00

Page 44

DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3.

NOPREC (Bit 2): This bit indicates the value of CC REGISTER NOPREC bit.

DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC.

Configuration Control Register (CC Register) (Write base address + 7)

This register is used to control the data rate. In the PC/AT and PS/2 mode, the bit definitions are as follows:

x x x x x x

DRATE0 DRATE1

X: Reserved Bit 7-2: Reserved. These bits should be set to 0. DRATE1 DRATE0 (Bit 1, 0):

These two bits select the data rate of the FDC. In the PS/2 Model 30 mode, the bit definitions are as follows:

34567

DRATE0

DRATE1

NOPREC

X X

X X X

X: Reserved Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2):

This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0):

These two bits select the data rate of the FDC.

Page 45

IDE

The IDE interface is essentially the AT bus ported to the hard disk drive. The hard disk controller resides on the IDE hard disk drive. So the IDE interface provides only chip select

signals and AT bus signals between the IDE hard disk drive and ISA slot. Table 1 shows the IDE registers and their ISA addresses.

Table 1

I/O ADDRESS REGISTERS

OFFSET READ WRITE

nCS0 base address + 0 Data Register Data Register nCS0 base address + 1 Error Register Write-Precomp nCS0 base address + 2 Sector Count Sector Count nCS0 base address + 3 Sector Number Sector Number nCS0 base address + 4 Cylinder LOW Cylinder LOW nCS0 base address + 5 Cylinder HIGH Cylinder HIGH nCS0 base address + 6 SDH Register SDH Register nCS0 base address + 7 Status Register Command Register nCS1 base address + 6 Alternate Status Fixed Disk Control

IDE Decode Description

When the processor selects the addresses which match the ones specified in CR 21, the chip system enables nCS0 = LOW; otherwise,

nCS0 = HIGH. When the processor selects the address which matches the one specified in CR22, the chip system enables nCS1 = LOW; otherwise, nCS1 = HIGH.

Page 46

UART PORT

Universal Asynchronous Receiver/Transmitter (UART A, UART B)

The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to parallel format on the receiver side. The serial format, in order of transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the internal transmitter logic. Provisions are also included to

use this 16x clock to drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also include complete modem control capability and a processor interrupt system that may be software trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode.

TABLE 2 - UART Register Bit Map

BIT NUMBER

BDLAB = 0

Receiver

Buffer

(Read Only)

RBR RX Data

Bit 0

RX Data

Bit 1

RX Data

Bit 2

RX Data

Bit 3

BDLAB = 0

Transmitter

Buffer Register

(Write Only)

TBR TX Data

Bit 0

TX Data

Bit 1

TX Data

Bit 2

TX Data

Bit 3

BDLAB = 0

Interrupt Control

ICR RBR Data

Ready

Interrupt

Enable

(ERDRI)

TBR

Empty

Interrupt

Enable

(ETBREI)

USR

Interrupt

Enable

(EUSRI)

HSR

Interrupt

Enable

(EHSRI)

A Interrupt Status

(Read Only)

ISR "0" if Interrupt

Pending

Interrupt

Status Bit (0)

Interrupt

Status

Bit (1)

Interrupt

Status

Bit (2)**

A UART FIFO

Control

(Write Only)

UFR FIFO

Enable

RCVR

FIFO

Reset

XMIT

FIFO

Reset

DMA

Mode

Select

Page 47

BIT NUMBER

B UART Control

UCR Data

Length

Select

Bit 0

(DLS0)

Data

Length

Select

Bit 1

(DLS1)

Multiple

Stop Bits

Enable

(MSBE)

Parity

Bit

Enable

(PBE)

C Handshake

Control

HCR Data

Terminal

Ready

(DTR)

Request

Send

(RTS)

Loopback

Input

IRQ

Enable

D UART Status

USR RBR Data

Ready (RDR)

Overrun

Error

(OER)

Parity Bit

Error

(PBER)

No Stop

Bit

Error

(NSER)

E Handshake Status

HSR CTS

Toggling

(TCTS)

DSR

Toggling

(TDSR)

RI Falling

Edge

(FERI)

DCD

Toggling

(TDCD)

F User Defined

UDR Bit 0 Bit 1 Bit 2 Bit 3

BDLAB = 1

Baudrate Divisor

Latch Low

BLL Bit 0 Bit 1 Bit 2 Bit 3

BDLAB = 1

Baudrate Divisor

Latch High

BHL Bit 8 Bit 9 Bit 10 Bit 11

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 mode.

TABLE 2 - UART Register Bit Map (continued)

BIT NUMBER

BDLAB = 0

Receiver

Buffer

(Read Only)

RBR RX Data

Bit 4

RX Data

Bit 5

RX Data

Bit 6

RX Data

Bit 7

BDLAB = 0

Transmitter

Buffer Register

(Write Only)

TBR TX Data

Bit 4

TX Data

Bit 5

TX Data

Bit 6

TX Data

Bit 7

BDLAB = 0

Interrupt Control

ICR 0 0 0 0

Page 48

BIT NUMBER

A Interrupt Status

(Read Only)

ISR 0 0 FIFOs

Enabled

FIFOs

Enabled

A UART FIFO

Control

(Write Only)

UFR Reserved Reversed RX

Interrupt

Active

Level

(LSB)

Interrupt

Active

Level

(MSB)

B UART Control

UCR Even

Parity

Enable

(EPE)

Parity

Bit Fixed

Enable

PBFE)

Set

Silence

Enable

(SSE)

Baud rate

Divisor

Latch

Access Bit

(BDLAB)

C Handshake

Control

HCR Internal

Loopback

Enable

0 0 0

D UART Status

USR Silent

Byte

Detected

(SBD)

TBR

Empty

(TBRE)

TSR

Empty

(TSRE)

RX FIFO

Error

Indication

(RFEI) **

E Handshake

Status Register

HSR Clear

to Send

(CTS)

Data Set

Ready (DSR)

Ring

Indicator

(RI)

Data

Carrier

Detect

(DCD)

F User Defined

UDR Bit 4 Bit 5 Bit 6 Bit 7

BDLAB = 1

Baudrate Divisor

Latch Low

BLL Bit 4 Bit 5 Bit 6 Bit 7

BDLAB = 1

Baudrate Divisor

Latch High

BHL Bit 12 Bit 13 Bit 14 Bit 15

*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 mode.

Page 49

UART Control Register (UCR) (Read/Write)

The UART Control Register controls and defines the protocol for asynchronous data communications, including data length, stop bit, parity, and baud rate selection.

7 0

Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE)

Baudrate divisor latch access bit (BDLAB)

Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary

format) from the divisor latches of the baudrate generator during a read or write operation. When this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control Register can be accessed.

Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only SOUT

is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1, (1) if EPE is a logical 1, the parity bit is fixed as a logical 0 to transmit and check. (2) if EPE is a logical 0, the parity bit is fixed as a logical 1 to transmit and check. Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when

bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked.

When the bit is reset, an odd number of logic 1's are sent or checked. Bit 3: PBE. When this bit is set, the position between the last data bit and the stop bit of the SOUT

will be stuffed with the parity bit at the transmitter. For the receiver, the parity bit in the same

position as the transmitter will be detected. Bit 2: MSBE. This bit defines the number of stop bits in each serial character that is transmitted or

received.

(1) If MSBE is set to a logical 0, one stop bit is sent and checked.

(2) If MSBE is set to a logical 1, and data length is 5 bits, one and a half stop bits are sent

and checked.

(3) If MSBE is set to a logical 1, and data length is 6, 7, or 8 bits, two stop bits are sent and

checked. Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in

each serial character.

Page 50

TABLE 3 - WORD LENGTH DEFINITION

DLS1 DLS0 DATA LENGTH

0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits

UART Status Register (USR) (Read/Write)

This 8-bit register provides information about the status of the data transfer during communication.

67 0

RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE)

Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI)

Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a

logic 1 when there is at least one parity bit error, no stop bit error or silent byte detected in

the FIFO. In 16550 mode, this bit is cleared by reading from the USR if there are no

remaining errors left in the FIFO. Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1.

In 16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1.

Other than these two cases, this bit will be reset to a logical 0. Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be

set to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the

CPU to write the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit

FIFO is empty. It will be reset to a logical 0 when the CPU writes data into TBR or FIFO. Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a

full word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it

indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it

will clear this bit to a logical 0. Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In

16550 mode, it indicates the same condition for the data on top of the FIFO. When the

CPU reads USR, it will clear this bit to a logical 0. Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In

16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU

reads USR, it will clear this bit to a logical 0.

Page 51

Bit 1: OER. This bit is set to a logical 1 to indicate received data have been overwritten by the next

received data before they were read by the CPU. In 16550 mode, it indicates the same

condition instead of FIFO full. When the CPU reads USR, it will clear this bit to a logical 0. Bit 0: RDR. This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in

the RBR or FIFO. After no data are left in the RBR or FIFO, the bit will be reset to a logical 0.

Handshake Control Register (HCR) (Read/Write)

This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART.

345

Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable

Internal loopback enable

Bit 4: When this bit is set to a logical 1, the UART enters diagnostic mode by an internal loopback,

as follows:

(1) SOUT is forced to a logical 1, and SIN is isolated from the communication link instead of

the TSR.

(2) Modem output pins are set to their inactive state.

(3) Modem input pins are isolated from the communication link and connect internally as

DTR (bit 0 of HCR) → nDSR, RTS ( bit 1 of HCR) → nCTS, Loopback RI input ( bit 2 of HCR) → nRI and IRQ enable ( bit 3 of HCR) → nDCD.

Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way.

Bit 3: The UART interrupt output is enabled by setting this bit to a logic 1. In the diagnostic mode

this bit is internally connected to the modem control input nDCD. Bit 2: This bit is used only in the diagnostic mode. In the diagnostic mode this bit is internally

connected to the modem control input nRI. Bit 1: This bit controls the nRTS output. The value of this bit is inverted and output to nRTS. Bit 0: This bit controls the nDTR output. The value of this bit is inverted and output to nDTR.

Page 52

Handshake Status Register (HSR) (Read/Write)

This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins.

Bit 7: This bit is the opposite of the nDCD input. This bit is equivalent to bit 3 of HCR in loopback

mode. Bit 6: This bit is the opposite of the nRI input. This bit is equivalent to bit 2 of HCR in loopback

mode. Bit 5: This bit is the opposite of the nDSR input. This bit is equivalent to bit 0 of HCR in loopback

mode. Bit 4: This bit is the opposite of the nCTS input. This bit is equivalent to bit 1 of HCR in loopback

mode. Bit 3: TDCD. This bit indicates that the nDCD pin has changed state after HSR was read by the

CPU. Bit 2: FERI. This bit indicates that the nRI pin has changed from low to high state after HSR was

read by the CPU. Bit 1: TDSR. This bit indicates that the nDSR pin has changed state after HSR was read by the

CPU. Bit 0: TCTS. This bit indicates that the nCTS pin has changed state after HSR was read by the

CPU.

1234567 0

RI falling edge (FERI)

Clear to send (CTS) Data set ready (DSR)

Ring indicator (RI)

Data carrier detect (DCD)

nCTS

toggling (TCTS)

nDSR

toggling (TDSR)

nDCD

toggling (TDCD)

Page 53

UART FIFO Control Register (UFR) (Write only)

This register is used to control the FIFO functions of the UART.

34567 0

FIFO enable Receiver FIFO reset Transmitter FIFO reset

DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB)

Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example,

if the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.

TABLE 4 - FIFO TRIGGER LEVEL

BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)

0 0 01 0 1 04 1 0 08 1 1 14

Bit 4, 5: Reserved Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if

UFR bit 0 = 1. Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear

to a logical 0 by itself after being set to a logical 1. Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear

to a logical 0 by itself after being set to a logical 1. Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1

before other bits of UFR are programmed.

Page 54

Interrupt Status Register (ISR) (Read only)

This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits.

1234567

0 if interrupt pending Interrupt Status bit 0

Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled

FIFOs enabled

0 0

Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1. Bit 5, 4: These two bits are always logic 0. Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a

time-out interrupt is pending. Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below. Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has

occurred, this bit will be set to a logical 0.

Page 55

TABLE 5 - INTERRUPT CONTROL FUNCTION

ISR INTERRUPT SET AND FUNCTION

Bit3Bit2Bit1Bit0Interrupt

Priority

Interrupt

Type

Interrupt Source Clear Interrupt

0 0 0 1 - - No Interrupt pending 0 1 1 0 First UART

Receive Status

1. OER = 1 2. PBER =1

3. NSER = 1 4. SBD = 1

Read USR

0 1 0 0 Second RBR Data

Ready

1. RBR data ready

2. FIFO interrupt active level reached

1. Read RBR

2. Read RBR until FIFO data under active level

1 1 0 0 Second FIFO Data

Timeout

Data present in RX FIFO for 4 characters period of time since last access of RX FIFO.

Read RBR

0 0 1 0 Third TBR Empty TBR empty 1. Write data into

TBR

2. Read ISR (if priority is third)

0 0 0 0 Fourth Handshake

Status

1. TCTS = 1 2. TDSR = 1

3. FERI = 1 4. TDCD = 1

Read HSR

** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.

Page 56

Interrupt Control Register (ICR) (Read/Write)

This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this register to a logical 1.

0 0 0

RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI)

Bit 7-4: These four bits are always logic 0. Bit 3: EHSRI. Setting this bit to a logical 1 enables the handshake status register interrupt. Bit 2: EUSRI. Setting this bit to a logical 1 enables the UART status register interrupt. Bit 1: ETBREI. Setting this bit to a logical 1 enables the TBR empty interrupt. Bit 0: ERDRI. Setting this bit to a logical 1 enables the RBR data ready interrupt.

Programmable Baud Generator (BLL/BHL) (Read/Write)

Two 8-bit registers, BLL and BHL, compose a programmable baud generator that uses 24 MHz to generate a 1.8461 MHz frequency and divides it by a divisor from 1 to 216-1. The output frequency of the baud generator is the baud rate multiplied by 16, and this is the base frequency for the transmitter and receiver. The table below illustrates the use of the baud generator with a frequency of 1.8461 MHz. In high-speed UART mode (refer to CR0C bit7 and CR0C bit6), the programmable baud generator directly uses 24 MHz and the same divisor as the normal speed divisor. In high-speed mode, the data transmission rate can be as high as 1.5M bps.

Page 57

User-Defined Register (UDR) (Read/Write)

This is a temporary register that can be accessed and defined by the user.

TABLE 6 - BAUD RATES

BAUD RATE USING 24 MHz TO GENERATE 1.8461 MHz

Desired Baud Rate

Decimal divisor used to

generate 16X clock

Percent error difference between

desired and actual

50 2304 ** 75 1536 **

110 1047 0.18%

134.5 857 0.099% 150 768 ** 300 384 ** 600 192 **

1200 96 ** 1800 64 ** 2000 58 0.53% 2400 48 ** 3600 32 ** 4800 24 ** 7200 16 ** 9600 12 **

19200 6 **

38400 3 **

57600 2 ** 115200 1 ** 230400 104* ** 460800 52* ** 921600 26* **

1.5M 1* 0%

* Only use in high speed mode (refer to CR0C bit 7 and CR0C bit 6). ** The percentage error for all baud rates, except where indicated otherwise, is 0.16%.

Page 58

PARALLEL PORT

Printer Interface Logic

The parallel port of the FDC87W22 makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The FDC87W22 supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port

(ECP), Extension FDD mode (EXTFDD), and Extension 2FDD mode (EXT2FDD) on the parallel port. Refer to the configuration registers for more information on disabling, power-down, and on selecting the mode of operation.

Table 7A shows the pin definitions for different modes of the parallel port.

TABLE 7A - Parallel Port Connector and Pin Definition for SPP/EPP/ECP Modes

HOST

CONNECTOR

PIN NUMBER

OF FDC87W22

ATTRIBUTE SPP EPP ECP

1 19 O nSTB nWrite nSTB

2-9 9-14,16-17 I/O PD<0:7> PD<0:7> PD<0:7>

10 26 I nACK Intr nACK 11 24 I BUSY nWait BUSY, PeriphAck

12 27 I PE PE PEerror,

nAckReverse

13 28 I SLCT Select SLCT 14 20 O nAFD nDStrb nAFD, HostAck

15 29 I nERR nError nFault1,

nPeriphRequest

16 21 O nINIT nInit nINIT1,

nReverseRqst

17 22 O nSLIN nAStrb nSLIN

1,2

Notes: n<name > : Active Low

1. Compatible Mode

2. High Speed Mode

3. For more information, refer to the IEEE 1284 standard.

Page 59

TABLE 7B - Parallel Port Connector and Pin Definition for EXTFDD and EXT2FDD Modes

Host

Connector

Pin Number

FDC87W22

Attri-

bute SPP

Attri-

bute EXT2FDD

Attri-

bute EXT-FDD

1 19 O nSTB --- --- --- --2 9 I/O PD0 I nINDEX2 I nINDEX2 3 10 I/O PD1 I nTRAK02 I nTRAK02 4 11 I/O PD2 I nWP2 I nWP2 5 12 I/O PD3 I nRDATA2 I nRDATA2 6 13 I/O PD4 I nDSKCHG2 I nDSKCHG2 7 14 I/O PD5 --- --- --- --8 15 I/O PD6 OD nMOA2 --- ---

9 16 I/O PD7 OD nDSA2 --- --10 26 I nACK OD nDSB2 OD nDSB2 11 24 I BUSY OD nMOB2 OD nMOB2 12 27 I PE OD nWD2 OD nWD2 13 28 I SLCT OD nWE2 OD nWE2 14 20 O nAFD OD nRWC2 OD nRWC2 15 29 I nERR OD nNERR2 OD nNERR2 16 21 O nINIT OD nDIR2 OD nDIR2 17 22 O nSLIN OD nSTEP2 OD nSTEP2

Page 60

HOST

CONNECTOR

PIN NUMBER

FDC87W22

ATTRI-

BUTE

SPP

ATTRI-

BUTE

EXTADP

MODE

ATTRI-

BUTE

JOYSTICK

MODE

1 19 O nSTB O nXWR O VDD 2 9 I/O PD0 I/O XD0 I JP0 3 10 I/O PD1 I/O XD1 I JP1 4 11 I/O PD2 I/O XD2 I --5 12 I/O PD3 I/O XD3 I --6 13 I/O PD4 I/O XD4 I JB0 7 14 I/O PD5 I/O XD5 I JB1 8 15 I/O PD6 I/O XD6 I ---

9 16 I/O PD7 I/O XD7 I --10 26 I nACK I XDRQ I --11 24 I BUSY I XIRQ I --12 27 I PE O XA0 I --13 28 I SLCT O XA1 I --14 20 O nAFD O nXRD O VDD 15 29 I nERR O XA2 I --16 21 O nINIT O nXDACK O VDD 17 22 O nSLIN O TC O VDD

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Enhanced Parallel Port (EPP)

TABLE 8 - PRINTER MODE AND EPP REGISTER ADDRESS

A2 A1 A0 REGISTER NOTE

0 0 0 Data port (R/W) 1 0 0 1 Printer status buffer (Read) 1 0 1 0 Printer control latch (Write) 1 0 1 0 Printer control swapper (Read) 1 0 1 1 EPP address port (R/W) 2 1 0 0 EPP data port 0 (R/W) 2 1 0 1 EPP data port 1 (R/W) 2 1 1 0 EPP data port 2 (R/W) 2 1 1 1 EPP data port 2 (R/W) 2

Notes:

1. These registers are available in all modes.

2. These registers are available only in EPP mode.

Data Swapper

The system microprocessor can read the contents of the printer's data latch by reading the data swapper.

Printer Status Buffer

The system microprocessor can read the printer status by reading the address of the printer status buffer. The bit definitions are as follows:

Bit 7: This signal is active during data entry, when the printer is off-line during printing, when the

print head is changing position, or during an error state. When this signal is active, the printer is busy and cannot accept data.

235 467 0

TMOUT nERROR SLCT

nBUSY

nACK

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Bit 6: This bit represents the current state of the printer's nACK signal. A 0 means the printer has

received a character and is ready to accept another. Normally, this signal will be active for

approximately 5 microseconds before nBUSY stops. Bit 5: A 1 means the printer has detected the end of paper. Bit 4: A 1 means the printer is selected. Bit 3: A 0 means the printer has encountered an error condition. Bit 1, 2: These two bits are not implemented and are logic one during a read of the status register.

Bit 0: This bit is valid in EPP mode only. It indicates that a 10 µS time-out has occurred on the EPP

bus. A logic 0 means that no time-out error has occurred; a logic 1 means that a time-out

error has been detected. Writing a logic 1 to this bit will clear the time-out status bit; writing a

logic 0 has no effect.

Printer Control Latch and Printer Control Swapper

The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows:

Bit 7,6: These two bits are a logic one during a read. They can be written. Bit 5: Direction control bit

When this bit is a logic 1, the parallel port is in input mode (read); when it is a logic 0, the

parallel port is in output mode (write). This bit can be read and written. In SPP mode, this bit

is invalid and fixed at zero. Bit 4: A 1 in this position allows an interrupt to occur when nACK changes from low to high. Bit 3: A 1 in this bit position selects the printer. Bit 2: A 0 starts the printer (50 microsecond pulse, minimum). Bit 1: A 1 causes the printer to line-feed after a line is printed. Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must

be present for a minimum of 0.5 microseconds before and after the strobe pulse.

111

234567 0

STROBE AUTO FD

SLCT IN IRQ ENABLE

DIR

nINIT

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EPP Address Port

The address port is available only in EPP mode. Bit definitions are as follows:

1234567 0

PD0 PD1

PD2 PD3

PD5

PD4 PD6

PD7

The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of nIOW causes an EPP address write cycle to be performed, and the trailing edge of nIOW latches the data for the duration of the EPP write cycle.

PD0-PD7 ports are read during a read operation. The leading edge of

nIOR

causes an EPP address

read cycle to be performed and the data to be output to the host CPU.

EPP Data Port 0-3

These four registers are available only in EPP mode. Bit definitions of each data port are as follows:

123456

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting) and output to the ports PD0-PD7 during a write operation. The leading edge of

nIOW

causes an EPP

data write cycle to be performed, and the trailing edge of

nIOW

latches the data for the duration of the

EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of nIOR causes an EPP read

cycle to be performed and the data to be output to the host CPU.

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Bit Map of Parallel Port and EPP Registers

Data Port (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Status Buffer (Read)

nBUSY nACK

PE SLCT nERROR 1 1 TMOUT

Control Swapper (Read)

1 1 1 IRQEN SLIN nINIT nAUTOFD nSTROBE

Control Latch (Write)

1 1 DIR IRQ SLIN nINIT nAUTOFD nSTROBE

EPP Address Port (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

EPP Data Port 0 (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

EPP Data Port 1 (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

EPP Data Port 2 (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

EPP Data Port 3 (R/W)

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

EPP Pin Descriptions

EPP NAME TYPE EPP DESCRIPTION

nWrite O Denotes an address or data read or write operation. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host. nWait I Inactive to acknowledge that data transfer is completed. Active to

indicate that the device is ready for the next transfer. PE I Paper end; same as SPP mode. Select I Printer selected status; same as SPP mode. nDStrb O This signal is active low. It denotes a data read or write operation. nError I Error; same as SPP mode. nInits O This signal is active low. When it is active, the EPP device is reset to

its initial operating mode. nAStrb O This signal is active low. It denotes an address read or write operation.

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EPP Operation

When the EPP mode is selected in the configuration register, the standard and bidirectional modes are also available. The PDx bus is in the standard or bi-directional mode when no EPP read, write, or address cycle is currently being executed. In this condition all output signals are set by the SPP Control Port and the direction is controlled by DIR of the Control Port.

A watchdog timer is required to prevent system lockup. The timer indicates that more than 10 µ

S have elapsed from the start of the EPP cycle to the time nWAIT is de-asserted. The current EPP cycle is aborted when a time-out occurs. The time-out condition is indicated in Status bit

0. EPP Operation

The EPP operates on a two-phase cycle. First, the host selects the register within the device for subsequent operations. Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed synchronously.

EPP Version 1.9 Operation The EPP read/write operation can be completed under the following conditions: a. If the nWait is active low, when the read

cycle (nWrite inactive high, nDStrb/nAStrb active low) or write cycle (nWrite active low, nDStrb/nAStrb active low) starts, the read/write cycle proceeds normally and will be completed when nWait goes inactive high.

b. If nWait is inactive high, the read/write cycle

will not start. It must wait until nWait changes to active low, at which time it will start as described above.

EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts, however, it will not terminate until nWait changes from active low to inactive high.

Extended Capabilities Parallel (ECP) Port

This port is software and hardware compatible with existing parallel ports, so it may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions.

Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed.

The ECP port supports run-length-encoded (RLE) decompression (required) in the hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated. The hardware support for compression is optional.

For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard.

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ECP Register and Mode Definitions

NAME ADDRESS I/O ECP MODES FUNCTION

data Base+000h R/W 000-001 Data Register ecpAFifo Base+000h R/W 011 ECP FIFO (Address) dsr Base+001h R All Status Register dcr Base+002h R/W All Control Register cFifo Base+400h R/W 010 Parallel Port Data FIFO ecpDFifo Base+400h R/W 011 ECP FIFO (DATA) tFifo Base+400h R/W 110 Test FIFO cnfgA Base+400h R 111 Configuration Register A cnfgB Base+401h R/W 111 Configuration Register B

ecr Base+402h R/W All Extended Control Register Note: The base addresses are specified by CR23, which are determined by configuration register or hardware setting.

MODE DESCRIPTION

000 SPP mode

001 PS/2 Parallel Port mode

010 Parallel Port Data FIFO mode

011 ECP Parallel Port mode

100 EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)

101 Reserved

110 Test mode

111 Configuration mode Note: The mode selection bits are bit 7-5 of the Extended Control Register.

Data and ecpAFifo Port

Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are output to the PD0-PD7 ports. During a read operation, ports PD0-PD7 are read and output to the host. The bit definitions are as follows:

7 6 5 4 3 2 1 0

PD0 PD1

PD2 PD3 PD4 PD5 PD6 PD7

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Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of this register is defined only for the forward direction. The bit definitions are as follows:

7 6 5 4 3 2 1 0

Address or RLE

Address/RLE

Device Status Register (DSR)

These bits are at low level during a read of the Printer Status Register. The bits of this status register are defined as follows:

7 6 5 4 3 2 1 0

nFault Select PError nAck nBusy

11 1

Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read.

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Device Control Register (DCR)

The bit definitions are as follows:

7 6 5 4 3 2 1 0

1 1

Strobe

Autofd

nInit Select In

Direction

AckInt En

Bit 6,7: These two bits are logic one during a read and cannot be written. Bit 5: This bit has no effect and the direction is always out if mode = 000 or mode = 010. Direction

is valid in all other modes.

0 The parallel port is in output mode. 1 The parallel port is in input mode.

Bit 4: Interrupt request enable. When this bit is set to a high level, it may be used to enable

interrupt requests from the parallel port to the CPU due to a low to high transition on the nACK input.

Bit 3: This bit is inverted and output to the nSLIN output.

0 The printer is not selected.

1 The printer is selected. Bit 2: This bit is output to the nINIT output. Bit 1: This bit is inverted and output to the nAFD output. Bit 0: This bit is inverted and output to the nSTB output.

cFifo (Parallel Port Data FIFO) Mode = 010

This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO. Transfers to the FIFO are byte aligned.

ecpDFifo (ECP Data FIFO) Mode = 011

When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned.

When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system.

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tFifo (Test FIFO Mode) Mode = 110

Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed on the parallel port data lines.

cnfgA (Configuration Register A) Mode = 111

This register is a read-only register. When it is read, 10H is returned. This indicates to the system that this is an 8-bit implementation.

cnfgB (Configuration Register B) Mode = 111

The bit definitions are as follows:

7 6 5 4 3 2 1 0

1 1 1

intrValue

compress

IRQx 0 IRQx 1 IRQx 2

Bit 7: This bit is read-only. It is at low level during a read. This means that this chip does not

support hardware RLE compression. Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts. Bit 5-3: Reflect the IRQ resource assigned for ECP port.

cnfgB[5:3] IRQ resource

000 Reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5

Bit 2-0: These five bits are at high level during a read and can be written.

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ecr (Extended Control Register) Mode = all

This register controls the extended ECP parallel port functions. The bit definitions are follows:

Empty Full

Service Intr DMA En nErrIntr En MODE MODE MODE

7 6 5 4 3 2 1 0

Bit 7-5: These bits are read/write and select the mode.

000 Standard Parallel Port mode. The FIFO is reset in this mode. 001 PS/2 Parallel Port mode. This is the same as 000 except that direction may be

used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register.

010 Parallel Port FIFO mode. This is the same as 000 except that bytes are written or

DMAed to the FIFO. FIFO data are automatically transmitted using the standard parallel port protocol. This mode is useful only when direction is 0.

011 ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed

into the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and transmitted automatically to the peripheral using ECP Protocol. When the direction is 1 (reverse direction) bytes are moved from the ECP parallel port and packed into bytes in the ecpDFifo.

100 Selects EPP Mode. In this mode, EPP is active if the EPP supported option is

selected. 101 Reserved. 110 Test Mode. The FIFO may be written and read in this mode, but the data will not be

transmitted on the parallel port. 111 Configuration Mode. The confgA and confgB registers are accessible at 0x400 and

0x401 in this mode.

Bit 4: Read/Write (Valid only in ECP Mode)

1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted

(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.

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Bit 3: Read/Write

1 Enables DMA. 0 Disables DMA unconditionally.

Bit 2: Read/Write

1 Disables DMA and all of the service interrupts. 0 Enables one of the following cases of interrupts. When one of the service interrupts

has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to

0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.

(a) dmaEn = 1:

During DMA this bit is set to a 1 when terminal count is reached.

(b) dmaEn = 0 direction = 0:

This bit is set to 1 whenever there are writeIntr Threshold or more bytes free in the

FIFO.

This bit is set to 1 whenever there are readIntr Threshold or more valid bytes to be

read from the FIFO.

Bit 1: Read only

0 The FIFO has at least 1 free byte. 1 The FIFO cannot accept another byte or the FIFO is completely full.

Bit 0: Read only

0 The FIFO contains at least 1 byte of data. 1 The FIFO is completely empty.

Bit Map of ECP Port Registers

D7 D6 D5 D4 D3 D2 D1 D0 NOTE

data PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 ecpAFifo Addr/RLE Address or RLE field 2 dsr nBusy nAck PError Select nFault 1 1 1 1 dcr 1 1 Direction ackIntEn SelectIn nInit autofd strobe 1 cFifo Parallel Port Data FIFO 2 ecpDFifo ECP Data FIFO 2 tFifo Test FIFO 2 cnfgA 0 0 0 1 0 0 0 0 cnfgB compress intrValue 1 1 1 1 1 1 ecr MODE nErrIntrEn dmaEn serviceIntr full empty

Notes:

1. These registers are available in all modes.

2. All FIFOs use one common 16-byte FIFO.

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ECP Pin Descriptions

NAME TYPE DESCRIPTION

nStrobe (HostClk) O The nStrobe registers data or address into the slave on

the asserting edge during write operations. This signal

handshakes with Busy. PD<7:0> I/O These signals contains address or data or RLE data. nAck (PeriphClk) I This signal indicates valid data driven by the peripheral

when asserted. This signal handshakes with nAutofd in

reverse. Busy (PeriphAck) I This signal desserts to indicate that the peripheral can

accept data. It indicates whether the data lines contain

ECP command information or data in the reverse

direction. When in reverse direction, normal data are

transferred when Busy (PeriphAck) is high and an 8-bit

command is transferred when it is low. PError (nAckReverse) I This signal is used to acknowledge a change in the

direction of the transfer (asserted = forward). The

peripheral drives this signal low to acknowledge

nReverseRequest. The host relies upon nAckReverse to

determine when it is permitted to drive the data bus. Select (Xflag) I Indicates printer on line. nAutoFd (HostAck) O Requests a byte of data from the peripheral when it is

asserted. This signal indicates whether the data lines

contain ECP address or data in the forward direction.

When in forward direction, normal data are transferred

when nAutoFd (HostAck) is high and an 8-bit command

is transferred when it is low. nFault (nPeriphRequest) I Generates an error interrupt when it is asserted. This

signal is valid only in the forward direction. The

peripheral is permitted (but not required) to drive this

pin low to request a reverse transfer during ECP Mode. nInit (nReverseRequest) O This signal sets the transfer direction (asserted =

reverse, deasserted = forward). This pin is driven low to

place the channel in the reverse direction. nSelectIn (ECPMode) O This signal is always deasserted in ECP mode.

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ECP Operation

The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation, it is necessary to initialize some of the port bits. The following are required:

- Set direction = 0, enabling the drivers.

- Set strobe = 0, causing the nStrobe

signal to default to the deasserted state.

- Set autoFd = 0, causing the nAutoFd signal to default to the deasserted state.

- Set mode = 011 (ECP Mode)

ECP address/RLE bytes or data bytes may be sent automatically by writing the ecpAFifo or ecpDFifo, respectively.

Mode Switching Software will execute P1284 negotiation and all operations prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ECP port only in the data transfer phase (mode 011 or 010).

If the port is in mode 000 or 001 it may switch to any other mode. If the port is not in mode 000 or 001 it can only be switched into mode 000 or

001. The direction can be changed only in mode

001. When in extended forward mode, the software

should wait for the FIFO to be empty before switching back to mode 000 or 001. In ECP reverse mode the software waits for all the data to be read from the FIFO before changing back to mode 000 or 001.

Command/Data ECP mode allows the transfer of normal 8-bit data or 8-bit commands. In the forward direction, normal data are transferred when HostAck is high and an 8-bit command is transferred when HostAck is low. The most significant bits of the command indicate whether it is a run-length count (for compression) or a channel address.

In the reverse direction, normal data are transferred when PeriphAck is high and an 8-bit command is transferred when PeriphAck is low. The most significant bit of the command is always zero.

Data Compression The FDC87W22 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo.

FIFO Operation

The FIFO threshold is set in configuration register 5. All data transfers to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used by selecting the Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled.

DMA Transfers

DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO

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using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an interrupt is generated and serviceIntr is asserted, which will disable the DMA.

Programmed I/O (NON-DMA) Mode

The ECP or parallel port FIFOs can also be operated using interrupt driven programmed I/O. Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located at 400H, or to/from the tFifo at 400H. The host must set the direction, state, dmaEn = 0 and serviceIntr = 0 in the programmed I/O transfers.

The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode.

Extension FDD Mode (EXTFDD)

In this mode, the FDC87W22 changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 7A.

After the printer interface is set to EXTFDD mode, the following occur:

1. Pins nMOB and nDSB will be forced to inactive state.

2. Pins, nDSKCHG, nRDATA, nWP, nTRAK0, nINDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC.

3. Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output.

4. If the parallel port is set to EXTFDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.

Extension 2FDD Mode (EXT2FDD)

In this mode, the FDC87W22 changes the printer interface pins to FDC input/output pins, allowing the user to install two external floppy disk drives through the DB-25 printer connector to replace internal floppy disk drives A and B. The pin assignments for the FDC input/output pins are shown in Table 7A.

After the printer interface is set to EXTFDD mode, the following occur:

1. Pins nMOA, nDSA, nMOB, and nDSB will be forced to inactive state.

2. Pins

nDSKCHG

, nRDATA, nWP, nTRAK0, and nINDEX will be logically ORed with pins PD4-PD0 to serve as input signals to the FDC.

3. Pins PD4-PD0 each will have an internal resistor of about 1K ohm to serve as pull-up resistor for FDD open drain/collector output.

4. If the parallel port is set to EXT2FDD mode after the system has booted DOS or another operating system, a warm reset is needed to enable the system to recognize the extension floppy drive.

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Extension Adapter Mode (EXTADP) (Patent Pending)

In this mode, the FDC87W22 redefines the printer interface pins for use as an extension adapter, allowing a pocket peripheral adapter card to be installed through the DB-25 printer connector. The pin assignments for the extension adapter are shown in table 7A.

- XDO-XD7 are the system data bus for the extension adapter.

- XA0-XA2 are the system address bus.

- nXWR and nXRD are the I/O read/write

commands with address comparing match or in DMA access mode.

- nXDACK, XTC, and XDRQ are used in conjunction with nPDACKX, TC, and PDRQX to execute a DMA cycle.

The extension adapter can issue a DMA request by setting pin XDRQ high, thus sending the FDC87W22 output to the host system by pin PDRQX. The DMA controller should recognize the DMA request and output a relative DACK to pin nPDACKX of the FDC87W22, which will output the DACK without any change from pin nXDACK to the extension adapter. Once the DMA transfer is completed, a terminal count (TC) should be issued from the DMA controller to pin TC of FDC87W22 and output to the extension adapter via pin XTC. XIRQ is the interrupt request of the extension adapter. The value of XIRQ coming from the extension adapter will directly pass through pin IRQ7 to the host system.

XIRQ and IRQ7, nXDACK and nPDACKX, and XDRQ and PDRQX are three input/output pairs of FDC87W22 pins. Although these pins are defined as DMA and interrupt functions, they can be redefined by users for other specific functions.

Operation

The idea behind EXTADP mode is to treat the parallel port DB-25 connector as an ISA slot, except that its addresses are not issued to the extension adapter. The operation of EXTADP mode is described below:

1. Set the FDC87W22 to EXTADP mode by programming bit 7 of CR7 as low and bit 3 and bit 2 of CR0 as high and low, respectively.

2. The FDC87W22 CR2 is an address register that records the address of the extension adapter. When the desired address is written into CR2, pins nXWR and nXRD of the FDC87W22 will simultaneously go low and the desired address will also appear on the printer data bus PD7-PD0. Users can logically OR these two signals as an initial reset.

3. After the above two steps, every time the host system issues an IOR or IOW command, the FDC87W22 will compare the I/O address with the CR2 register. If the comparision matches, the data, low bits addresses (XA2-XA0), and nXWR/nXRD will be presented on the parallel port DB-25 connector.

4. DMA operations are handled in the same way as item 3, except that the relevant nPDACKX, PDRQX will be active on the DB25 connector.

Joystick Mode (Patent pending)

The joystick mode allows users to plug a joystick into the parallel port DB-25 connector. The pin definitions are shown in Table 7A.

- Pins nNSTB, nAFD, nNSLIN, and nINIT output high as a voltage supply to the joystick.

- Pins PD5 and PD4 are the button input of the joystick.

- Pins PD1 and PD0 are the X/Y axis paddle input of the joystick.

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- There are two one-shot timers (556) inside the FDC87W22 for use with the joystick.

Game Port Decoder

The FDC87W22 provides nGMRD and nGMWR pins that decode game port address as specified in CR1E and I/O read/write commands.

If the host issues nIOR and the specified address, the nGMRD pin is low active; if it issues nIOW and the specified address, the nGMWR pin is low active.

Plug and Play Configuration

A powerful new plug-and-play function has been built into the FDC87W22 to help simplify the task of setting up a computer environment. With appropriate support from BIOS manufacturers, the system designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT, UART, IDE, and game port) in the PC's I/O space (100H - 3FFH). In addition, the FDC87W22 also provides 8 interrupt requests and 3 DMA pairs for designers to assign in interfacing FDCs, UARTs, and PRTs.

Hence this powerful I/O chip offers greater flexibility for system designers.

The PnP feature is implemented through a set of Extended Function Registers (CR1E and CR20 to 29). Details on configuring these registers are given in Section 8. The default values of these PnP-related registers set the system to a configuration compatible with environments designed with previous Winbond I/O chips.

Extended Function Registers

The FDC87W22 provides many configuration registers for setting up different types of configurations. After power-on reset, the state of the hardware setting of each pin will be latched by the relevant configuration register to allow the FDC87W22 to enter the proper operating configuration. To protect the chip from invalid reads or writes, the configuration registers cannot be accessed by the user.

There are four ways to enable the configuration registers to be read or written. HEFERE (CR0C bit 5) and HEFRAS (CR16 bit 0) can be used to select one out of these four methods of entering the Extended Function mode as follows:

HEFRAS HEFERE Address and Value

0 0 write 88H to the location 250H 0 1 write 89H to the location 250H (power-on default) 1 0 write 86H to the location 3F0H twice 1 1 write 87H to the location 3F0H twice

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First, a specific value must be written once (88H/89H) or twice (86H/87H) to the Extended Functions Enable Register (I/O port address 250H or 3F0H). Second, an index value (00H17H, 1EH, 20H-29H) must be written to the Extended Functions Index Register (I/O port address 251H or 3F0H) to identify which configuration register is to be accessed. The designer can then access the desired configuration register through the Extended Functions Data Register (I/O port address 252H or 3F1H).

After programming of the configuration register is finished, an additional value should be written to EFERs to exit the Extended Function mode to prevent unintentional access to those configuration registers. In the case of EFER at 250H, this additional value can be any value other than 88H if HEFERE = 0 and 89H if HEFERE = 1. While EFER is at 3F0H, this additional value must be AAH. The designer can also set bit 6 of CR9 (LOCKREG) to high to protect the configuration registers against accidental accesses.

The configuration registers can be reset to their default or hardware settings only by a cold reset (pin MR = 1). A warm reset will not affect the configuration registers.

Extended Functions Enable Registers (EFERs)

After a power-on reset, the FDC87W22 enters the default operating mode. Before the FDC87W22 enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers. On a PC/AT system, their port addresses are 250H or 3F0H (as described in the above section).

Extended Function Index Registers (EFIRs), Extended Function Data Registers (EFDRs)

After the extended function mode is entered, the Extended Function Index Register (EFIR) must be loaded with an index value (0H, 1H, 2H, ..., or 29H) to access Configuration Register 0 (CR0), Configuration Register 1 (CR1), Configuration Register 2 (CR2), and so forth through the Extended Function Data Register (EFDR). The EFIRs are write-only registers with port address 251H or 3F0H (as described in section 8.0) on PC/AT systems; the EFDRs are read/write registers with port address 252H or 3F1H (as described in section 8.0) on PC/AT systems. The function of each configuration register is described below.

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Configuration Register 0 (CR0), default = 00H

When the device is in Extended Function mode and EFIR is 0H, the CR0 register can be accessed through EFDR. The bit definitions for CR0 are as follows:

7 6 5 4 3 2 1 0

OCSS0 OCSS1

reserved reserved

PRTMODS0 PRTMODS1

Bit 7-Bit 4: Reserved. PRTMOD1 PRTMOD0 (Bit 3, Bit 2): These two bits and PRTMOD2 (CR9 bit7) determine the parallel port mode of the FDC87W22.

PRTMODS2

(BIT 7 OF CR9)

PRTMOD1

(BIT 3 OF CR0)

PRTMODS0

(BIT 2 OF CR0)

0 0 1 EXTFDC 0 1 0 EXTADP 0 1 1 EXT2FDD 1 0 0 JOYSTICK 1 0 1 EPP/SPP 1 1 0 ECP 1 1 1 ECP/EPP

01 Extension FDD Mode (EXTFDD), PRTMOD2 = 0 10 Extension Adapter Mode (EXTADP), PRTMOD2 = 0 11 Extension 2FDD Mode (EXT2FDD), PRTMOD2 = 0 00 JOYSTICK Mode, PRTMOD2 = 1 01 EPP Mode and SPP Mode, PRTMOD2 = 1 10 ECP Mode, PRTMOD2 = 1 11 ECP Mode and EPP Mode, PRTMOD2 = 1

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OSCS1, OSCS0 (Bit 1, Bit 0): These two bits and OSCS2 (CR6 bit 6) are used to select one of the FDC87W22's power-down functions. These bits may be programmed in four different ways:

00 Default power-on state after power-on reset (OSCS2 = 0). 00 OSC on, 24 MHz clock is stopped internally (OSCS2 = 1). Clock can be restarted by

clearing OSCS2.

01 Immediate power-down (IPD) state, OSCS2 = 0

When bit 0 is 1 and bit 1 is set to 0, the FDC87W22 will stop its oscillator and enter power-down mode immediately. The FDC87W22 will not leave the power-down mode until either a system power-on reset from the MR pin or these two bits are used to program the chip back to power-on state. After leaving the power-down mode, the FDC87W22 must wait 128 mS for the oscillator to stabilize.

10 Standby for automatic power-down (APD), OSCS2 = 0

When bit 1 is set to 1 and bit 0 is set to 0, the FDC87W22 will stand by for automatic power-down. A power-down will occur when the following conditions obtain:

• FDC not busy

• FDD motor off

• Interrupt source of line status, modem status, and data ready is inactive (neglecting IER

enable/disable)

• Master Reset inactive

• SOUTA and SOUTB in idle state

• SINA and SINB in idle state

• No register read or write to chip

If all of these conditions are met, a counter begins to count down. While the timer is counting down, the FDC87W22 remains in normal operating mode, and if any of the above conditions changes, the counter will be reset. If the set time (set by bit 7 and bit 6 of CR8) elapses without a change in any of the above conditions, bits 1 and 0 will be set to (1, 1) and the chip will enter automatic power-down mode. The oscillator of the FDC87W22 will remain running, but the internal clock will be disabled to save power. Once the above conditions are no longer met, the internal clock will be resupplied and the chip will return to normal operation.

11 Automatic power-down (ADP) state, OSCS2 = 0

The FDC87W22 enters this state automatically after the counter described above has counted down. If there is a change in any of the conditions listed above, the FDC87W22 's clock will be restarted and bits 1 and 0 will be set to (1, 0), i.e., standby for automatic power-down. When the clock is restarted, the chip is ready for normal operation, with no need to wait for the oscillator to stabilize.

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Configuration Register 1 (CR1), default = 00H

When the device is in Extended Function mode and EFIR is 01H, the CR1 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

reserved reserved reserved reserved reserved reserved reserved ABCHG

Bit 0-bit 6: Reserved. ABCHG (Bit 7): This bit enables the FDC AB Change Mode. Default to be enabled at power-on reset.

0 Drives A and B assigned as usual 1 Drive A and drive B assignments exchanged

Configuration Register 2 (CR2), default = 00H

When the device is in Extended Function mode and EFIR is 02H, the CR2 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

CEA EA3 EA4 EA5 EA6 EA7 EA8 EA9

When the FDC87W22 is programmed into extension adapter mode, the contents of this register are a base address for the extension adapter. When base addresses EA3-EA9 are written into CR2, both the nXRD and nXWR pins will be active low simultaneously and an adapter connected to the parallel port can latch the same base address through pins XD1-XD7. After the base address is latched into CR2, a subsequent read/write cycle to this same base address will generate an nXRD or nXWR signal.

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If CEA is set to 0, then the FDC87W22 will compare system addresses SA9-SA3 with EA9-EA3 to generate a compare-equal signal for this read/write command to access the Extension adapter. If CEA is set to 1, then only EA9-EA4 are used in this comparison.

Configuration Register 3 (CR3), default = 30H

When the device is in Extended Function mode and EFIR is 03H, the CR3 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

SUBMIDI SUAMIDI reserved reserved GMODS EPPVER GMENL reserved

SUBMIDI (Bit 0): This bit selects the clock divide rate of UARTB.

0 Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default) 1 Enables MIDI support, UARTB clock = 24 MHz divided by 12

SUAMIDI (Bit 1): This bit selects the clock divide rate of UARTA.

0 Disables MIDI support, UARTA clock = 24 MHz divided by 13 (default)

1 Enables MIDI support, UARTA clock = 24 MHz divided by 12 Bit 2-bit 3: Reserved. GMODS (Bit 4):

This bit selects the adapter mode or portable mode.

0 Selects the portable mode. Pins 41 and 39 will function as PFDCEN and PEXTEN

1 Selects the adapter mode. Pins 41 and 39 will function as nGMRD and nGMWR Note: GMDRQ (CR16 bit 3) has higher precedence over this bit. That is, GMODS selection is only

valid when GMGRQ = 0.

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EPPVER (Bit 5): This bit selects the EPP version of parallel port:

0 Selects the EPP 1.9 version

1 Selects the EPP 1.7 version (default) Bit 7-bit 6: Reserved.

Configuration Register 4 (CR4), default = 00H

When the device is in Extended Function mode and EFIR is 04H, the CR4 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

URBTRI URATRI GMTRI PRTTRI URBPWD URAPWD GMPWD PRTPWD

PRTPWD (Bit 7):

0 Supplies power to the parallel port (default)

1 Puts the parallel port in power-down mode GMPWD (Bit 6):

0 Supplies power to the game port (default)

1 Puts the game port in power-down mode URAPWD (Bit 5):

0 Supplies power to COMA (default)

1 Puts COMA in power-down mode URBPWD (Bit 4):

0 Supplies power to COMB (default)

1 Puts COMB in power-down mode PRTTRI (Bit 3): This bit enables or disables the tri-state outputs of parallel port in power-down mode.

0 The output pins of the parallel port will not be tri-stated when parallel port is in

power-down mode. (default)

1 The output pins of the parallel port will be tri-stated when parallel port is in power-

down mode. GMTRI (Bit 2): This bit enables or disables the tri-state outputs of the game port in power-down mode.

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0 The output pins of the game port will not be tri-stated when game port is in power-

down mode. (default)

1 The output pins of the game port will be tri-stated when game port is in power-down

mode. URATRI (Bit 1): This bit enables or disables the tri-state outputs of UARTA in power-down mode.

0 The output pins of UARTA will not be tri-stated when UARTA is in power-down

mode.

1 The output pins of UARTA will be tri-stated when UARTA is in power-down mode. URBTRI (Bit 0): This bit enables or disables the tri-state outputs of UARTB in power-down mode.

0 The output pins of UARTB will not be tri-stated when UARTB is in power-down

mode.

1 The output pins of UARTB will be tri-stated when UARTB is in power-down mode.

Configuration Register 5 (CR5), default = 00H

When the device is in Extended Function mode and EFIR is 05H, the CR5 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

ECPFTHR0 ECPFTHR1

ECPFTHR2 Reserved

Reserved Reserved Reserved

ECPFTHR3

Bit 7-4: Reserved ECPFTHR3-0 (bit 3-0): These four bits define the FIFO threshold for the ECP mode parallel port.

The default value is 0000 after power-up.

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Configuration Register 6 (CR6), default = 00H

When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

FDCTRI IDEPWD FDCPWD FIPURDWM SEL4FDD OSCS2 Reserved

IDETRI

Bit 7: Reserved OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit 1, 0 of CR0) select one of the FDC87W22's power-down functions. Refer to descriptions of CR0. (Default to be 0)

SEL4FDD (Bit 5): Selects four FDD mode

0 Selects two FDD mode (default, see Table 9A) 1 Selects four FDD mode

nDSA, nDSB, nMOA and nMOB output pins are encoded as show in Table 9B to select four drives.

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Table 9A

DO REGISTER ( 3F2H ) nMOB nMOA nDSB nDSA DRIVE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 SELECTED

0 0 0 0 0 0 1 1 1 1 -0 0 0 1 0 0 1 0 1 0 FDD A 0 0 1 0 0 1 0 1 0 1 FDD B 0 1 0 0 0 1 1 1 1 1 -1 0 0 0 1 1 1 1 1 1 --

Table 9B

DO REGISTER ( 3F2H ) nMOB nMOA nDSB nDSA DRIVE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 1 Bit 0 SELECTED

0 0 0 0 X X 1 1 x x -0 0 0 1 0 0 0 0 0 0 FDD A 0 0 1 0 0 1 0 0 0 1 FDD B 0 1 0 0 1 0 0 0 1 0 FDD C 1 0 0 0 1 1 0 0 1 1 FDD D

FIPURDWN (Bit 4): This bit controls the internal pull-up resistors of the FDC input pins nRDATA, nINDEX, nTRAK0, nDSKCHG, and nWP.

0 The internal pull-up resistors of FDC are turned on. (default) 1 The internal pull-up resistors of FDC are turned off.

FDCPWD (Bit 3): This bit controls the power to the FDC.

0 Power is supplied to the FDC. (default) 1 Puts the FDC in power-down mode.

IDEPWD (Bit 2): This bit controls the power of the IDE.

0 Power is supplied to the IDE. (default) 1 Puts the IDE in power-down mode.

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FDCTRI (Bit 1): This bit enables or disables the tri-state outputs of the FDC in power-down mode.

0 The output pins of the FDC will not be tri-stated when FDC is in power-down mode.

1 The output pins of the FDC will be tri-stated when FDC is in power-down mode. IDETRI (BIt 0):

This bit enables or disables the tri-state outputs of the IDE in power-down mode.

0 The output pins of the IDE will not be tri-stated when IDE is in power-down mode.

1 The output pins of the IDE will be tri-stated when IDE is in power-down mode.

Configuration Register 7 (CR7), default = 00H

When the device is in Extended Function mode and EFIR is 07H, the CR7 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type 1

FDD A type 1, 0 (Bit 1, 0): These two bits select the type of FDD A.

00 Selects normal mode. When nRWC = 0, the data transfer rate is 250 Kb/s. When

nRWC= 1, the data transfer rate is 500 Kb/s.

Three mode FDD select (EN3MODE = 1):

01 nRWC= 0, selects 1.2 MB high-density FDD. 10 nRWC= 1, selects 1.44 MB high-density FDD. 11 Don't care nRWC, selects 720 KB double-density FDD.

FDD B type 1, 0 (Bit 3, 2): These two bits select the type of FDD B.

00 Selects normal mode. When nRWC = 0, the data transfer rate is 250 Kb/s. When

nRWC= 1, the data transfer rate is 500 Kb/s.

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Three mode FDD select (EN3MODE = 1):

01 nRWC= 0, selects 1.2 MB high-density FDD. 10 nRWC = 1, selects 1.44 MB high-density FDD. 11 Don't care nRWC, selects 720 KB double-density FDD.

FDD C type 1, 0 (Bit 5, 4): These two bits select the type of FDD C.

00 Selects normal mode. When nRWC = 0, the data transfer rate is 250 kb/s. When

nRWC = 1, the data transfer rate is 500 kb/s.

Three mode FDD select (EN 3 MODE = 1):

01 nRWC = 0, selects 1.2 MB high-density FDD. 10 nRWC = 1, selects 1.44 MB high-density FDD. 11 Don't care nRWC, selects 720 KB double-density FDD.

FDD D type 1, 0 (Bit 7, 6): These two bits select the type of FDD D.

00 Selects normal mode. When nRWC = 0, the data transfer rate is 250 Kb/s. When

nRWC = 1, the data transfer rate is 500 Kb/s.

Three mode FDD select (EN3MODE = 1):

01 nRWC = 0, selects 1.2 MB high-density FDD. 10 nRWC = 1, selects 1.44 MB high-density FDD. 11 Don't care nRWC, selects 720 KB double-density FDD.

Configuration Register 8 (CR8), default = 00H

When the device is in Extended Function mode and EFIR is 08H, the CR8 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1

DISFDDWR APDTMS2

APDTMS1

SWWP

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APDTMS2 APDTMS1 (Bit 6, 7): These two bits select the count-down time of the automatic power-down mode counter.

00 4 seconds 01 32 seconds 10 64 seconds 11 4 minutes

DISFDDWR (Bit 5): This bit enables or disables FDD write data.

0 Enables FDD write 1 Disables FDD write (forces pins nWE, nWD to stay high)

Once this bit is set high, the FDC operates normally, but because pin nWE is inactive, the FDD will not write data to diskettes. For example, if a diskette is formatted with DISFDDWR = 1, after the format command has been executed, messages will be displayed that appear to indicate that the format is complete. If the diskette is removed from the disk drive and inserted again, however, typing the DIR command will reveal that the contents of the diskette have not been modified and the diskette was not actually reformatted.

This is because as the operating system (e.g., DOS) reads the diskette files, it keeps the files in memory. If there is a write operation, DOS will write data to the diskette and memory simultaneously. When DOS wants to read the diskette, it will first search the files in memory. If DOS finds the file in memory, it will not issue a read command to read the diskette. When DISFDDWR = 1, DOS still writes data to the diskette and memory, but only the data in memory are updated. If a read operation is performed, data are read from memory first, and not from the diskette. The action of removing the diskette from the drive and inserting it again forces the nDSKCHG pin active. DOS will then read the contents of the diskette and will show that the contents have not been modified. The same holds true with write commands.

The disable FDD write function allows users to protect diskettes against computer viruses by ensuring that no data are written to the diskette.

SWWP (Bit 4):

0 Normal, use nWP to determine whether the FDD is write-protected or not 1 FDD is always write-protected

Media ID 1 Media ID 0 (Bit 3, 2): These two bits hold the media ID bit 1, 0 for three mode

Floppy Boot Drive 1 Floppy Boot Drive 0 (bit 1, 0) These two bits hold the value of floppy boot drive 1 and drive 0 for three mode

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Configuration Register 9 (CR9), default = 0AH

When the device is in Extended Function mode and EFIR is 09H, the CR9 register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

CHIP ID0 CHIP ID1 CHIP ID2 CHIP ID3 Reserved

LOCKREG

EN3MODE

PRTMODS2

PRTMODS2 (Bit 7): This bit and PRTMODS1, PRTMODS0 (bits 3, 2 of CR0) select the operating mode of the FDC87W22. Refer to the descriptions of CR0.

LOCKREG (Bit 6): This bit enables or disables the reading and writing of all configuration registers.

0 Enables the reading and writing of CR0-CR29

1 Disables the reading and writing of CR0-CR29 (locks FDC87W22 extension

functions)

EN3MODE (Bit 5): This bit enables or disables three mode FDD selection. When this bit is high, it enables the read/write 3F3H register.

0 Disables 3 mode FDD selection

1 Enables 3 mode FDD selection When three mode FDD function is enabled, the value of nRWC depends on bit 5 and bit 4 of TDR(3F3H). The values of nRWC and their meaning are shown in Table 10.

Table 10

BIT 5 OF TDR BIT 4 OF TDR nRWC nRWC = 0 nRWC= 1

0 0 Normal 250K bps 500K bps 0 1 0 1.2 M FDD X 1 0 1 X 1.4M FDD 1 1 X X X

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Bit 4: Reserved. CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-0): These four bits are read-only bits that contain chip identification information. The value is 0AH for FDC87W22 during a read.

Configuration Register A (CRA), default = 1FH

When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed through EFDR. The bit definitions are as follows:

7 6 5 4 3 2 1 0

PEXTECPP PEXT ECP PEXT EPP PEXT ADP

PEXT ACT

PDCACT PDIRHOP

PFDCACT

PFDCACT (Bit 7): This bit controls whether PFDCEN (pin 41) is active high or low in portable mode.

0 PFDCEN is active low 1 PFDCEN is active high

PEXTACT (Bit 6): This bit controls whether PEXTEN (pin 39) is active high or low in portable mode. This pin can also reflect the mode of the parallel port: EXTADP mode, EPP mode, ECP mode, or ECP/EPP mode, or any combination of these modes.

0 PEXTEN is active low 1 PEXTEN is active high

Bit 5: Reserved. PDCACT (Bit 4):

This bit controls whether the PDCIN pin is active high or low.

0 PDCIN is active low 1 PDCIN is active high

PEXTADP (Bit 3): This bit controls whether the PEXTEN pin is active in EXTADP mode.

0 PEXTEN is not active in EXTADP mode 1 PEXTEN is active in EXTADP mode

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PEXTEPP (Bit 2): This bit controls whether the PEXTEN pin is active in EPP mode.

0 PEXTEN is not active in EPP mode 1 PEXTEN is active in EPP mode

PEXTECP (Bit 1): This bit controls whether the PEXTEN pin is active in ECP mode.

0 PEXTEN is not active in ECP mode 1 PEXTEN is active in ECP mode

PEXTECPP (Bit 0): This bit controls whether the PEXTEN pin is active in ECP/EPP mode.

0 PEXTEN is not active in ECP/EPP mode 1 PEXTEN is active in ECP/EPP mode

Configuration Register B (CR0B), default = 0CH

When the device is in Extended Function mode and EFIR is 0BH, the CRB register can be accessed through EFDR. The bit definitions are as follows:

Bit 7-5: These bits are reserved and are logic 0 during a read. ENIFCHG (Bit 4):

This bit is active high. When active, it enables host interface mode change, which is determined by IDENT (Bit 3) and MFM (Bit 2).

IDENT (Bit 3): This bit indicates the type of drive being accessed and changes the level on nRWC (pin 87).

0 nRWC will be active low for high data rates (typically used for 3.5" drives) 1 nRWC will be active high for high data rates (typically used for 5.25" drives)

When hardware reset or ENIFCHG is a logic 1, IDENT and MFM select one of three interface modes, as shown in Table 11.

1234567 0

nDRV2EN INVERTZ

IDENT

ENIFCHG

MFM

0 0 0

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Table 11

IDENT MFM INTERFACE

0 0 Model 30 mode 0 1 PS/2 mode 1 0 AT mode 1 1 AT mode

MFM (Bit 2): This bit and IDENT select one of the three interface modes (PS/2 mode, Model 30, or PC/AT mode).

INTVERTZ (Bit 1): This bit determines the polarity of all FDD interface signals.

0 FDD interface signals are active low 1 FDD interface signals are active high

nDRV2EN (Bit 0): PS/2 mode only When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A.

Configuration Register C (CR0C), default = 28H

When the device is in Extended Function mode and EFIR is 0CH, the CR0C register can be accessed through EFDR. The bit definitions are as follows:

34567

TX2INV RX2INV Reserved URIRSEL Reserved HEFERE TURB TURA

TURA (bit 7):

0 The clock source of UART A is 1.8462 MHZ (24 MHz divide 13) (default)

1 The clock source of UART A is 24 MHz, it can make the baudrate of UART A up to

1.5 MHz

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TURB (bit 6):

0 The clock source of UART B is 1.8462 MHz (24 MHz divide 13) (default)

1 The clock source of UART B is 24 MHz, it can make the baudrate of UART A up to

1.5 MHz

HEFERE (bit 5): This bit combines with HEFRAS (CR16 bit 0) to define how to enable Extended

Function Registers.

HEFRAS HEFERE Address and Value

0 0 write 88H to the location 250H 0 1 write 89H to the location 250H (default) 1 0 write 86H to the location 3F0H twice

1 1 write 87H to the location 3F0H twice The default value of HEFERE is 1. Bit 4: Reserved. URIRSEL (bit 3):

0 Select UART B as IR function. 1 Select UART B as normal function.

The default value of URIRSEL is 1. Bit 2: Reserved. RX2INV (bit 1):

0 The SINB pin of UART B function or IRRX pin of IR function in normal condition. 1 Inverse the SINB pin of UART B function or IRRX pin of IR function TX2INV (bit 0): 0 The SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1 Inverse the SOUTB pin of UART B function or IRTX pin of IR function.

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Configuration Register D (CR0D), default = a3H

When the device is in Extended Function mode and EFIR is 0DH, the CR0D register can be accessed through EFDR. The bit definitions are as follows:

34567

SIRTX1

SIRTX0

SIRRX1

SIRRX0

HDUPLX

IRMODE2

IRMODE1

IRMODE0

SIRTX1 (bit 7): IRTX pin selection bit 1 SIRTX0 (bit 6): IRTX pin selection bit 0

SIRTX1 SIRTX0 IRTX output on pin

0 0 disabled 0 1 IRTX1 (pin 43) 1 0 IRTX2 (pin 95)

1 1 disabled SIRRX1 (bit 5): IRRX pin selection bit 1 SIRRX0 (bit 4): IRRX pin selection bit 0

SIRRX1 SIRRX0 IRRX input on pin

0 0 disabled

0 1 IRRX1 (pin 42)

1 0 IRRX2 (pin 94)

1 1 disabled

HDUPLX (bit 3):

0 The IR function is Full Duplex. 1 The IR function is Half Duplex.

IRMODE2 (bit 2): IR function mode selection bit 2 IRMODE1 (bit 1): IR function mode selection bit 1

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IRMODE0 (bit 0): IR function mode selection bit 0

IR MODE IR FUNCTION IRTX IRRX

00X Disable tri-state high 010* IrDA

Active pulse 1.6 µS

Demodulation into SINB 011* IrDA Active pulse 3/16 bit time Demodulation into SINB 100 ASK-IR Inverting IRTX pin routed to SINB 101 ASK-IR Inverting IRTX & 500 kHz clock routed to SINB 110 ASK-IR Inverting IRTX Demodulation into SINB 111* ASK-IR Inverting IRTX & 500 kHz clock Demodulation into SINB

Note: The notation is normal mode in the IR function. The SIR schematic diagram for registers CRC and CRD is shown below.

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Configuration Register E (CR0E), Configuration Register F (CR0F)

Reserved for testing. Should be kept all 0's.

MUX 0

1 0

01 00 10 11

11,00

01 10

1 MUX

0 MUX

IRDA Mod.

3/16

IRDA Mod.

Mod1.6u

IRDA

IRMODE0

IRMODE2

(CRD.bit2)

URIRSEL

(CRC,bit3)

Transmission Time Frame

16550A

SIN

UART2

SOUT

RX2INV

(CRC.bit1)

URIRSEL

(CRC.bit3)

0 MUX

SIRRX1~0

CR0D.bit5,4

ASK_IR

SIN2

IRMODE1

(CRD.bit3)

HUPLX

IRMODE0

(CRD.bit0)

500kHz

MUX

(CRD.bit1)

IRMODE2 (CRD.bit2)

IRMODE2,1=00

(CRD.bit0)

disable IRTX1 IRTX2

SOUT2

NCS1

IRRX1

IRRX2

+5V NCS0

+5V

SIRTX1~0

CRD.bit7,6

TX2INV CRC.bit0

MUX

IR-DA

Demodulation

(default)

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Configuration Register 10 (CR10), default = 00H

When the device is in Extended Function mode and EFIR is 10H, the CR10 register can be accessed through EFDR. The bit definitions are as follows:

34567

GIO0AD7

GIO0AD0 GIO0AD1

GIO0AD2 GIO0AD3

GIO0AD4 GIO0AD5 GIO0AD6

GIO0AD7-GIO0AD0 (bit 7-bit 0): GIOP0 (pin 92) address bit 7 - bit 0.

Configuration Register 11 (CR11), default = 00H

When the device is in Extended Function mode and EFIR is 11H, the CR11 register can be accessed through EFDR. The bit definitions are as follows:

34567

G0CADM1

GIO0AD8 GIO0AD9

GIO0AD10 Reserved

G0CADM0

Reserved Reserved

G0CADM1-G0CADM0 (bit 7-bit 6): GIOP0 address bit compare mode selection

G0CADM1 G0CADM0 GIOP0 pin

0 0 compare GIO0AD10-GIO0AD0 with SA10-SA0 0 1 compare GIO0AD10-GIO0AD1 with SA10-SA1 1 0 compare GIO0AD10-GIO0AD2 with SA10-SA2 1 1 compare GIO0AD10-GIO0AD3 with SA10-SA3

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Bit 5-bit 3: Reserved GIO0AD10-GIO0AD8 (bit 2-bit 0): GIOP0 (pin 92) address bit 10-bit 8

Configuration Register 12 (CR12), default = 00H

When the device is in Extended Function mode and EFIR is 12H, the CR12 register can be accessed through EFDR. The bit definitions are as follows:

34567

GIO1AD7

GIO1AD0 GIO1AD1

GIO1AD2 GIO1AD3

GIO1AD4 GIO1AD5 GIO1AD6

GIO1AD7-GIO1AD0 (bit 7-bit 0): GIOP1 (pin 96) address bit 7-bit 0.

Configuration Register 13 (CR13), default = 00H

When the device is in Extended Function mode and EFIR is 13H, the CR13 register can be accessed through EFDR. The bit definitions are as follows:

34567

G1CADM1

GIO1AD8 GIO1AD9 GIO1AD10 Reserved

G1CADM0

Reserved Reserved

G1CADM1-G1CADM0 (bit 7-bit 6): GIOP1 address bit compare mode selection

G1CADM1 G1CADM0 GIOP1 pin

0 0 compare GIO1AD10-GIO1AD0 with SA10-SA0 0 1 compare GIO1AD10-GIO1AD1 with SA10-SA1 1 0 compare GIO1AD10-GIO1AD2 with SA10-SA2 1 1 compare GIO1AD10-GIO1AD3 with SA10-SA3

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Bit 5- bit 3: Reserved GIO1AD10-GIO1AD8 (bit 2-it 0): GIOP1 (pin 96) address bit 10-bit 8

Configuration Register 14 (CR14), default = 00H

When the device is in Extended Function mode and EFIR is 14H, the CR14 register can be accessed through EFDR. The bit definitions are as follows:

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GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2

GIOP0MD2-GIOP0MD0 (bit 7-bit 5): GIOP0 pin mode selection

GIOP0MD2 GIOP0MD1 GIOP0MD0 GIOP0 pin

0 0

0 1

Inactive (tri-state) as a data output pin (SD0→GIOP0), when (AEN = L) AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the value of SD0 will be present on GIOP0

0 1 0

As a data input pin (GIOP0→SD0), when (AEN = L) AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the value of GIOP0 will be present on SD0

0 1 1

As a data input/output pin (GIOP0↔SD0). When (AEN = L) AND (NIOW = L) AND (SA10-0 = GIO0AD10-0), the value of SD0 will be present on GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10-0 = GIO0AD10-0), the value of GIOP0 will be present on SD0

1 X X As a Chip Select pin, the pin will be active at (AEN

= L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR (NIOW = L)

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100

GIO0CSH(bit 4):

0 The Chip Select pin will be active LOW when (AEN = L) AND (SA10-0 =

GIO0AD10-0) OR (NIOR = L) OR (NIOW = L)

1 The Chip Select pin will be active HIGH when (AEN = L) AND (SA10-0 =

GIO0AD10-0) OR (NIOR = L) OR (NIOW = L) GCS0IOR (bit 3): See below. GCS0IOW (bit 2): See below.

GCS0IOR GCS0IOW

0 0 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0)

0 1 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L)

1 0 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOR = L)

1 1 GIOP0 functions as a Chip Select pin, and will be active when

(AEN = L) AND (SA10-0 = GIO0AD10-0) AND (NIOW = L OR

NIOR = L) GDA0OPI (bit 1): See below. GDA0IPI (bit 0): See below.

GDA0OPI GDA0IPI

0 0

GIOP0 functions as a data pin, and GIOP0→SD0, SD0→GIOP0

0 1

GIOP0 functions as a data pin, and inverse GIOP0→SD0,

SD0→GIOP0

1 0

GIOP0 functions as a data pin, and GIOP0→SD0, inverse

SD0→GIOP0

1 1

GIOP0 functions as a data pin, and inverse GIOP0→SD0, inverse

SD0→GIOP0

Datasheet FDC87W22 Datasheet (Standard Microsystems Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual