Datasheet FDC655BN Datasheet (Fairchild)

Page 1
tm
FDC655BN
Single N-Channel, Logic Level, PowerTrench® MOSFET
30 V, 6.3 A, 25 mΩ Features
Max rMax rFast switchingLow gate charge High performance trchnology for extremely low rTermination is Lead-free and RoHS Compliant
= 25 mΩ at VGS = 10 V, ID = 6.3 A
DS(on)
= 33 mΩ at VGS = 4.5 V, ID = 5.5 A
DS(on)
DS(on)
General Description
This N-Channel Logic Level MOSFET is produced using Fairchild Semiconductor’s advanced Power that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance.
These devices are well suited for low voltage and battery powered applicatoins where low in-line power loss and fast switching are required.
FDC655BN Single N-Channel, Logic Level, PowerTrench
January 2010
Trench® process
D
D
G
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Drain to Source Voltage 30 V Gate to Source Voltage ±20 V
-Continuous TA = 25°C (Note 1a) 6.3
-Pulsed 20 Power Dissipation ( Note 1a) 1.6 Power Dissipation (Note 1b) 0.8 Operating and Storage Junction Temperature Range -55 to + 150 °C
= 25°C unless otherwise noted
C
D
D
S
Thermal Characteristics
R
θJA
Thermal Resistance, Junction to Ambient (Note 1a) 78 °C/W
Package Marking and Ordering Information
MOSFET
A
W
Device Marking Device Package Reel Size Tape Width Quantity
.55B FDC655BN SSOT-6
©2010 Fairchild Semiconductor Corporation FDC655BN Rev.C2
TM
1
7 ’’ 8 mm 3000 units
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Page 2
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
∆BV ∆T
I
DSS
I
GSS
DSS
DSS J
Drain to Source Breakdown Voltage I Breakdown Voltage Temperature
Coefficient Zero Gate Voltage Drain Current V Gate to Source Leakage Current V
= 250 µA, VGS = 0 V30 V
D
I
= 250 µA, referenced to 25°C 25 mV/°C
D
= 24 V, V
DS
= ±20 V, V
GS
= 0 V1µA
GS
= 0 V ±100nA
DS
On Characteristics
V
GS(th)
∆V ∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, I Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance V
I
= 250 µA, referenced to 25°C -5 mV/°C
D
V
= 10 V, ID = 6.3 A 21 25
GS
= 4.5 V, ID = 5.5 A2633
GS
= 10 V, ID = 6.3 A, T
V
GS
= 10 V, ID = 6.3 A35S
DS
= 250 µA11.93V
D
= 125°C 30 36
J
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance Output Capacitance 100 130 pF Reverse Transfer Capacitance 60 90 pF
= 15 V, VGS = 0 V,
V
DS
f = 1MHz
Gate Resistance 3.0 Ω
470 620 pF
FDC655BN Single N-Channel, Logic Level, PowerTrench
mΩV
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q Q
g g gs gd
Turn-On Delay Time Rise Time 210ns Turn-Off Delay Time 15 26 ns
= 15 V, ID = 1 A,
V
DD
V
= 10 V, R
GS
GEN
= 6 Ω
611ns
Fall Time 210ns Total Gate Charge V Total Gate Charge V Gate to Source Charge 1.4 nC
= 0 V to 10 V
GS
= 0 V to 5 V57nC
GS
V
DD
I
= 6.3 A
D
= 15 V,
913nC
Gate to Drain “Miller” Charge 1.6 nC
Drain-Source Diode Characteristics
I
S
V
SD
t
rr
Q
rr
Notes:
1: R
θJA
R
θJC
a. 78 b. 156 °C/W when mounted on a minimum pad.
2: Pulse Test: Pulse Width<300 us, Duty Cycle<2.0%.
Maximum Continuous Drain-Source Diode Forward Current 1.3 A Source-Drain Diode Forward Voltage V Reverse Recovery Time Reverse Recovery Charge 4 10 nC
is the sum of the junction-to-case and ca se-to-ambient thermal resistan ce where the case th ermal reference is defined as t he solder mountin g surface of the d rain pins. is guaranteed by design while R
°C/W when mounted on a 1 in2 pad of 2 oz copper on FR-4 boar d.
is determined by the user’s board design.
θCA
= 0 V, IS = 1.3 A (Note 2) 0.8 1.2 V
GS
= 6.3 A, di/dt = 100 A/µs
I
F
15 26 ns
MOSFET
©2010 Fairchild Semiconductor Corporation FDC655BN Rev.C2
2
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Page 3
FDC655BN Single N-Channel, Logic Level, PowerTrench
Typical Characteristics T
20
16
12
8
, DRAIN CURRENT (A)
4
D
I
0
0 0.5 1.0 1.5 2.0
Figure 1.
1.6
ID = 6.3 A
= 10 V
V
GS
1.4
1.2
1.0
NORMALIZED
0.8
DRAIN TO SOURCE ON-RESISTANCE
0.6
-75 -50 -25 0 25 50 75 100 125 150
VGS = 10 V VGS = 6 V VGS = 4.5 V
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
On Region Characteristics Figure 2.
T
, JUNCTION TEMPERATURE (
J
= 25°C unless otherwise noted
J
VGS = 3.5 V
VGS = 3 V
o
C)
5
PULSE DURATION = 80 µs
4
VGS = 3 V
DUTY CYCLE = 0.5% MAX
3
VGS = 3.5 V
2
NORMALIZED
1
DRAIN TO SOURCE ON-RESISTANCE
0
048121620
I
D
VGS = 6 V
, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 10 V
Norma l i z e d O n - Resistance
vs Drain Current and Gate Voltage
90 80
(mΩ)
70 60 50
DRAIN TO
,
40
DS(on)
r
30 20
SOURCE ON-RESISTANCE
10
246810
V
, GATE TO SOURCE VOLTAGE (V)
GS
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
ID = 6.3 A
TJ = 125 oC
TJ = 25 oC
MOSFET
Fi g ure 3 . Norm a lize d On Re s ista n ce
vs Junction Temperature
20
PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX
16
V
= 5 V
DS
12
8
, DRAIN CURRENT (A)
4
D
I
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VGS, GATE TO SOURCE VOLTAGE (V)
TJ = 150 oC
Figure 5. Transfer Characteristics
©2010 Fairchild Semiconductor Corporation FDC655BN Rev.C2
Figure 4.
On-Resista nce vs Gate to
Source Voltage
100
V
= 0 V
GS
10
1
TJ = 25 oC
TJ = -55 oC
0.1
, REVERSE DRAIN CURRENT (A)
S
I
0.01
0.2 0.4 0.6 0.8 1.0 1.2
TJ = 150 oC
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6.
Source to Dr ain Diode
TJ = 25 oC
TJ = -55 oC
Forward Voltage vs Source Current
3
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Page 4
FDC655BN Single N-Channel, Logic Level, PowerTrench
Typical Characteristics T
= 25°C unless otherwise noted
J
10
ID = 6.3 A
8
VDD = 10 V
6
4
VDD = 20 V
2
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
0246810
Figure 7.
Qg, GATE CHARGE (nC)
Gate Charge Characteristics Figure 8.
100
THIS AREA IS LIMITED BY r
DS(on)
10
1
SINGLE PULSE T
, DRAIN CURRENT (A)
0.1
D
I
0.01
0.01 0.1 1 10 100
= MAX RATED
J
R T
o
= 156
C/W
θJA
o
= 25
C
A
VDS, DRAIN to SOURCE VOLTAGE (V)
1000
C
iss
C
V
DD
= 15 V
100
CAPACITANCE (pF)
f = 1 MHz V
= 0 V
GS
10
0.1 1 10 30
VDS, DRAIN TO SOURCE VOL TAGE (V)
oss
C
rss
Capacitance vs Drain
to Source Voltage
1000
VGS = 10 V
t, PULSE WIDTH (sec)
SINGLE PULSE
= 156 oC/W
R
θ
JA
T
= 25 oC
A
100 1000
MOSFET
1 ms
10 ms
100 ms 1 s
10 s
DC
100
10
1
PEAK TRANSIENT POWER (W)
,
)
PK
(
P
0.1 10-410-310-210-1110
Figure 9. Forward Bias Safe
Operating Area
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
θJA
Z
0.1
0.05
0.02
0.01
0.01
IMPEDANCE,
NORMALIZED THERMAL
0.001
0.0003
-4
10
10
Figure 11.
©2010 Fairchild Semiconductor Corporation FDC655BN Rev.C2
Figure 10.
Power Dissipation
-3
SINGLE PULSE
= 156 oC/W
R
θJA
-2
10
-1
10
t, RECTANGULAR PULSE DURATION (sec)
110
NOTES: DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
Junction-to-Ambient Transient Thermal Response Curve
4
Single Pulse Maximum
P
DM
t
1
t
2
2
x R
+ T
θJA
θJA
A
100 1000
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Page 5
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FDC655BN Single N-Channel, Logic Level, PowerTrench
MOSFET
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Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
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Rev. I46
©2010 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDC655BN Rev.C2
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