Datasheet FDC6323L Datasheet (Fairchild Semiconductor)

Page 1
FDC6323L
Integrated Load Switch
General Description Features
V
These Integrated Load Switches are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage high side load switch application where low conduction loss and ease of driving are needed.
DROP
V
DROP
High density cell design for extremely low on-resistance. V
ON/OFF
>6KV Human Body Model. SuperSOTTM-6 package design using copper lead frame
for superior thermal and electrical capabilities.
March 1999
=0.2V @ VIN=5V, IL=1A, V =0.3V @ VIN=3.3V, IL=1A, V
Zener protection for ESD ruggedness.
= 1.5V to 8V
ON/OFF
ON/OFF
= 1.5V to 8V.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
IN
ON/OFF
EQUIVALENT CIRCUIT
V
DROP
+
-
Vout,C1
Q1
3
2
1
Vout,C1
R2
1
pin
SuperSOT -6
TM
Absolute Maximum Ratings T
Vin,R1
4
ON/OFF
= 25°C unless otherwise noted
R1,C1
5
6
See Application Circuit
Q2
Symbol Parameter FDC6323L Units
V V I
L
IN
ON/OFF
Input Voltage Range 3 - 8 V On/Off Voltage Range 1.5 - 8 V Load Current @ V
=0.5V - Continuous (Note 1) 1.5 A
DROP
- Pulsed (Note 1 & 3) 2.5
P
D
TJ,T ESD Electrostatic Discharge Rating MIL-STD-883D Human Body
Maximum Power Dissipation (Note 2a) 0.7 W Operating and Storage Temperature Range -55 to 150 °C
STG
6 kV
Model (100pf/1500Ohm)
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient (Note 2a) 180 °C/W Thermal Resistance, Junction-to-Case (Note 2) 60 °C/W
OUT
© 1999 Fairchild Semiconductor Corporation
FDC6323L Rev.F
Page 2
Electrical Characteristics (T
= 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS
I
FL
I
RL
Forward Leakage Current VIN = 8 V, V Reverse Leakage Current VIN = -8 V, V
= 0 V 1 µA
ON/OFF
= 0 V -1 µA
ON/OFF
ON CHARACTERISTICS (Note 3)
V
IN
V
ON/OFF
V
DROP
I
L
Notes:
1. VIN=8V, V
2. R by design while R
P
D
Typical R
Input Voltage 3 8 V On/Off Voltage 1.5 8 V Conduction Voltage Drop @ 1A VIN = 5 V, V
VIN = 3.3 V, V
Load Current V
=8V, V
ON/OFF
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
T
(t)
=
R
θ
a. 180oC/W when mounted on a 2oz minimum copper pad.
=0.5V, TA=25oC
DROP
is determined by the user's board design.
CA
θ
T
J−TA
=
(t)
R
θJ A
θJ C
for single device operation using the board layouts shown below on FR-4 PCB in a still air environment:
JA
J−TA
2
(t)
= I
×R
DS(ON)@T
D
(t)
R
θCA
J
= 0.2 V, VIN = 5 V, V
DROP
V
= 0.3 V, VIN = 3.3 V, V
DROP
= 3.3 V 0.145 0.2 V
ON/OFF
= 3.3 V 0.178 0.3
ON/OFF
= 3.3 V 1 A
ON/OFF
= 3.3 V 1
ON/OFF
is guaranteed
JC
θ
2a
Scale 1 : 1 on letter size paper
3. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDC6323L Rev.F
Page 3
Typical Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
0.5
T = 125°C
0.4
J
T = 25°C
J
0.3
DROP
0.2
V (V)
V = 5V
IN
V = 1.5 - 8V
0.1
0
0 1 2 3 4
Figure 1. V
DROP
I (A)
L
Versus IL at VIN=5V.
ON/OFF
PW =300us, D≤ 2%
1
I = 1A
L
V = 1.5 - 8V
0.8
ON/OFF
PW =300us, D≤ 2%
0.6
T = 125°C
DROP
0.4
V (V)
T = 25°C
J
0.2
0
1 2 3 4 5
J
V (V)
IN
0.5
T = 125°C
0.4
J
T = 25°C
J
0.3
DROP
V (V)
0.2
0.1
0
0 1 2 3 4
Figure 2. V
DROP
I (A)
L
Versus IL at VIN=3.3V.
0.4
0.35
0.3
T = 125°C
J
V = 3.3V
IN
V = 1.5 - 8V
ON/OFF
PW =300us, D≤ 2%
I = 1A
L
IN
V = 3.3V PW =300us, D≤ 2%
0.25
(ON)
R ,(Ohm)
0.2
T = 25°C
J
0.15
0.1 0 1 2 3 4 5
I ,(A)
L
Figure 3. V
Versus V
DROP
at IL=1A.
IN
1
I = 1A
L
V = 1.5 - 8V
0.8
ON/OFF
PW =300us, D≤ 2%
0.6
(ON)
0.4
R ,(Ohm)
0.2
0
1 2 3 4 5
T = 25°C
J
T = 125°C
J
V ,(V)
IN
Figure 5. On Resistance Variation with
Input Voltage.
Figure 4. R
Versus IL at VIN=3.3V.
(ON)
FDC6323L Rev.F
Page 4
Typical Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
50
40
30
µ
µ
Vin = 5V
20
Time ( s)
IL = 1A Von/off = 3.3V
R1 = 20K Ci = 10 F Co = 1 F
µ µ
R2 (K )
ΩΩ
10
0
0 2 4 6 8 10
td(off)
tf
Figure 6. Switching Variation with R2 at Vin=5V and R1=20KOhm.
50
Vin = 2.5V IL = 1A Von/off = 3.3V
40
30
µ
µ
20
Time ( s)
10
R1 = 20K Ci = 10 F Co = 1 F
µ
µ
tr td(on)
tr
tf
td(off) td(on)
50
40
30
µ
µ
20
Time ( s)
10
0
0 2 4 6 8 10
R2 (K )
td(off)
ΩΩ
tf
Vin = 3.3V IL = 1A Von/off = 3.3V R1 = 20K Ci = 10 F Co = 1 F
tr
Figure 7. Switching Variation with R2 at Vin=3.3V and R1=20KOhm.
250
Vin = 5V
200
150
100
% of Current Overshoot
50
3.3V
2.5V
IL = 1A Von/off = 3.3V R1 = 20K Ci = 10 F Co = 1 F
µ
µ
td(on)
µ
µ
0
0 2 4 6 8 10
R2 (K )
ΩΩ
Figure 8. Switching Variation with R2 at Vin=2.5V and R1=20KOhm.
500
IL = 1A Von/off = 3.3V
R1 = 20K
400
300
200
Vdrop (mV)
100
µ
Ci = 10 F
µ
Co = 1 F
Vin = 2.5V
3.3V
0
0 20 40 60 80 100
R2 (K )
ΩΩ
Figure 10. Vdrop Variation with Vin and R2.
5V
0
0 2 4 6 8 10
R2 (K )
ΩΩ
Figure 9. % of Current Overshoot Variation with Vin and R2.
t t
on off
t
d(on)
t
r
t
d(off)
90%
V
OUT
10%
90%
V
IN
50%
50%
10%
PULSE WIDTH
Figure 11. Switching Waveforms.
90%
10%
t
f
INVERTED
FDC6323L Rev.F
Page 5
Typical Electrical Characteristics (T
r(t), NORMALIZED EFFECTIVE
= 25 OC unless otherwise noted )
A
0.3
10
3
R(ON) LIMIT
1
1s
10ms
100ms
100us
1ms
DC
0.1
L
I , DRAIN CURRENT (A)
0.03
0.01
0.1 0.2 0.5 1 2 5 10 20 30
V = 5V
IN
SINGLE PULSE
R = See Note 2a
JA
θ
T = 25°C
A
V (V)
DROP
Figure 12. Safe Operating Area.
1
D = 0.5
0.5
R (t) = r(t) * R
θ
0.2
0.1
0.05
0.02
0.01
TRANSIENT THERMAL RESISTANCE
0.005
0.00001 0.0001 0.001 0.01 0.1 1 10 100 300
0.2
0.1
0.05
0.02
0.01 Single Pulse
t , TIME (sec)
JA
R = See Note 2a
θ
JA
P(pk)
t
t
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
θ
JA
θ
JA
Figure 13. Transient Thermal Response Curve.
Note: Thermal characterization performed on the conditions described in Note 2a. Transient thermal response will change depends on the circuit board design.
FDC6323L Rev.F
Page 6
FDC6323L Load Switch Application
=
APPLICATION CIRCUIT
Q2
IN OUT
R1
ON/OFF
Q1
R2
Component Values
R1 Typical 10k - 1M R2 Typical 0 - 100k (optional) C1 Typical 1000pF (optional)
C1
LOAD
Co
General Description
This device is particularly suited for compact computer peripheral switching applications where 8V input and 1A output current capability are needed. This load switch integrates a small N-Channel Power MOSFET (Q1) which drives a large P-Channel Power MOSFET (Q2) in one tiny SuperSOTTM-6 package.
A load switch is usually configured for high side switching so that the load can be isolated from the active power source. A P-Channel Power MOSFET, because it does not require its drive voltage above the input voltage, is usually more cost effective than using an N-Channel device in this particular application. A large P-Channel Power MOSFET minimizes voltage drop. By using a small N-Channel device the driving stage is simplified.
Design Notes
R1 is needed to turn off Q2.
R2 can be used to soft start the switch in case the output capacitance Co is small.
R2 should be at least 10 times smaller than R1 to guarantee Q1 turns on.
By using R1 and R2 a certain amount of current is lost from the input. This bias current loss is given by the equation
I
BIAS_LOSS
Vin
R1+R2
when the switch is ON. I
BIAS_LOSS
can be minimized by selecting a large
value for R1.
R2 and C
of Q2 make ramp for slow turn on. If excessive overshoot current occurs due to fast turn on,
RSS
additional capacitance C1 can be added externally to slow down the turn on.
FDC6323L Rev.F
Page 7
SuperSOTTM-6 Tape and Reel Data and Package Dimensions
SSOT-6 Packaging Configuration: Figure 1.0
Customize Label
Antistatic Cover Tape
Conductive Embossed
Carrier Tape
F63TNR Label
SSOT-6 Packaging Information
Packaging Option Packaging type
Qty per Reel/Tube/Bag 3,000 10,000 Reel Size Box Dimension (mm) 184x187x47 343x343x64 Max qty per Box 9,000 20,000 Weight per unit (gm) 0.0158 0.0158 Weight per Reel (kg) 0.1440 0.4700
Note/Comments
184mm x
Pizza Box for
184mm x 47mm
Standard Option
SSOT-6 Tape Leader Configuration: Figure 2.0
Standard
(no flow code)
TNR
7” Dia
F63TNR Label
D87Z
TNR
13”
F63TNR Label
Trailer
Pin 1
SSOT-6 Unit Orientation
343mm x 342mm x 64mm
Intermediate box for D87Z Option
F63TNR Label sample
LOT: CBVK741B019
FSID: FDC633N
D/C1: D9842 QTY1: SPEC REV: QARV: D/C2: QTY2: CPN:
631
631631
631
F63TNR Label
QTY: 3000
SPEC:
(F63TNR)2
Carrier
Tape
Cover Tape
1998 Fairchild Semiconductor Corporation
Trailer Tape 160mm minimum
Components
Leader Tape 390mm minimum
December 1998, Rev. B
Page 8
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SSOT-6 Embossed Carrier Tape Configuration: Figure 3.0
T
K0
Wc
B0
P0
D0
E1
F
W
E2
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
SSOT-6
(8mm)
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
SSOT-6 Reel Configuration: Figure 4.0
A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
3.23
3.18
8.0
1.55
1.00
1.75
6.25
+/-0.10
+/-0.10
+/-0.3
+/-0.05
+/-0.125
+/-0.10
rotational and lateral movement requirements (see sketches A, B, and C).
B0
20 deg maximum component rotation
Sketch A (Side or Front Sectional View)
Component Rotation
3.50
min
+/-0.05
20 deg maximum
A0
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
4.0 +/-0.1
Typical component cavity center line
Typical component center line
Dim A
Max
4.0 +/-0.1
1.37
0.255 +/-0.150
5.2 +/-0.3
0.5mm maximum
+/-0.10
0.5mm maximum
Sketch C (Top View)
Component lateral movement
0.06 +/-0.02
Dim A
max
Tape Size
8mm 7” Dia
8mm 13” Dia
Reel
Option
Dim N
See detail AA
7” Diameter Option
B Min
Dim C
13” Diameter Option
See detail AA
W2 max Measured at Hub
W3
Dim D
min
DETAIL AA
Dimensions are in inches and millimeters
Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
7.00
0.059
177.8
13.00 330
1.5
0.059
1.5
512 +0.020/-0.008 13 +0.5/-0.2
512 +0.020/-0.008 13 +0.5/-0.2
0.795
2.165550.331 +0.059/-0.000
20.2
0.795
4.00
20.2
100
8.4 +1.5/0
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.567
14.4
0.311 – 0.429
7.9 – 10.9
0.311 – 0.429
7.9 – 10.9
December 1998, Rev. B
Page 9
[
]
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SuperSOT-6 (FS PKG Code 31, 33)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown b elow are in:
Part Weight per unit (gram): 0.0158
inc hes
m illimete rs
1998 Fairchild Semiconductor Corporation
September 1998, Rev. A
Page 10
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ CoolFET™ CROSSVOLT™ E2CMOS
TM
FACT™ FACT Quiet Series™
®
FAST FASTr™ GTO™ HiSeC™
ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
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