Datasheet EM73A89B Datasheet (ELAN)

GENERAL DESCRIPTION

EM73A89B is an advanced single chip CMOS 4-bit micro-controller. It contains 16K-byte ROM, 1012-nibble
RAM, 4-bit ALU, 13-level subroutine nesting, 22-stage time base, two 12-bit timer/counters for the kernel
function, and one high speed conter. EM73A89B also equipped with 6 interrupt sources, 3~7 I/O ports (including
1 input port and 2~7 bidirection ports), LCD display (64x16 or 64x32), built-in watch-dog-timer and speech
synthesizer.
It's low power consumption and high speed feature are further strengten with DUAL, SLOW, IDLE and STOP
operation mode for optimized power saving.

FEATURES

 Operation voltage : 2.2V to 3.6V.
 Clock source : Dual clock system. Low-frequency oscillator is 32KHz. Crystal oscillator or RC

 Instruction set : 107 powerful instructions.
 Instruction cycle time : 0.85µs for 9.2M or 1.7µs for 4.6M Hz selected by mask option(high speed clock).

 ROM capacity : 16K x 8 bits.
 RAM capacity : 1012 x 4 bits.
 Input port : 1 port (P0.0-P0.3), IDLE/STOP releasing function is available by mask option.

 Bidirection port : 2~7 ports (P1, P2, P4, P5, P6, P7, P8). IDLE/STOP release function for P8(0..

 Built-in watch-dog-timer counter : It is available by mask option.
 12-bit timer/counter : Two 12-bit timer/counters are programmable for timer, event counter and pulse

 Built-in time base counter : 22 stages.
 Subroutine nesting : Up to 13 levels.

 Interrupt : External interrupt . . . . . . 2 input interrupt sources.

 High speed counter : The high speed counter includes one 8-bit high speed counter and a resistor to

 LCD driver : 64x32 or 64x16 dots, 1/32 or 1/16 duty, 1/5 bias by mask option.
 Speech synthesizer : 992K speech data ROM (use as 992K nibbles data ROM).
 PWM or current D/A : Output selection by mask option.
 Power saving function : SLOW, IDLE, STOP operation modes.
 Package type : Chip form 126 pins.

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

oscillator by mask option and high-frequency oscillator is a built-in internal
oscillator.

122µs for 32768 Hz (low speed clock, frequency double).

(each input pin has a pull-up and pull-down resistor available by mask option).

3) is available by mask option. P1, P2, P5, P6, P7 are shared with LCD pins.

width measurement mode.

Internal interrupt . . . . . . 2 timer overflow interrupts, 1 time base interrupt.

1 speech/HTC interrupt.

frequency oscillator. It has resistor to frequrncy oscillation mode, melody mode
and auto load timer mode.

* This specification are subject to be changed without notice.

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FUNCTION BLOCK DIAGRAM

RESET CLK

Reset

Control

BZ1/VO

BZ2

P4.0(RX)

P4.1
P4.2(RY)
P4.3(RZ)

VC1~VC4,

VA,VB

VR1~VR4

Speech

synthesizer

HTC

LCD Driver

SEG0~43

COM0~15

Interrupt

Control

Timer/Counter

(TA,TB)

or SEG44~59

P2,5,6,7/COM16~31

P1/SESG60~63

Preliminary

LXIN

LXOUT

Clock

Generator

System Control

Instruction Decoder
Instruction Register

Time
Base

ROM

PC

Data Bus

I/O Control

Timing

Generator

Data pointer

ACC

ALU

Flag

ZCS

Clock Mode

Control

Stack pointer

Stack

RAM

HR

LR

P8.2(INT0)/WAKEUPC

P8.0(INT1)/WAKEUPA

P8.1(TRGB)/WAKEUPB

P8.3(TRGA)/WAKEUPD

P0.0/WAKEUP0
P0.1/WAKEUP1
P0.2/WAKEUP2
P0.3/WAKEUP3

PIN DESCRIPTIONS

Symbol Pin-type Function

V

DD,VDD2

V

SS

RESET RESET-A System reset input signal, low active

CLK OSC-G Capacitor connecting pin for internal high frequency oscillator.
LXIN OSC-B/OSC-H Crystal/Resistor connecting pin for low speed clock source.
LXOUT OSC-B Crystal connecting pin for low speed clock source.
P0(0..3)/WAKEUP0..3 INPUT-B 4-bit input port with IDLE/STOP releasing function

P4.0(RX),P4.2(RY), I/O-X1 3-bit bidirection I/O pins or RF oscillation input pins.
P4.3(RZ) mask option : open-drain (apply to RF oscillation)

P4.1 I/O-Q1 1-bit bidirection I/O pin.

Power supply (+)
Power supply (-)

mask option : none

pull-up

mask option : wakeup enable, pull-up

wakeup enable, none
wakeup disable, pull-up
wakeup disable, pull-down
wakeup disable, none

high current push-pull
normal current push-pull
low current push-pull

mask option : open-drain

high current push-pull
normal current push-pull
low current push-pull

* This specification are subject to be changed without notice.

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Preliminary

Symbol Pin-type Function

P8.0(INT1)/WAKEUPA I/O-X1 2-bit bidirection I/O port with external interrupt sources input and IDLE
P8.2(INT0)/WAKEUPC /STOP releasing function

mask option : wakeup enable, normal current push-pull

wakeup ensable, low current push-pull
wakeup disable, high current push-pull
wakeup disable, normal current push-pull
wakeup disable, low current push-pull

wakeup disable, open drain
P8.1(TRGB)/WAKEUPB I/O-X1 2-bit bidirection I/O port with time/counter A,B external input and IDLE
P8.3(TRGA)/WAKEUPD /STOP releasing function

mask option : wakeup enable, normal current push-pull

wakeup ensable, low current push-pull

wakeup disable, high current push-pull

wakeup disable, normal current push-pull

wakeup disable, low current push-pull

wakeup disable, open drain
VCA, VCB, V1~V6 LCD bias voltage pins
BZ1/VO PWM or current D/A output pin for speech synthesizer by mask option
BZ2 PWM output pin for speech synthesizer
TEST Tie Vss as package type, no connecting as COB type.

*16 COMMONS :

COM0~COM15 LCD common output pins
SEG0~SEG59 LCD segment output pins

P1(0..3)/SEG63..60 I/O-P 4-bit bidirection I/O pins with LCD segment pins

mask option : LCD segment pin

push-pull

open-drain
P2(0..3),P5(0..3), I/O-P 16-bit bidirection I/O pins
P6(0..3),P7(0..3) mask option : push-pull

open-drain

*32 COMMONS :

COM0~COM31 LCD common output pins
SEG0~SEG43 LCD segment output pins

P1(0..3)/SEG63..60, I/O-P 16-bit bidirection I/O pins with LCD segment pins
P2(0..3)/SEG59..56, mask option : LCD segment pin
P5(0..3)/SEG55..52, push-pull
P6(0..3)/SEG51..48, open-drain
P7(0..3)/SEG47..44

* This specification are subject to be changed without notice.

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Preliminary

FUNCTION DESCRIPTIONS

PROGRAM ROM ( 16K X 8 bits )

16 K x 8 bits program ROM contains user's program and some fixed data.
The basic structure of the program ROM may be categorized into 5 partitions.

1. Address 0000h : Reset start address.

2. Address 0002h - 000Ch : 6 kinds of interrupt service routine entry addresses.

3. Address 000Eh - 0086h : SCALL subroutine entry address, only available at 000Eh, 0016h, 001Eh, 0026h, 002Eh,
0036h, 003Eh, 0046h, 004Eh, 0056h, 005Eh, 0066h, 006Eh, 0076h, 007Eh, 0086h.

4. Address 0000h - 07FFh : LCALL subroutine entry address.

5. Address 0000h - 1FFFh : Except used as above function, the other region can be used as user's program and
data region.
address Bank 0 :

EM73A89B

0000h
0002h
0004h
0006h
0008h
000Ah
000Ch
000Eh
0086h

.

.

.

07FFh
0800h

0FFFh
1000h

1FFFh

Reset start address
INT0 ; interrupt service routine entry address

SPI or HTCI
TRGA
TRGB
TBI
INT1

SCALL, subroutine call entry address

Bank 1

Bank 2

Bank 3

Subroutine call entry address
designated by [LCALL a]
instruction

Data table for
[LDAX],[LDAXI]
instruction

* This specification are subject to be changed without notice.

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User's program and fixed data are stored in the program ROM. User's program is executed using the PC value

Preliminary

to fetch an instruction code.
The 16Kx8 bits program ROM can be divided into 4 banks. There are 4Kx8 bits per bank.
The program ROM bank is selected by P3(1..0). The program counter is a 13-bit binary counter. The PC and
P3 are initialized to "0" during reset.
When P3(1..0)=00B or 11B, the bank0 and bank1 of program ROM will be selected. P3(1..0)=01B, the bank0
and bank2 will be selected. P3(1..0)=10B, the bank0 and bank3 will be selected.

P3=xx00B

Address P3=xx11B P3=xx01B P3=xx10B

0000h

:
: Bank0 Bank0 Bank0

0FFFh

1000h

:
: Bank1 Bank2 Bank3

1FFFh

PROGRAM EXAMPLE:

BANK 0

START: :

:
:
LDIA #00H ; set program ROM to bank1
OUTA P3
B XA1
:

XA : :

:
LDIA #01H ; set program ROM to bank2
OUTA P3
B XB1
:

XB : :

:
LDIA #02H ; set program ROM to bank3
OUTA P3
B XC1
:

XC : :

:
BXD

XD : :

:
:

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 1

XA1 : :

:
BXA
:

XA2 : :

* This specification are subject to be changed without notice.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

B XA2

Preliminary

:

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 2

XB1 : :

:
BXB
:

XB2 : :

B XB2
:

; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

BANK 3

XC1 : :

:
BXC
:

XC2 : :

B XC2

Fixed data can be read out by table-look-up instruction. Table-look-up instruction is requires the Data point
(DP) to indicate the ROM address in obtaining the ROM code data (Except bank 0) :

LDAX Acc
LDAXI Acc

←←

← ROM[DP]

←←
←←

← ROM[DP]

←←

L

,DP+1

H

DP is a 12-bit data register that stores the program ROM address as pointer for the ROM code data.
User has to initially load ROM address into DP with instructions "STADPL", and "STADPM, STADPH",
then to obtain the lower nibble of ROM code data by instruction "LDAX" and higher nibble by instruction
"LDAXI".

PROGRAM EXAMPLE: Read out the ROM code of address 1777h by table-look-up instruction.

LDIA #07h;
STADPL ; [DP]
STADPM ; [DP]
STADPH ; [DP]
:
LDL #00h;
LDH #03h;

LDAX ; ACC ← 6h
STAMI ; RAM[30] ← 6h
LDAXI ; ACC ← 5h
STAM ; RAM[31] ← 5h

;
ORG 1777h
DATA 56h;

← 07h

L

← 07h

M

← 07h, Load DP=777h

H

DATA RAM ( 1012-nibble )

A total 1012 - nibble data RAM is available from address 000 to 3FFh
Data RAM includes the zero page region, stacks and data areas.

* This specification are subject to be changed without notice.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

EM73A89B

Bank 0

Address

P9=xx00B 000-00Fh

010-01Fh
020-02Fh
030-03Fh
040-04Fh
050-05Fh
060-06Fh
070-07Fh
080-08Fh

090-09Fh
0A0-0AFh
0B0-0BFh

0C0-0CFh
0D0-0DFh

0E0-0EFh

0F0-0FFh

Bank 1

P9=xx01B 100-10Fh

110-11Fh

:

:
1E0-1EFh
1F0-1FFh

Bank 2

P9=xx10B 200-20Fh

210-21Fh
220-22Fh
230-23Fh
240-24Fh
250-25Fh
260-26Fh
270-27Fh
280-28Fh

290-29Fh
2A0-2AFh
2B0-2BFh

2C0-2CFh
2D0-2DFh
2E0-2EFh

2F0-2FFh

Bank 3

P9=xx11B 300-30Fh

310-31Fh

320-32Fh

330-33Fh

340-34Fh

350-35Fh

360-36Fh

370-37Fh

380-38Fh

390-39Fh
3A0-3AFh
3B0-3BFh

3C0-3CFh
3D0-3DFh

3E0-3EFh
3F0-3FFh

0123456789ABCDEF

ZERO PAGE

Level 0 Level 1 Level 2 Level 3
Level 4 Level 5 Level 6 Level 7

Level 8

Level 8 Level 10 Level 11

Level 12

:
:

COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8

COM9
COM10
COM11
COM12
COM13
COM14
COM15

COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

* This specification are subject to be changed without notice.

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

8.16.2001

SEG62

SEG63

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

ZERO- PAGE:

From 000h to 00Fh is the zero-page location. It is used as the zero-page address mode pointer for the
instruction of "STD #k,y; ADD #k,y; CLR y,b; CMP k,y".

PROGRAM EXAMPLE: To write immediate data "07h" to RAM [03] and to clear bit 2 of RAM [0Eh].

STD #07h, 03h ; RAM[03] ← 07h

CLR 0Eh,2 ; RAM[0Eh]

STACK:

There are 13 - level (maximum) stack levels that user can use for subroutine (including interrupt and CALL).
User can assign any level be the starting stack by providing the level number to stack pointer (SP).
When an instruction (CALL or interrupt) is invoked, before enter the subroutine, the previous PC address
is saved into the stack until returned from those subroutines, the PC value is restored by the data saved in stack.

DATA AREA:

← 0

2

Except the area used by user's application, the whole RAM can be used as data area for storing and loading
general data.

ADDRESSING MODE

The 1012 nibble data memory consists of four banks (bank 0 ~ bank 3). There are 244x4 bits (address
000h~0F3h) in bank 0 and 768x4 bits (address 100h ~ 3FFh) in bank 1 ~ bank 3.

The bank is selected by P9.
P9 Initial value : * * 0 0

* * RBK
RBK RAM bank

0 0 Bank0
0 1 Bank1
1 0 Bank2
1 1 Bank3
The Data Memory consists of three Address mode, namely -

(1) Indirect addressing mode:

The address in the bank is specified by the HL registers.

P9(1,0)

HR LR

RAM address

* This specification are subject to be changed without notice.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "032h".

OUT #0001B,P9 ; RAM bank1

LDL #3h ; LR← 3
LDH # 4h ; HR← 4
LDAM ; Acc← RAM[134h]

OUT #0000B,P9 ; RAM bank0

LDL #2h ; LR← 2
LDH # 3h ; HR← 3
STAM ; RAM[023h]← Acc

(2) Direct addressing mode:

The address in the bank is directly specified by 8 bits code of the second byte in the instruction field.

instruction field

xxxxxxxx

P9(1,0)

EM73A89B

RAM address

PROGRAM EXAMPLE: Load the data of RAM address "143h" to RAM address "023h".

OUT #0001B,P9

LDA 43h ; Acc← RAM[143h]

OUT #0000B,P9

STA 23h ; RAM[023h]← Acc

(3) Zero-page addressing mode:

The zero-page is in the bank 0 (address 000h~00Fh). The address is the lower 4 bits code of the second byte
in the instruction field.

xxxxxxxx

instruction field

yyyy

0000

yyyy

RAM address

PROGRAM EXAMPLE: Write immediate "0Fh" to RAM address "005h".

STD #0Fh, 05h ; RAM[05h]← 0Fh

00

* This specification are subject to be changed without notice.

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PROGRAM COUNTER (16K ROM)

Preliminary

Program counter ( PC ) is composed by a 13-bit counter, which indicates the next executed address for the
instruction of program ROM instruction.
For BRANCH and CALL instructions, PC is changed by instruction indicating. PC only can indicate the address
from 0000h-1FFFh. The bank number is decided by P3.

(1) Branch instruction:

SBR a

Object code: 00aa aaaa

Condition: SF=1; PC ← PC

( branch condition satisified )

12-6.a

PC Hold original PC value+1 aaaaaa

SF=0; PC← PC +1( branch condition not satisified )

PC Original PC value + 1

LBR a

Object code: 1100 aaaa aaaa aaaa

Condition: SF=1; PC ← PC

( branch condition satisified )

12.a

Hold

PC

a a a a a a aaaaaa

+2

SF=0; PC← PC +2( branch condition not satisified )

PC Original PC value + 2

SLBR a

Object code: 0101 0101 1100 aaaa aaaa aaaa (a:1000h~1FFFh)

0101 0111 1100 aaaa aaaa aaaa (a:0000h~0FFFh)

Condition: SF=1; PC ← a ( branch condition satisified )

PCaaaaaaaaaaaa a

SF=0 ; PC ← PC + 3 ( branch condition not satisified )

PC Original PC value + 3

(2) Subroutine instruction:

SCALL a

Object code: 1110 nnnn

Condition : PC ← a ; a=8n+6 ; n=1..Fh ; a=86h, n=0

PC00000aaaaa aaa

LCALL a

Object code: 0100 0aaa aaaa aaaa

Condition: PC ← a

* This specification are subject to be changed without notice.

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4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

PC00aaaaaaaaaa a

RET

Object code: 0100 1111

Condition: PC ← STACK[SP]; SP + 1

PC The return address stored in stack

RT I

Object code: 0100 1101

Condition : FLAG. PC ← STACK[SP]; EI ← 1; SP + 1

PC The return address stored in stack

(3) Interrupt acceptance operation:

When an interrupt is accepted, the original PC is pushed into stack and interrupt vector will be loaded into
PC. The interrupt vectors are as follows :

INT0 (External interrupt from P8.2)

PC00000000000 1 0

SPI (speech end interrupt)

PC000000000010 0

TRGA (Timer A overflow interrupt)

PC0000000000 1 1 0

TRGB (Time B overflow interrupt)

PC00000000 0 1 0 0 0

TBI (Time base interrupt)

PC00000000 0 1 0 1 0

INT1 (External interrupt from P8.0)

PC00000000 0 1 1 0 0

(4) Reset operation:

PC00000000000 0 0

* This specification are subject to be changed without notice.

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Preliminary

(5) Other operations:

For 1-byte instruction execution: PC + 1
For 2-byte instruction execution: PC + 2
For 3-byte instruction execution: PC + 3

ACCUMULATOR

Accumulator(ACC) is a 4-bit data register for temporary data storage. For the arithematic, logic and
comparative opertion.., ACC plays a role which holds the source data and result.

FLAGS

There are three kinds of flag, CF ( Carry flag ), ZF ( Zero flag ) and SF ( Status flag ), these three 1-bit flags

are included by the arithematic, logic and comparative .... operation.

All flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after
RTI instruction is executed.

(1) Carry Flag ( CF )

The carry flag is affected by the following operations:
a. Addition : CF as a carry out indicator, under addition operation, when a carry-out occures, the CF is "1",

likewise, if the operation has no carry-out, CF is "0".

b. Subtraction : CF as a borrow-in indicator, under subtraction operation, when a borrow occures, the CF

is "0", likewise, if there is no borrow-in, the CF is "1".

c. Comparision : CF as a borrow-in indicator for Comparision operation as in the subtraction operation.

d. Rotation : CF shifts into the empty bit of accumulator for the rotation and holds the shift out data after

rotation.

e. CF test instruction : Under TFCFC instruction, the CF content is sent into SF then clear itself as "0".

Under TTSFC instruction, the CF content is sent into SF then set itself as "1".

(2) Zero Flag ( ZF )

ZF is affected by the result of ALU, if the ALU operation generates a "0" result, the ZF is "1", likewise, the
ZF is "0".

(3) Status Flag ( SF )

The SF is affected by instruction operation and system status.

a. SF is initiated to "1" for reset condition.

b. Branch instruction is decided by SF, when SF=1, branch condition is satisified, likewise, when SF = 0,

branch condition is unsatisified.

* This specification are subject to be changed without notice.

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PROGRAM EXAMPLE:

Preliminary

Check following arithematic operation for CF, ZF, SF

CF ZF SF

LDIA #00h; - 1 1
LDIA #03h; - 0 1
ADDA #05h; - 0 1
ADDA #0Dh; - 0 0
ADDA #0Eh; - 0 0

ALU

The arithematic operation of 4-bit data is performed in ALU unit. There are 2 flags that can be affected by
the result of ALU operation, ZF and SF. The operation of ALU is affected by CF only.

ALU STRUCTURE

ALU supported user arithematic operation functions, including Addition, Subtraction and Rotaion.

DATA BUS

ALU

ZF CF SF

ALU FUNCTION

(1) Addition:

ALU supports addition function with instructions ADDAM, ADCAM, ADDM #k, ADD #k,y .... .

The addition operation affects CF and ZF. Under addition operation, if the result is "0", ZF will be "1",
otherwise, ZF will be "0". When the addition operation has a carry-out, CF will be "1", otherwise, CF will
be "0".

EXAMPLE:

Operation Carry Zero
3+4=7 0 0
7+F=6 1 0
0+0=0 0 1
8+8=0 1 1

(2) Subtraction:

ALU supports subtraction function with instructions SUBM #k, SUBA #k, SBCAM, DECM... . The

subtraction operation affects CF and ZF. Under subtraction operation, if the result is negative, CF will
be "0", and a borrow out, otherwise, if the result is positive, CF will be "1". For ZF, if the result of subtraction
operation is "0", the ZF is "1", likewise, ZF is "1".

* This specification are subject to be changed without notice.

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EXAMPLE:

Preliminary

Operation Carry Zero
8-4=4 1 0
7-F= -8(1000) 0 0
9-9=0 1 1

(3) Rotation:

Two types of rotation operation are available, one is rotation left, the other is rotation right.
RLCA instruction rotates Acc value counter-clockwise, shift the CF value into the LSB bit of Acc and hold
the shift out data in CF.

MSB LSB

ACC

CF

RRCA instruction operation rotates Acc value clockwise, shift the CF value into the MSB bit of Acc and
hold the shift out data in CF.

MSB LSB

ACC

CF

PROGRAM EXAMPLE: To rotate Acc clockwise (right) and shift a "1" into the MSB bit of Acc.

TTCFS; CF ← 1

RRCA; rotate Acc right and shift CF=1 into MSB.

HL REGISTER

HL register are two 4-bit registers, they are used as a pair of pointer for the RAM memoryaddress. They are
used as also 2 independent temporary 4-bit data registers. For certain instructions, L register can be a pointer
to indicate the pin number (Port4 only).

HL REGISTER STRUCTURE

3 2 1 0

H REGISTER

3 2 1 0

L REGISTER

HL REGISTER FUNCTION

(1) HL register is used as a temporary register for instructions : LDL #k, LDH #k, THA, THL, INCL, DECL,

EXAL, EXAH.

PROGRAM EXAMPLE:

LDL #05h;
LDH #0Dh;

Load immediate data "5h" into L register, "0Dh" into H register.

(2) HL register is used as a pointer for the address of RAM memory for instructions : LDAM, STAM, STAMI ..

PROGRAM EXAMPLE: Store immediate data "#0Ah" into RAM of address 35h.

* This specification are subject to be changed without notice.

8.16.2001

14

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

LDL #5h;
LDH #3h;

STDMI #0Ah; RAM[35] ← Ah

(3) L register is used as a pointer to indicate the bit of I/O port for instructions : SELP, CLPL, TFPL,

(When LR = 0 indicate P4.0)

PROGRAM EXAMPLE: To set bit 0 of Port4 to "1"

LDL #00h;

SEPL ; P4.0 ← 1

STACK POINTER (SP)

Stack pointer is a 4-bit register that stores the present stack level number.
Before using stack, user must set the SP value first, CPU will not initiate the SP value after reset condition.
When a new subroutine is received, the SP is decreased by one automatically, likewise, if returning from a
subroutine, the SP is increased by one.
The data transfer between ACC and SP is done with instructions "LDASP" and "STASP".

DATA POINTER (DP)

Data pointer is a 12-bit register that stores the ROM address can indicating the ROM code data specified
by user (refer to data ROM).

CLOCK AND TIMING GENERATOR

The clock generator is supported by a dual clock system. The high-frequency oscillator is internal oscillator.
The low-frequency oscillator may be sourced from crystal, the working frequency is 32 KHz.

CLOCK GENERATOR STRUCTURE

There are two clock generator for system clock control unit, P14 is the status register that hold the CPU
status. P16, P19 and P22 are the command register for system clock mode control.

CLK

LXIN

LXOUT

High-frequency

generator

Low-frequency

generator

fc

System clock

fs

mode control

P14

P16

P19

P22

LXIN

LXOUT

Crystal connection

VDD

* This specification are subject to be changed without notice.

System control

R

LXIN

open

RC oscillator connection

R=2.2MΩ

LXOUT

8.16.2001

15

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

SYSTEM CLOCK MODE CONTROL

Preliminary

The system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator
and switch between the basic clocks. EM73A89B has four operation modes (DUAL, SLOW, IDLE and
STOP operation modes).

RESET

operation

Reset

Reset

I/O wakeup

Reset

Reset release

STOP

operation

mode

NORMAL

operation

mode

Command

(P16)

Reset

Command

High osc : stopped
Low osc : stopped

High osc : oscillating
Low osc : oscillating

Command

(P22)

(P22)

Command

(P19)

Command

(P16)

SLOW

operation

mode

High osc : stopped
Low osc : oscillating

I/O or internal timer wakeup

IDLE
(CPU
stops)

High osc : stopped
Low osc : oscillating

Operation Mode Oscillator System Clock Available function One instruction cycle

NORMAL High, Low frequency High frequency clock LCD, speech, HTC. 8 / fc

SLOW Low frequency Low frequency clock LCD, HTC 4 / fs

IDLE Low frequency CPU stops LCD ­STOP None CPU stops All disable -

DUAL OPERATION MODE

The 4-bit µc is in the DUAL operation mode when the CPU is reseted. This mode is dual clock system
(high-frequency and low-frequency clocks oscillating). It can be changed to SLOW or STOP operation
mode with the command register (P22 or P16).
LCD display, speech synthesizer and sound generator are available for the DUAL operation mode.

SLOW OPERATION MODE

The SLOW operation mode is single clock system (low-frequency clock oscillating). It can be changed to
the DUAL operation mode with the command register (P22), STOP operation mode with P16 and IDEL
operation mode with P19.

LCD display is available for the SLOW operation mode. Speech synthesizer and sound generator are
disabled in this mode.

* This specification are subject to be changed without notice.

8.16.2001

16

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

P22 3210 Initial value : ***0

Preliminary

* * * SOM

SOM Select operation mode

0 DUAL operation mode
1 SLOW operation mode

P14 32 10 Initial value : 0000

ACT WKS SINT CPUS

CPUS CPU status WKS Wakeup status

0 DUAL operation mode 0 Wakeup not by internal timer
1 SLOW operation mode 1 Wakeup by internal timer

Port14 is the status register for CPU. P14.0 (CPU status) is a read-only bit. P14.2 (wakeup status) will be
set as "1" when CPU is waked by internal timer. P14.2 will be cleared as "0" when user out data to P14.
P14.1 is the interrupt source selector (refer to interrupt). P14.3 is the speech acknowledge signal (refer to
speech synthesizer control).

IDLE OPERATION MODE

The IDLE operation mode suspends all CPU functions except the low-frequency clock oscillation and the
LCD driver. It keeps the internal status with low power consumption without stopping the slow clock
oscillator and LCD display.

LCD display is available for the IDLE operation mode. The high speed counter and speech synthesizer are
disabled in this mode. The IDLE operation mode will be wakeup and return to the SLOW operation mode by
the internal timing generator or I/O pins (P0(0..3)/WAKEUP 0..3 and P8(0..3)/WAKEUPA..D).

P19 32 10 Initial value : 0000

IDME SIDR

IDME Enable IDLE mode SIDR Select IDLE releasing condition

0 1 Enable IDLE mode 0 0 P0(0..3), P8(0..3) pin input
* * no function 0 1 P0(0..3), P8(0..3) pin input and 1 sec signal

1 0 P0(0..3), P8(0..3) pin input and 0.5 sec signal
1 1 P0(0..3), P8(0..3) pin input and 15.625 ms signal

STOP OPERATION MODE

The STOP operation mode suspends system operation and holds the internal status immediately before the
suspension with low power consumption. This mode will be released by reset or I/O pins (P0(0..3)/
WAKEUP 0..3 or P8(0..3)/WAKEUP A..D).

LCD display, high speed counter and speech synthesizer are disabled in this mode.

* This specification are subject to be changed without notice.

8.16.2001

17

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

P16 3210 Initial value : *000

* SWWT

SWWT Enable STOP mode

1 0 1 Enable STOP mode
* * * no function

GENERAL PURPOSE REGISTER (P10)

P10 is a 4-bit general purpose register which can be read, written and rested by all I/O instructions.
(including : INA, INM, OUT, OUTA, OUTM, SEP, CLP, TTP, TFP)

PROGRAM EXAMPLE:

CHIP ROM16K

;--------RAM define area-----------------

DSEG

ORG 10H
HLBUF: RES 2 ; HL buffer for interrupt
P9BUF: RES 1 ; P9 (RAM bank) buffer for interrupt

:
;----------Interrupt subroutine--------------------

CSEG

ORG 004H

LBR S PI

:
SPI: OUTA P10 ; save Acc to general purpose register P10

INA P9

OUT #0000B,P9 10 instruction bytes

STA P9BUF ; save RAM bank to P9BUF

EXHL HLBUF ; save HL to HLBUF

:

:

EXHL HLBUF ; restore HLBUF to HL

LDA P9BUF ; resotre P9BUF to RAM bank 10 instruction bytes

OUTA P9

INA P10 ; restore register P10 to Acc

RTI

* This specification are subject to be changed without notice.

8.16.2001

18

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

TIME BASE INTERRUPT (TBI)

The time base can be used to generate a single fixed frequency interrupt. Eight types of frequencies can be
selected with the "P25" setting.

P25 3 2 1 0

initial value : 0000

P25 NORMAL operation mode SLOW operation mode

0 0 x x Interrupt disable Interrupt disable
0 1 0 0 Interrupt frequency LXIN / 2

0 1 0 1 Interrupt frequency LXIN / 2
0 1 1 0 Interrupt frequency LXIN / 2
0 1 1 1 Interrupt frequency LXIN / 2
1 1 0 0 Interrupt frequency LXIN / 21 Hz Reserved
1 1 0 1 Interrupt frequency LXIN / 26 Hz Interrupt frequency LXIN / 26 Hz
1 1 1 0 Interrupt frequency LXIN / 28 Hz Interrupt frequency LXIN / 28 Hz
1 1 1 1 Interrupt frequency LXIN / 2

1 0 x x Reserved Reserved

3

Hz Reserved

15

Hz Interrupt frequency LXIN / 2

5

Hz Reserved

14

Hz Interrupt frequency LXIN / 2

10

Hz Interrupt frequency LXIN / 2

14

10

15

Hz

Hz

Hz

TIMER / COUNTER (TIMERA, TIMERB)

Timer/counters support three special functions:

1. Even counter

2. Timer.

3. Pulse-width measurement.

These three functions can be executed by 2 timer/counter independently.
With timerA, the counter data is saved in timer register TAH, TAM, TAL. User can set counter initial
value and read the counter value by instruction "LDATAH(M,L)" and "STATAH(M,L)". With timer B
register is TBH, TBM, TBL and the W/R instruction are "LDATBH (M,L)" and "STATBH (M,L)".
The basic structure of timer/counter is composed by two identical counter module, these two modules can
be set initial timer or counter value to the timer registers, P28 and P29 are the command registers for timerA
and timer B, user can choose different operation modes and internal clock rates by setting these two
registers. When timer/counter overflows, it will generate a TRGA(B) interrupt request to interrupt control
unit.

12 BIT COUNTER

INTERRUPT CONTROL

TRGA request

DATA BUS

TRGB request

12 BIT COUNTER

P8.3/
TRGA

internal clock

EVENT COUNTER CONTROL

TIMER CONTROL

PULSE-WIDTH MEASUREMENT

P28

CONTROL

TMSA IPSA

P29

* This specification are subject to be changed without notice.

EVENT COUNTER CONTROL

TIMER CONTROL

PULSE-WIDTH MEASUREMENT

CONTROL

TMSB IPSB

P8.1/
TRGB

internal clock

8.16.2001

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EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

TIMER/COUNTER CONTROL

P8.1/TRGB, P8.3/TRGA are the external timer inputs for timerB and timerA, they are used in event
counter and pulse-width measurement mode.

Timer/counter command port: P28 is the command port for timer/counterA and P29 is for the timer/
counterB.

P28, P29 3210 Initial value : 0000

TMSA(B) IPSA(B)

TMSA(B) Mode selection
0 0 Stop
0 1 Event counter mode
1 0 Timer mode
1 1 Pulse width measurement mode

IPSA Clock rate selection IPSB Clock rate selection

NORMAL mode SLOW mode NORMAL mode SLOW mode
0 0 LXIN/23 HZ Reserved 0 0 Depend on high speed timer/counter
0 1 LXIN/27 HZ LXIN/27 HZ 0 1 LXIN/25 HZ LXIN/25 HZ
1 0 LXIN/211 HZ LXIN/211 HZ 1 0 LXIN/29 HZ LXIN/29 HZ
1 1 LXIN/215 HZ LXIN/215 HZ 1 1 LXIN/213 HZ LXIN/213 HZ

TIMER/COUNTER FUNCTION

Timer/counterA,B are programmable for timer, event counter and pulse width measurement mode. Each
timer/counter can execute any of these functions independently.

EVENT COUNTER MODE

Under event counter mode, the timer/counter is increased by one at any rising edge of P8.1/TRGB for timerB
(P8.3/TRGA for timer A). When timerB (timerA) counts overflow, it will provide an interrupt request
TRGB (TRGA) to interrupt control unit.

P8.1/TRGB (P8.3/TRGA)

TimerB (TimerA) value n n+1 n+2 n+3 n+4 n+5 n+6

PROGRAM EXAMPLE: Enable timerA with P28

LDIA #0100b;
OUTA P28 ; Enable timerA with event counter mode

* This specification are subject to be changed without notice.

8.16.2001

20

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

TIMER MODE

Under timer mode, the timer/counter is increased by one at any rising edge of internal pulse. User can choose
up to 4 types of internal pulse rate by setting IPSB for timerB (IPSA for timerA).
When timer/counter counts overflow, an interrupt request will be sent to interrupt control unit.

Internal pulse

TimerB (TimerA )value

n n+1 n+2 n+3 n+4 n+5 n+6 n+7

PROGRAM EXAMPLE: To generate TRGA interrupt request after 60 ms with system clock LXlN=32KHz

LDIA #0100B ;
EXAE ; enable mask 2

EICIL 110111b ; interrupt latch ←0, enable EI

LDIA #0Ah;
STATAL;
LDIA #00h;
STATAM;
LDIA #0Fh;
STATAH;
LDIA #1000B;
OUTA P28 ; enable timerA with internal pulse rate: LXIN/23 Hz

NOTE: The preset value of timer/counter register is calculated as following procedure.

Internal pulse rate: LXIN/2

3

; LXIN = 32KHz
The time of timer counter count one = 23 /LXIN = 8/32768=0.244ms
The number of internal pulse to get timer overflow = 60 ms/0.244ms = 245.901= 0F6h
The preset value of timer/counter register = 1000h - 0F6h = F0Ah

PULSE WIDTH MEASUREMENT MODE

Under the pulse width measurement mode, the counter is incresed at the rising edge of internal pulse during
external timer/counter input (P8.1/TRGB, P8.3/TRGA) in high level, interrupt request is generated as soon as
timer/counter count overflow.

P8.1/TRGB(P8.3/TRGA)

Internal pulse

TimerB(TimerA) value

n n+1 n+2 n+3 n+4 n+5

PROGRAM EXAMPLE: Enable timerA by pulse width measurement mode.

LDIA #1100b ;
OUTA P28 ; Enable timerA with pulse width measurement mode.

* This specification are subject to be changed without notice.

8.16.2001

21

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

INTERRUPT FUNCTION

Six interrupt sources are available, 2 from external interrupt sources and 4 from internal interrupt sources.
Multiple interrupts are admitted according to their priority.

Type Interrupt source Priority Interrupt Interrupt Program ROM

Latch Enable condition entry address

External External interrupt (INT0) 1 IL5 EI=1 002h
Internal Speech or HTC interrupt (SPI or HTCI) 2 IL4 EI=1, MASK3=1 004h
Internal TimerA overflow interrupt (TRGA) 3 IL3 EI=1, MASK2=1 006h
Internal TimerB overflow interrupt (TRGB) 4 IL2 EI=1, MASK1=1 008h
Internal Time base interrupt(TBI) 5 IL1 00Ah
External External interrupt(INT1) 6 IL0 EI=1, MASK0=1 00Ch

INTERRUPT STRUCTURE

Reset by system reset and program

instruction

Reset by system reset and program

instruction

Set by program instruction

MASK0 MASK1 MASK1 MASK2 MASK3

IL1

TRGB
r2

EI

TRGA
r3

IL2

Priority checker

IL3

INT1

r0

IL0

TBI

r1

Interrupt request Interrupt entry address

SPI or
HTCI

r4

IL4

Entry address generator

INT0

r5

IL5

Interrupt controller:

IL0-IL5 : Interrupt latch. Hold all interrupt requests from all interrupt sources. IL's can not

be set by program, but can be reset by program or system reset, so IL can only
decide which interrupt source can be accepted.

MASK0-MASK3 : Except INT0, MASK register may permit or inhibit all interrupt sources.

EI : Enable interrupt Flip-Flop may promit or inhibit all interrupt sources, when inter-

rupt occurs, EI is auto cleared to "0", after RTI instruction is executed, EI is auto
set to "1" again.

Priority checker : Check interrupt priority when multiple interrupts occur.

* This specification are subject to be changed without notice.

8.16.2001

22

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

INTERRUPT OPERATION

Preliminary

The procedure of interrupt operation:

1. Push PC and all flags to stack.

2. Set interrupt entry address into PC.

3. Set SF = 1.

4. Clear EI to inhibit other interrupts occur.

5. Clear the IL with which interrupt source has already been accepted.

6. Excute interrupt subroutine from the interrupt entry address.

7. CPU accept RTI, restore PC and flags from stack. Set EI to accept other interrupt requests.

PROGRAM EXAMPLE: To enable interrupt of "INT0, TRGA"

LDIA #0100B ;
EXAE ; set mask register "0100b"
EICIL 010111B ; enable interrupt F.F. and clear IL3 and IL5

INTERRUPT SOURCE SELECTION REGISTER

P14 3 2 1 0 Initial value : 0000

ACT WKS SINT CPUS

P14.1 is the interrupt source selection register for speech ending interrupt (SPI) and high speed counter
overflow interrupt (HTCI) selection. When SINT=0, the program address "0004H" is the interrupt entry
address of SPI. When SINT=1, the program address "0004H" is the interrupt entry address of HTCI.
P14.0 and P14.2 are the CPU flages (refer to system operation mode). P14.3 is the speech acknowledge
signal (refer to speech synthesizer control).

HIGH SPEED COUNTER

EM73A89B has one high speed counter for resistor to frequency oscillation mode, melody mode and auto load
timer mode. This function is available for the DUAL and SLOW operation mode. The resistor to frequency
oscillation (RFO) circuit as show below :

F

RF

P18(3..2)

Counter

clock

rate

FRF/2

P20(1..0)

Rate

gating

rate

X

P13

8-bit Counter

P20(3..2)

Mode

P12

P17

VCR

HTCI interrupt

TCB

PWM ckt or D/A

P4.0(RX)

P4.2(RY)

P4.3(RZ)

P18(1..0)

MUX

Resistor

to

frequency

oscillator

* This specification are subject to be changed without notice.

8.16.2001

23

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

CONTROL OF HIGH SPEED COUNTER

The high speed counter is controlled by the command registers (P20, P18) :

P20 3 2 1 0 Initial value : 0000

MODE RATE

MODE Selection of HTC mode
0 0 Disable HTC
0 1 Auto load timer mode
1 0 Melody mode
1 1 Resistor to frequency oscillation mode

RATE Internal pulse rate / Counter start request frequency
( Hz ) Resistor to frequency Auto load timer mode /

oscillation mode Melody mode internal pulse rate
0 0 LXIN / 2
0 1 LXIN / 2
1 0 LXIN / 2
1 1 LXIN / 2

$



"

#

CLK / 2
CLK / 2
CLK / 2
CLK / 2

EM73A89B

"

#

$

%

P18 3 2 1 0 Initial value : 0000

RFIP RFIN

RFIP Input frequency of RFO RFIN Selection of RFO Pin
0 0 F
0 1 F
1 0 F
1 1 F

4. 0 0 Normal I/O

4. / 4 0 1 P4.0 (RX) for RFO

4. / 16 1 0 P4.2 (RY) for RFO

4. / 64 1 1 P4.3 (RZ) for RFO

P12 and P13 are the 8-bit binary counter registers of the HTC. P12 is lower nibble register and P13 is higher
nibble register.

P13 P12

3 2 1 0 3 2 1 0 Initial value : 0000 0000

Higher nibble register Lower nibble register

The HTC can be set initial value and send counter value to counter registers (P13 and P12), P20 and P18
are the command ports for HTC, user can choose different operation mode and different internal clockrate
by setting the port. The timer/counter increase one at the rising edge of internal pulse. The HTC can
generate an overflow interrupt (HTCI) when it overflows. The HTCI can't be generated when the HTC
is in the melody mode or disabled.

* This specification are subject to be changed without notice.

8.16.2001

24

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

8-BIT BINARY COUNTER

Preliminary

Write the preset value to the registers

The value of 8-bit binary counter can be presetted by P13 and P12. The value of registers can be loaded into
the 8-bit binary counter when the counter starts counting or occurs overflow. When the 8-bit binary counter
overflows, the HTCI interrupt will be generated. If you write values to the registers before the next overflow
occurs, the preset value can be changed.

Read the count value from the registers

The count value of 8-bit binary counter can be read out from P13 and P12. The value is unstable when you
read out the value during counting. Thus, you must disable the counter before reading out the value.

20-BIT COUNTER FUNCTION

The 8-bit binary counter is connected to TCB which is one 12-bit general counter and becomes to the 20­bit counter. The TCB increases one when the 8-bit binary counter overflows and generats an overflow
interrupt (TRGB) when the TCB overflows. The TRGB cannot be generated when the HTC is in the melody
or disable.

FUNCTION OF HIGH SPEED COUNTER

The HTC has three modes which are RFO mode, melody mode and auto load timer mode.

The HTC is disabled when the CPU is reseted or in the STOP/IDLE operation mode. Users must enable
it by yourself when the CPU is waked up.

Resistor to frequency oscillation mode

In this mode, the HTC is counted by the rising edges of input pulses from P4.1 (CS) and the value of
window gate width is specified by P20. In this case, the window gate width interval is from the time base
output fall to rise and the value of window gate width setting is the same as the time base interrupt frequency.
The time base can be generated a fixed frequency interrupt when the time base interrupt (TBI) is enabled.
The content of the HTC can be read and initialized by the TBI interrupt service routine.

HTC input pulse

Time base

8-bit binary counter

8-bit binary counter
overflow

TCB counter

Program

 ex. TBI interrupt frequency is LXIN/2

(P20=1111B). The window gate width of RFO is 2

n+1 00 01 00 01n FF

00 001

Disable
HTC and
read data.

TBI interrupt service routine

15

Hz (P25=0101B). The pulse rate of RFO is LXIN/215 Hz

Enable HTC
and write data.

Window gate width

14

/LXIN sec. (LXIN=32KHz)

* This specification are subject to be changed without notice.

8.16.2001

25

PROGRAM EXAMPLE

DSEG
ORG 00H

HLBUF: RES 2

P9BUF: RES 1

RFCON: RES 1

:

CSEG
ORG 00H
LBR MAIN ; initial jump
ORG 0AH
LBR TBI ; timebase interrupt vector address
:

TBI: OUTA P10

INA P9
OUT #0,P9
STA P9BUF
EXHL HLBUF
CMP #00H,RFCON
B TBI1
STD #01H,RFCON
LDIA #00H ; initial TCB & HTC register
OUTA P13
OUTA P12
STATBL
STATBM
STATBH
B TBIEND

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

; timebase interrupt service routine

* This specification are subject to be changed without notice.

8.16.2001

26

TBI1: OUTA P10

INA P9
OUT #0,P9
STA P9BUF
EXHL HLBUF
LDIA #00H ; disable RFO before reading the counter value
OUTA P20
INA P12 ; store the counter value to RAM[00] - RAM[04]
STA 00H
INA P13
STA 01H
LDATBL
STA 02H
LDATBM
STA 03H
LDATBH
STA 04H

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

TBIEND: EXHL HLBUF

LDA P9BUF
OUTA P9
INA P10
RTI

MAIN: STD #00H,RFCON

LDIA #0001B ; P4.0 (RX) output
OUTA P18
LDIA #0010B ; enable timebase interrupt
EXAE
EICIL 0
LDIA #1111B ; the pulse rate of RFO=2
OUTA P20
LDIA #0101B ; enable timebase, interrupt frequency : LXIN / 2
OUTA P25
:

; main program

15

/LXIN sec.

15

Hz

* This specification are subject to be changed without notice.

8.16.2001

27

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Auto load timer mode

In this mode, there are four different internal pulse rates can be selected by P20. The HTC loads the
initial values by the counter registers (P12, P13) and increases at the rising edges of internal pulse generated
by the time base. The value of TCB increases one when the high speed counter overflows and generates
an overflow interrupt (TRGB) when the TCB overflows. This mode is only available for DUAL operation
mode.

PROGRAM EXAMPLE :

LDIA #00H ; initial TCB & HTC register
STATBL
STATBM
STATBH
OUTA P13
OUTA P12
OUTA P18
LDIA #0111B ; enable timer mode, internal pulse rate : CLK/2
OUTA P20
:
LDIA #00H ; disable timer mode
OUTA P20
INA P12 ; store the counter value to RAM[00] - RAM[04]
STA 00H
INA P13
STA 01H
LDATBL
STA 02H
LDATBM
STA 03H
LDATBH
STA 04H

7

Melody mode

In the melody mode, HTC will output the square wave to the PWM circuit or D/A converter.
The 8-bit tone frequency register is P13 and P12. The tone frequency will be changed when users output
the different data to P12. Thus, the data must be output to P13 before P12 when users want to change
the 8-bit tone frequency (TF). This mode is only available for DUAL operation mode.

P13 P12

3 2 1 0 3 2 1 0 Initial value : 0000 0000 ( TF )

Higher nibble register Lower nibble register

** F

= [ (CLK / 2:) / (100H - TF) ] / 2, TF = 0 ~ 255

TONE

** Example : CLK = 4.6MHz, RATE = 10, TF = 11001110 B= 0CEH.

F

= [ (4.6MHz / 25) / (100H - 0CEH) ] / 2 = 1430 Hz.

TONE

* This specification are subject to be changed without notice.

8.16.2001

28

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Volume control register (P17)

Preliminary

The are 16 levels of volume for sound generator. P17 is the volume control register.
Port17

3 2 1 0

VCR

VCR ts/tp

1 1 1 1 15/16

1 1 1 0 14/16

::
0 0 0 1 1/16

0 0 0 0 0/16

PROGRAM EXAMPLE:

LDIA #0CH
OUTA P13
LDIA #0EH
OUTA P12
LDIA #0111B ; volume control
OUTA P17
LDIA #1010B ; 1430 Hz tone output
OUTA P20

Initial value : 0000

ts

1

tp=

CLK/64 (CLK=4.6MHz)

tp

LCD DRIVER

It can directly drive the liquid crystal display (LCD) and has 64 segment pins, 16 or 32 common pins by mask
option. There are total 64x16 or 64x32 dots can be display. The V1~V5, VA and VB pins have to connect the
capacitors for LCD voltage multiplier.

16 common pins 32 common pins

Display dots 16x64 dots 32x64 dots
Bias 1/5 bias 1/5 bias
Duty 1/16 duty 1/32 duty
LCD display RAM Bank2 (P9=xx10B) Bank2(P9=xx10B), Bank3(P9=xx11B)
I/O or LCD pin COM0..15, COM0..31,
by mask option SEG0..59, SEG0..43,

P1[0..3]/SEG63..60 P7[0..3]/SEG47..44,

P6[0..3]/SEG51..48,
P5[0..3]/SEG55..52,
P2[0..3]/SEG59..56,
P1[0..3]/SEG63..60

* This specification are subject to be changed without notice.

8.16.2001

29

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

LCD driver control command register (P27) :

Preliminary

Port27 3210 Initial value : 0000

LDC VREF

LDC LCD display control VREF Reference voltage V5(1/5bias)*

0 LCD display disable 0 0 0 0.85V 4.25V
1 LCD display enable 0 0 1 0.90V 4.50V

* : Don't care. 0 1 0 0.95V 4.75V

1

: V5 is LCD working voltage 0 1 1 1.00V 5.00V

*

(suggestion only). 1 0 0 1.05V 5.25V

1 0 1 Reserved Reserved
1 1 * Reserved Reserved

Example :

LDIA #1001B ; enable LCD.
OUTA P27
:
LDIA #0000B ; disable LCD.
OUTA P27

LCD display data area:

The LCD display data is stored in the display data area of the data memory (RAM).

Bank 2

P9=xx10B 200-20Fh COM0

Bank 3

P9=xx11B300-30Fh

Address 0 1 2 3 4 5 6 7 8 9 A B C D E F

210-21Fh COM1
220-22Fh COM2
230-23Fh COM3
240-24Fh COM4
250-25Fh COM5
260-26Fh COM6
270-27Fh COM7
280-28Fh COM8

290-29Fh COM9
2A0-2AFh COM10
2B0-2BFh COM11

2C0-2CFh
2D0-2DFh

2E0-2EFh
2F0-2FFh

COM12
COM13
COM14
COM15

COM16
310-31Fh
320-32Fh
330-33Fh
340-34Fh
350-35Fh
360-36Fh
370-37Fh
380-38Fh
390-39Fh

3A0-3AFh
3B0-3BFh
3C0-3CFh
3D0-3DFh
3E0-3EFh

3F0-3FFh

COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31

1

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

* This specification are subject to be changed without notice.

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

8.16.2001

30

LCD waveform :

(1)1/32 duty, 1/5 bias

COM0
COM1

:
:
:
:

COM31

SEG1

SEG0

: ON
: OFF

COM0

V5
V4

V3
V2
V1

VSS

COM1

VSS

COM31

V5
V4

V3
V2
V1

VSS

SEG0

Preliminary

V5
V4

V3
V2
V1

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

V5
V4

V3
V2
V1

VSS

SEG0 - COM0

V5
V4
V3
V2
V1

VSS

ON

-V1

-V2

-V3

-V4

-V5

SEG0 - COM1

V5
V4
V3
V2
V1

VSS

OFF

-V1

-V2

-V3

-V4

-V5

Frame freq.=64Hz

* This specification are subject to be changed without notice.

8.16.2001

31

(2)1/16 duty, 1/5 bias

SEG1

SEG0

COM0
COM1

:
:
:
:

COM15

COM0

VSS

COM1

VSS

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

V5

V4
V3
V2
V1

V5
V4
V3
V2
V1

: ON
: OFF

COM15

V5
V4
V3
V2
V1

VSS

SEG0

V5
V4
V3
V2
V1

VSS

SEG0 - COM0

SEG0 - COM1

ON

OFF

VSS

-V1

-V2

-V3

-V4

-V5

VSS

-V1

-V2

-V3

-V4

-V5

V5
V4
V3
V2
V1

V5
V4
V3
V2
V1

Frame freq.= 64Hz

* This specification are subject to be changed without notice.

8.16.2001

32

SPEECH SYNTHESIZER

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Set tone freq.

P12,13 Write

P11 Write

Set data address
(write 5 times)

speech
ROM

P11 Read

Read data

Set melody mode

P20 Write

Sound effect generator

P24 Write

Set speech address
(write 4 times)

Set tone amplitude

P17 Write

speech

decoder

P23 Write

Set sample rate

P14.3 read

Speech active

D/A

PWM

BZ1/VO

BZ2

SPI interrupt

Block diagram of speech and sound effect

EM73A89B speech synthesizer operates as following :

1. Send the speech start address to the address latch by writing P24 four times.

2. Choose the sampling rate, enable the speech synthesizer by writing P23.

3. The ROM address counters send the ROM address A6 .. A19 to the speech ROM.

4. ACT is the speech acknowledge signal. When the speech synthesizer has voice output. ACT is high.
When ACT is changed from high to low, the speech synthesizer can generate the speech ending
interrupt SPI. The ACT signal can be read from P14.3.

SPEECH SYNTHESIZER CONTROL

Speech sample rate control register (P23 write) :

P23 3 2 1 0 Initial value : 1111

SR

SR Sample rate selection

0000 CLK/64/2/3 port 23 -- initialization is "1111".
0001 CLK/64/2/4 port 24 -- initialization is pointed to the low­0010 CLK/64/3/3 nibble of start address latch.
0011 CLK/64/3/4
0100 CLK/64/2/7 The frequency of CLK is decided by mask option.
0101 CLK/64/4/4
0110 CLK/64/6/3
0111 CLK/64/6/4
1*** Disable speech

* This specification are subject to be changed without notice.

8.16.2001

33

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Speech active flag (P14.3 read) :

P14 3 2 1 0 Initial value : 0000

ACT WKS SINT CPUS

ACT is the speech acknowledge signal. When the speech synthesizer has voice output, ACT is high. When

ACT is high → low, the speech synthesizer can generate the speech ending interrupt SPI.

P14(0,2) are CPU status flags (refer to CPU status). P14.1 is the interrupt source selector (refer to interrupt).

Speech start address register (P24 write) :

P24 3 2 1 0 Initial value : 1111

Port 24

P24L1 P24L2 P24L3 P24L4

A9 A8 A7 A6 A13 A12 A11 A10 A17 A16 A15 A14 - - A19 A18

Send the speech start address to the speech synthesizer by writing P24 four times. There is a pointer counter
to point the address latch (P24L1, P24L2, P24L3, P24L4). It will increase one when write P24. So, the first
time writing P24 to P24L1, the second time is P24L2, the third time is P24L3, the fourth time is P24L4 and the
fifth time is P24L1 latch again, ... etc. The pointer counter point to P24L1 when CPU is reset or P23 is written.
In the DUAL operation mode, the speech synthesizer is available. In the other operation modes, it is disable.

EM73A89B

PROGRAM EXAMPLE:

CHIP ROM16K

;--------RAM define area-----------------

DSEG

ORG 10H
HLBUF: RES 2 ; HL buffer for in terrupt
P9BUF: RES 1 ; P9 (RAM bank) buffer for interrupt

:
;----------Constant-------------------------­ACT EQU 143
SPEECH EQU 43200H

:
;----------Interrupt subroutine-----------

CSEG

ORG 004H

LBR S PI

:
SPI: OUTA P10 ; save Acc to general purpose register P10

INA P9

OUT #0000B,P9 10 instruction bytes

STA P9BUF ; save RAM bank to P9BUF

EXHL HLBUF ; save HL to HLBUF

:

:

EXHL HLBUF ; restore HLBUF to HL

LDA P9BUF ; resotre P9BUF to RAM bank 10 instruction bytes

OUTA P9

INA P10 ; restore register P10 to Acc

RTI

* This specification are subject to be changed without notice.

8.16.2001

34

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

;----------Main program------------------­MAIN :

:

LDIA #0000B

OUTA P14 ; select SPI interrupt

LDIA #SPEECH/40H ; set speech start address

OUTA P24

LDIA #SPEECH/400H

OUTA P24

LDIA #SPEECH/4000H

OUTA P24

LDIA #SPEECH/40000H

OUTA P24

LDIA #0011B ; set sampling rate and start playing

OUTA P23

:
WAIT :

TTP P14,3 ; wait speed end

B WAIT

:

Preliminary

USING SPEECH ROM AS DATA ROM

The speech ROM can be used for speech synthesizer and for data ROM simutaneously.
First, write initial address to P11 five times, then you can read P11 to get data, and the address counter
increases one automatically.
The read operation should be all done before you leave normal mode and change to slow mode.

Get speech ROM data (P11 read) :

3210

Port 11

Set speech ROM address (P11 write) :

3210

Port 11

P11L1 P11L2 P11L3 P11L4 P11L5

A3 A2 A1 A0 A7 A6 A5 A4 A11 A10 A9 A8 A15 A14 A13 A12 A19 A18 A17 A16

PROGRAM EXAMPLE:

DATA_ADR EQU 12345H ; the start address of the speech ROM

:
LDIA #DATA_ADR
OUTA P11
LDIA #DATA_ADR/10H
OUTA P11
LDIA #DATA_ADR/100H
OUTA P11
LDIA #DATA_ADR/1000H
OUTA P11
LDIA #DATA_ADR/10000H
OUTA P11

* This specification are subject to be changed without notice.

8.16.2001

35

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

; READ DATA
INA P11 ; read DATA_ADR
STA TEMP
INA P11
STA TEMP+1
:

WATCH-DOG-TIMER (WDT)

Watch-dog-timer can help user to detect the malfunction (runaway) of CPU and give system a timeup signal every
certain time. User can use the time up signal to give system a reset signal when system is fail.
This function is available by mask option. If the mask option of WDT is enabled, it will stop counting when CPU
is reseted or in the STOP operation mode.
The basic structure of Watch-Dog-Timer control is composed by a 4-stage binary counter and a control unit.
The WDT counter counts for a certain time to check the CPU status, if there is no malfunction happened, the
counter will be cleared and continue counting. Otherwise, if there is a malfunction happened, the WDT control
will send a WDT signal (low active) to reset CPU. The WDT checking period is assign by P21 (WDT command
port).

LXIN/2

13

WDT counter

0

12

3

RESET pin

counter clear request

WDT control

P21

WDT
command port

mask option

P21 is the control port of watch-dog-timer, and the WDT time up signal is connected to RESET.

Port 21 3210Initial value :0000

CWC * * WDT

CWC Clear watchdog timer counter

0 Clear counter then return to 1
1 Nothing

WDT Set watch-dog-timer detect time

0 3 x 213/LXIN = 3 x 213/32K Hz = 0.75 sec

13

1 7 x 2

/LXIN = 7 x 213/32K Hz = 1.75 sec

PROGRAM EXAMPLE

To enable WDT with 7 x 213/LXIN detection time.

LDIA #0001B
OUTA P21 ; set WDT detection time and clear WDT counter
:
:

* This specification are subject to be changed without notice.

8.16.2001

36

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

RESETTING FUNCTION

Preliminary

When CPU in normal working condition and RESET pin is held in low level for three instruction cycles at least,
then CPU begins to initialize the whole internal states, when RESET pin changes to high level, CPU begins
to work in normal condition.
The CPU internal state during reset condition is as following table :

Hardware condition in RESET state Initial value
Program counter 0000h
Status flag 01h
Interrupt enable flip-flop ( EI ) 00h
MASK0 ,1, 2, 3 00h
Interrupt latch ( IL ) 00h
P3, 9, 10, 11, 12, 13, 14, 16, 18, 19, 20, 21, 22, 00h
25, 27, 28, 29
P0, 1, 2, 4, 5, 6, 7, 8, 17, 23, 24 0Fh
CLK, LXIN Start oscillation

The RESET pin is a hysteresis input pin and it has a pull-up resistor available by mask option.
The simplest RESET circuit is connect RESET pin with a capacitor to VSS and a diode to VDD.

RESET

* This specification are subject to be changed without notice.

8.16.2001

37

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

EM73A89B I/O PORT DESCRIPTION :

Port Input function Output function Note

0 E Input port , wakeup function
1 E Input port E Output port / LCD segment pins
2 E Input port E Output port / LCD pins
3 I ROM bank selection I ROM bank selection
4 E Input port E Output port / RFO pins
5 E Input port E Output port / LCD pins
6 E Input port E Output port / LCD pins
7 E Input port E Output port / LCD pins
8 E Input port, wakeup function, E Output port

external interrupt input

9 I RAM bank selection I RAM bank selection
10 I General purpose register I General purpose register
11 I Read data register I Data ROM address register
12 -- I High speed counter register Low nibble
13 -- I High speed counter register High nibble
14 I CPU status, ACT flag I CPU status, interrupt souce selector
15 -- -­16 I STOP mode control register
17 I TONE volume control register
18 I HTC control register
19 I IDLE mode control register
20 I HTC control register
21 I WDT control register
22 I DUAL/SLOW mode control register
23 I Speech sampling rate register
24 I Speech start address register
25 I Timebase control register
26 -­27 I LCD control register
28 I Timer/counter A control register
29 I Timer/counter B control register
30 -­31 --

* This specification are subject to be changed without notice.

8.16.2001

38

APPLICATION CIRCUIT

V

BA T

0.1µF

3V

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

0.1µF

V

DD

P0.0

P0.1

P0.2

100

V

DD2

VA

VB

V

BA T

SEG0~
SEG63
COM0~
COM31

EM73A89B

LCD PANNEL

0.1µF

RESET

100Ω

0.1µF

BZ1

BZ2

RESET

LXOUT

VSS

EM73A89B

V5
V4
V3
V2
V1

LXIN

CLK

all 0.1µF

32.768KHz

20P

0.022µF

* This specification are subject to be changed without notice.

8.16.2001

39

RESET PIN TYPE

TYPE RESET-A

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

RESET

OSCILLATION PIN TYPE

TYPE OSC-B TYPE OSC_G

LXIN

LXOUT

TYPE OSC-H

VDD

LXIN

mask option

Crystal
Osc.

RC Osc.

CLK

Internal

Osc.

INPUT PIN TYPE

TYPE INPUT-A TYPE INPUT-B

: mask option

* This specification are subject to be changed without notice.

P0
/WAKEUP

WAKEUP function
mask option

TYPE INPUT_A

8.16.2001

40

I/O PIN TYPE

TYPE I/O TYPE I/O-P

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

mask option

path B

path A

TYPE I/O

Special function
output

Output
data
latch

Input
data

Output
data

: mask option

TYPE I/O-Q1 TYPE I/O-X1

: mask option

path B

path A

TYPE I/O_N

TYPE I/O_Q1

SEL

Special function
control input

Input data

Output

data

latch

Output
data

Path A : For set and clear bit of port instructions, data goes through path A from output data latch to CPU.
Path B : For input and test instructions, data from output pin go through path B to CPU and the output data latch

will be set to high.

* This specification are subject to be changed without notice.

8.16.2001

41

PAD DIAGRAM (16 COMMONS)

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26
SEG25

SEG24
SEG23

SEG22

SEG21

SEG20
SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9
SEG8

SEG7

SEG6

SEG5
SEG4
SEG3

SEG2

SEG1

SEG0

COM0

COM1
COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

VSS

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

V5

VA

VB

1

2

3

4

5

6

7
8

9

10
11

12

13
14

15

16

17

18

19

20
21

22

23

24

25

26

27

28

29

30

31

32

33

34

35
36

37

38
39

40

41

42

43

44

45

46

47
48

49

V1

V3

V4

122 115

EM73A89B

V2

SEG63/P1.0

SEG62/P1.1

(0,0)

SEG61/P1.2

SEG60/P1.3

SEG59

114116117118119120121123124125126

SEG58

113

SEG57

112

111

110

109

108

107
106

105

104

103

102

101

100

99

98

97

96

95

94
93

92

91

90

89

88

87

86

85

84

83

82

81

80

79
78

77

76

75

74

73

72

71

70

69

68

67

66
65

64

EM73A89B

SEG56

SEG55

SEG54

SEG53

SEG52
SEG51
SEG50

SEG49
SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39
SEG38

SEG37

SEG36

SEG35

SEG34

SEG33
SEG32

P7.3

P7.2

P7.1

P7.0

P6.3
P6.2

P6.1

P6.0

P5.3
P5.2

P5.1

P5.0

P2.3

P2.2

P2.1

P2.0

LXOUT

LXIN

VDD

CLK

P4.0

P4.1
P4.2

P4.3

50 51 52 53 54 55 56 57 58 59 60 61 62 63

VDD2

BZ1/VO

BZ2

VSS

TEST

RESET

P8.3

P8.2

P8.1

* This specification are subject to be changed without notice.

P8.0

P0.3

P0.2

P0.1

P0.0

8.16.2001

42

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

1 SEG31 -780.0 2753.9
2 SEG30 -780.0 2623.9
3 SEG29 -780.0 2496.4
4 SEG28 -780.0 2371.4
5 SEG27 -780.0 2246.4
6 SEG26 -780.0 2121.4
7 SEG25 -780.0 1996.4
8 SEG24 -780.0 1873.9

9 SEG23 -780.0 1753.9
10 SEG22 -780.0 1633.9
11 SEG21 -780.0 1513.9
12 SEG20 -780.0 1393.9
13 SEG19 -780.0 1276.4
14 SEG18 -780.0 1161.4
15 SEG17 -780.0 1046.4
16 SEG16 -780.0 931.4
17 SEG15 -780.0 816.4
18 SEG14 -780.0 703.9
19 SEG13 -780.0 593.9
20 SEG12 -780.0 483.9
21 SEG11 -780.0 373.9
22 SEG10 -780.0 263.9
23 SEG9 -780.0 156.4
24 SEG8 -780.0 51.4
25 SEG7 -780.0 -53.6
26 SEG6 -780.0 -158.6
27 SEG5 -780.0 -263.6
28 SEG4 -780.0 -371.1
29 SEG3 -780.0 -481.1
30 SEG2 -780.0 -591.1
31 SEG1 -780.0 -701.1
32 SEG0 -780.0 -811.1
33 COM0 -780.0 -923.6
34 COM1 -780.0 -1038.6
35 COM2 -780.0 -1153.6
36 COM3 -780.0 -1268.6
37 COM4 -780.0 -1383.6
38 COM5 -780.0 -1501.1
39 COM6 -780.0 -1621.1
40 COM7 -780.0 -1741.1

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

43

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

41 COM8 -780.0 -1861.1
42 COM9 -780.0 -1981.1
43 COM10 -780.0 -2103.6
44 COM11 -780.0 -2228.6
45 COM12 -780.0 -2353.6
46 COM13 -780.0 -2478.6
47 COM14 -780.0 -2603.6
48 COM15 -780.0 -2731.1
49 VSS -780.0 -2861.1
50 VDD2 -763.3 -3120.0
51 BZ1/VO -633.2 -3120.0
52 BZ2 -483.2 -3120.0
53 VSS -353.1 -3120.0
54 TEST -237.9 -3120.0
55 RESET -127.9 -3120.0
56 P8.3 -17.9 -3120.0
57 P8.2 92.1 -3120.0
58 P8.1 202.1 -3120.0
59 P8.0 312.1 -3120.0
60 P0.3 422.1 -3120.0
61 P0.2 532.1 -3120.0
62 P0.1 642.1 -3120.0
63 P0.0 759.6 -3120.0
64 P4.3 780.0 -2861.1
65 P4.2 780.0 -2731.1
66 P4.1 780.0 -2603.6
67 P4.0 780.0 -2478.6
68 CLK 780.0 -2353.6
69 VDD 780.0 -2228.6
70 LXIN 780.0 -2103.6
71 LXOUT 780.0 -1981.1
72 P2.0 780.0 -1861.1
73 P2.1 780.0 -1741.1
74 P2.2 780.0 -1621.1
75 P2.3 780.0 -1501.1
76 P5.0 780.0 -1383.6
77 P5.1 780.0 -1268.6
78 P5.2 780.0 -1153.6
79 P5.3 780.0 -1041.1
80 P6.0 780.0 -931.1

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

44

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

81 P6.1 780.0 -821.1
82 P6.2 780.0 -711.1
83 P6.3 780.0 -601.1
84 P7.0 780.0 -491.1
85 P7.1 780.0 -381.1
86 P7.2 780.0 -271.1
87 P7.3 780.0 -161.1
88 SEG32 780.0 -53.6
89 SEG33 780.0 51.4
90 SEG34 780.0 156.4
91 SEG35 780.0 263.9
92 SEG36 780.0 373.9
93 SEG37 780.0 483.9
94 SEG38 780.0 593.9
95 SEG39 780.0 703.9
96 SEG40 780.0 816.4
97 SEG41 780.0 931.4
98 SEG42 780.0 1046.1

99 SEG43 780.0 1161.4
100 SEG44 780.0 1276.4
101 SEG45 780.0 1393.9
102 SEG46 780.0 1513.9
103 SEG47 780.0 1633.9
104 SEG48 780.0 1753.9
105 SEG49 780.0 1873.9
106 SEG50 780.0 1996.4
107 SEG51 780.0 2121.4
108 SEG52 780.0 2246.4
109 SEG53 780.0 2371.4
110 SEG54 780.0 2496.4
111 SEG55 780.0 2623.9
112 SEG56 780.0 2753.9
113 SEG57 715.0 3120.0
114 SEG58 605.0 3120.0
115 SEG59 495.0 3120.0
116 SEG60/P1.3 385.0 3120.0
117 SEG61/P1.2 275.0 3120.0
118 SEG62/P1.1 165.0 3120.0
119 SEG63/P1.0 55.0 3120.0
120 V2 -55.0 3120.0

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

45

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

121 V1 -165.0 3120.0
122 V4 -275.0 3120.0
123 V3 -385.0 3120.0
124 V5 -495.0 3120.0
125 VB -605.0 3120.0
126 VA -715.0 3120.0

Unit : um
Chip size : 1810 x 6490um
Note : For PCB layout, IC substrate must be floated or connected to Vss.

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

46

PAD DIAGRAM (32 COMMONS)

SEG31

SEG30

SEG29

SEG28

SEG27

SEG26
SEG25

SEG24
SEG23

SEG22

SEG21

SEG20
SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9
SEG8

SEG7

SEG6

SEG5
SEG4
SEG3

SEG2

SEG1

SEG0

COM0

COM1
COM2

COM3

COM4

COM5

COM6

COM7

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

VSS

Preliminary

VA

VB

V3

V5

1

2

3

4

5

6

7
8

9

10
11

12

13
14

15

16

17

18

19

20
21

22

23

24

25

26

27

28

29

30

31

32

33

34

35
36

37

38
39

40

41

42

43

44

45

46

47
48

49

EM73A89B

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

V4

V1

122 115

V2

SEG62/P1.1

SEG63/P1.0

(0,0)

SEG61/P1.2

SEG60/P1.3

SEG59/P2.0

SEG58/P2.1

114116117118119120121123124125126

SEG57/P2.2

113

112

111

110

109

108

107
106

105

104

103

102

101

100

99

98

97

96

95

94
93

92

91

90

89

88

87

86

85

84

83

82

81

80

79
78

77

76

75

74

73

72

71

70

69

68

67

66
65

64

SEG56/P2.3

SEG55/P5.0

SEG54/P5.1

SEG53/P5.2

SEG52/P5.3
SEG51/P6.0
SEG50/P6.1

SEG49/P6.2
SEG48/P6.3

SEG47/P7.0

SEG46/P7.1

SEG45/P7.2

SEG44/P7.3

SEG43

SEG42

SEG41

SEG40

SEG39
SEG38

SEG37

SEG36

SEG35

SEG34

SEG33
SEG32

COM16

COM17

COM18

COM19

COM20
COM21

COM22

COM23

COM24
COM25

COM26

COM27

COM28

COM29

COM30

COM31

LXOUT

LXIN

VDD

CLK

P4.0

P4.1
P4.2

P4.3

50 51 52 53 54 55 56 57 58 59 60 61 62 63

VDD2

BZ1/VO

BZ2

VSS

TEST

RESET

P8.3

P8.2

P8.1

* This specification are subject to be changed without notice.

P8.0

P0.3

P0.2

P0.1

P0.0

8.16.2001

47

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

1 SEG31 -780.0 2753.9
2 SEG30 -780.0 2623.9
3 SEG29 -780.0 2496.4
4 SEG28 -780.0 2371.4
5 SEG27 -780.0 2246.4
6 SEG26 -780.0 2121.4
7 SEG25 -780.0 1996.4
8 SEG24 -780.0 1873.9

9 SEG23 -780.0 1753.9
10 SEG22 -780.0 1633.9
11 SEG21 -780.0 1513.9
12 SEG20 -780.0 1393.9
13 SEG19 -780.0 1276.4
14 SEG18 -780.0 1161.4
15 SEG17 -780.0 1046.4
16 SEG16 -780.0 931.4
17 SEG15 -780.0 816.4
18 SEG14 -780.0 703.9
19 SEG13 -780.0 593.9
20 SEG12 -780.0 483.9
21 SEG11 -780.0 373.9
22 SEG10 -780.0 263.9
23 SEG9 -780.0 156.4
24 SEG8 -780.0 51.4
25 SEG7 -780.0 -53.6
26 SEG6 -780.0 -158.6
27 SEG5 -780.0 -263.6
28 SEG4 -780.0 -371.1
29 SEG3 -780.0 -481.1
30 SEG2 -780.0 -591.1
31 SEG1 -780.0 -701.1
32 SEG0 -780.0 -811.1
33 COM0 -780.0 -923.6
34 COM1 -780.0 -1038.6
35 COM2 -780.0 -1153.6
36 COM3 -780.0 -1268.6
37 COM4 -780.0 -1383.6
38 COM5 -780.0 -1501.1
39 COM6 -780.0 -1621.1
40 COM7 -780.0 -1741.1

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

48

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

41 COM8 -780.0 -1861.1
42 COM9 -780.0 -1981.1
43 COM10 -780.0 -2103.6
44 COM11 -780.0 -2228.6
45 COM12 -780.0 -2353.6
46 COM13 -780.0 -2478.6
47 COM14 -780.0 -2603.6
48 COM15 -780.0 -2731.1
49 VSS -780.0 -2861.1
50 VDD2 -763.3 -3120.0
51 BZ1/VO -633.2 -3120.0
52 BZ2 -483.2 -3120.0
53 VSS -353.1 -3120.0
54 TEST -237.9 -3120.0
55 RESET -127.9 -3120.0
56 P8.3 -17.9 -3120.0
57 P8.2 92.1 -3120.0
58 P8.1 202.1 -3120.0
59 P8.0 312.1 -3120.0
60 P0.3 422.1 -3120.0
61 P0.2 532.1 -3120.0
62 P0.1 642.1 -3120.0
63 P0.0 759.6 -3120.0
64 P4.3 780.0 -2861.1
65 P4.2 780.0 -2731.1
66 P4.1 780.0 -2603.6
67 P4.0 780.0 -2478.6
68 CLK 780.0 -2353.6
69 VDD 780.0 -2228.6
70 LXIN 780.0 -2103.6
71 LXOUT 780.0 -1981.1
72 COM31 780.0 -1861.1
73 COM30 780.0 -1741.1
74 COM29 780.0 -1621.1
75 COM28 780.0 -1501.1
76 COM27 780.0 -1383.6
77 COM26 780.0 -1268.6
78 COM25 780.0 -1153.6
79 COM24 780.0 -1041.1
80 COM23 780.0 -931.1

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

49

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

81 COM22 780.0 -821.1
82 COM21 780.0 -711.1
83 COM20 780.0 -601.1
84 COM19 780.0 -491.1
85 COM18 780.0 -381.1
86 COM17 780.0 -271.1
87 COM16 780.0 -161.1
88 SEG32 780.0 -53.6
89 SEG33 780.0 51.4
90 SEG34 780.0 156.4
91 SEG35 780.0 263.9
92 SEG36 780.0 373.9
93 SEG37 780.0 483.9
94 SEG38 780.0 593.9
95 SEG39 780.0 703.9
96 SEG40 780.0 816.4
97 SEG41 780.0 931.4
98 SEG42 780.0 1046.1

99 SEG43 780.0 1161.4
100 SEG44/P7.3 780.0 1276.4
101 SEG45/P7.2 780.0 1393.9
102 SEG46/P7.1 780.0 1513.9
103 SEG47/P7.0 780.0 1633.9
104 SEG48/P6.3 780.0 1753.9
105 SEG49/P6.2 780.0 1873.9
106 SEG50/P6.1 780.0 1996.4
107 SEG51/P6.0 780.0 2121.4
108 SEG52/P5.3 780.0 2246.4
109 SEG53/P5.2 780.0 2371.4
110 SEG54/P5.1 780.0 2496.4
111 SEG55/P5.0 780.0 2623.9
112 SEG56/P2.3 780.0 2753.9
113 SEG57/P2.2 715.0 3120.0
114 SEG58/P2.1 605.0 3120.0
115 SEG59/P2.0 495.0 3120.0
116 SEG60/P1.3 385.0 3120.0
117 SEG61/P1.2 275.0 3120.0
118 SEG62/P1.1 165.0 3120.0
119 SEG63/P1.0 55.0 3120.0
120 V2 -55.0 3120.0

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

50

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Pad No. Symbol X Y

121 V1 -165.0 3120.0
122 V4 -275.0 3120.0
123 V3 -385.0 3120.0
124 V5 -495.0 3120.0
125 VB -605.0 3120.0
126 VA -715.0 3120.0

Unit : um
Chip size : 1810 x 6490um
Note : For PCB layout, IC substrate must be floated or connected to Vss.

EM73A89B

* This specification are subject to be changed without notice.

8.16.2001

51

ABSOLUTE MAXIMUM RATINGS

Items Sym. Ratings Conditions

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Supply Voltage V
Input Voltage V
Output Voltage V
Power Dissipation P
Operating Temperature T
Storage Temperature T

DD

IN

O

D

OPR

STG

-0.5V to 3.6V

-0.5V to VDD+0.5V

-0.5V to VDD+0.5V
300mW T

-30oC to 70oC

-55oC to 125oC

OPR

=50oC

RECOMMANDED OPERATING CONDITIONS

Items Sym. Ratings Conditions

Supply Voltage V
Input Voltage V

Operating Frequency F

DD

IH

V

IL

C

Fs 32KHz LXIN,LXOUT

DC ELECTRICAL CHARACTERISTICS (VDD=3±0.3V, VSS=0V, T

2.2V to 3.6V

0.90xVDD to V
0V to 0.10xV

DD

DD

4.6MHz ~ 9.2MHz CLK

=25oC)

OPR

Parameters Sym. Min. Typ. Max. Unit Conditions

Supply current I

Hysteresis voltage V

V

Input current I

I

Output voltage V

V
Leakage current I
Input resistor R

DD

HYS+

HYS-

IH

IL

OH

OL

LO

IN

-0.51.2mAV

=3.3V,DUAL mode,no load,

DD

Fc=4.6MHz ,Fs=32KHz

-3545µAV

-3040µAV

-712µAV

-0.1 1µAV

0.50V

0.20V

DD

DD

- 0.75V

- 0.40V

V RESET, P0, P8

DD

V

DD

=3.3V,SLOW mode,Fs=32KHz, LCD on

DD

=3.3V, IDLE mode, LCD on

DD

=3.3V, IDLE mode, LCD off

DD

=3.3V, STOP mode

DD

- - ±1 µA P0, RESET, VDD=3.3V,VIH=3.3/0V

- - ±1 µA Open-drain, V

=3.3V,VIH=3.3/0V

DD

- -250 -500 µA Push-pull (normal current push-pull)
V

=3.3V, VIL=0.4V

DD

- -20 -25 µA Push-pull (low current push-pull)
V

=3.3V, VIL=0.4V

DD

2.4 - - V Push-pull, (high current push-pull)
V

=2.7V, IOH=-0.9mA

DD

2.0 2.4 - V Push-pull, (normal current push-pull)
V

=2.7V, IOH=-40µA

DD

- 0.15 0.3 V VDD=2.7V, IOL=0.9mA

- - 1 µA Open-drain, VDD=3.3V, VO=3.3V

100 200 300 KΩ P0, V
300 600 900 KΩ RESET, V

=3.3V

DD

=3.3V

DD

* This specification are subject to be changed without notice.

8.16.2001

52

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

EM73A89B

Output current I
of BZ1, BZ2 I

OH

OL

I

OH

I

OL

30 - - mA VDD=3.0V, VBZ=1.5V,
30 - - mA mask option : small size
75 - - mA VDD=3.0V, VBZ=1.5V,
75 - - mA mask option : large size

Output current of VO 2 3 4 mA VDD=3.0V, vo=0.7V
LCD reference V

REF

0.765 0.85 0.935 V VDD=3.0V,no load,VREF=000

voltage 0.81 0.90 0.99 V VDD=3.0V,no load,VREF=001

0.855 0.95 1.045 V VDD=3.0V,no load,VREF=010

0.9 1.00 1.1 V VDD=3.0V,no load,VREF=011

0.945 1.05 1.155 V VDD=3.0V,no load,VREF=100

* This specification are subject to be changed without notice.

8.16.2001

53

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

INSTRUCTION TABLE

Preliminary

(1) Data Transfer

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZ S

LDA x 0110 1010 xxxx xxxx Acc←RAM[x] 2 2 - Z 1
LDAM 0101 1010 Acc ←RAM[HL] 1 1 - Z 1
LDAX 0110 0101 Acc←ROM[DP]
LDAXI 0110 0111 Acc←ROM[DP]

L

,DP+1 1 2 - Z 1

H

LDH #k 1001 kkkk HR←k11--1
LDHL x 0100 1110 xxxx xx00 LR←RAM[x],HR←RAM[x+1] 2 2 - - 1
LDIA #k 1101 kkkk Acc←k11-Z1
LDL #k 1000 kkkk LR←k11--1
STA x 0110 1001 xxxx xxxx RAM[x]←Acc 2 2 - - 1
STAM 0101 1001 RAM[HL]←Acc 1 1 - - 1
STAMD 0111 1101 RAM[HL]←Acc, LR-1 1 1 - Z C
STAMI 0111 1111 RAM[HL]←Acc, LR+1 1 1 - Z C'
STD #k,y 0100 1000 kkkk yyyy RAM[y]←k22--1
STDMI #k 1010 kkkk RAM[HL]←k, LR+1 1 1 - Z C'
THA 0111 0110 Acc←HR 1 1 - Z 1
TLA 0111 0100 Acc←LR 1 1 - Z 1

12-Z1

(2) Rotate

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

RLCA 0101 0000 ←CF←Acc← 11CZC'
RRCA 0101 0001 →CF→Acc→ 11CZC'

(3) Arithmetic operation

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

C ZS

ADCAM 0111 0000 Acc←Acc + RAM[HL] + CF 1 1 C Z C'
ADD #k,y 0100 1001 kkkk yyyy RAM[y]←RAM[y] + k 2 2 - Z C'
ADDA #k 0110 1110 0101 kkkk Acc←Acc+k 2 2 - Z C'
ADDAM 0111 0001 Acc←Acc + RAM[HL] 1 1 - Z C'
ADDH #k 0110 1110 1001 kkkk HR←HR+k 2 2 - Z C'
ADDL #k 0110 1110 0001 kkkk LR←LR+k 2 2 - Z C'
ADDM #k 0110 1110 1101 kkkk RAM[HL]←RAM[HL] +k 2 2 - Z C'
DECA 0101 1100 Acc←Acc-1 1 1 - Z C
DECL 0111 1100 LR←LR-1 1 1 - Z C
DECM 0101 1101 RAM[HL]←RAM[HL] -1 1 1 - Z C
INCA 0101 1110 Acc←Acc + 1 1 1 - Z C'

* This specification are subject to be changed without notice.

8.16.2001

54

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

INCL 0111 1110 LR←LR + 1 1 1 - Z C'
INCM 0101 1111 RAM[HL]←RAM[HL]+1 1 1 - Z C'
SUBA #k 0110 1110 0111 kkkk Acc←k-Acc 2 2 - Z C
SBCAM 0111 0010 Acc←RAM[HLl - Acc - CF' 1 1 C Z C
SUBM #k 0110 1110 1111 kkkk RAM[HL]←k - RAM[HL] 2 2 - Z C

(4) Logical operation

Mnemonic Object code (binary) Operation description Byte Cycle Flag

CZS

ANDA #k 0110 1110 0110 kkkk Acc←Acc&k 2 2 - Z Z'
ANDAM 0111 1011 Acc←Acc & RAM[HL] 1 1 - Z Z'
ANDM #k 0110 1110 1110 kkkk RAM[HL]←RAM[HL]&k 2 2 - Z Z'
ORA #k 0110 1110 0100 kkkk Acc←Acc k 2 2 - Z Z'
ORAM 0111 1000 Acc ←Acc RAM[HL] 1 1 - Z Z'
ORM #k 0110 1110 1100 kkkk RAM[HL]←RAM[HL] k 2 2 - Z Z'
XORAM 0111 1001 Acc←Acc^RAM[HL] 1 1 - Z Z'

- -

- -

- -

(5) Exchange

Mnemonic Object code (binary) Operation description Byte Cycle Flag

CZS

EXA x 0110 1000 xxxx xxxx Acc↔RAM[x] 2 2 - Z 1
EXAH 0110 0110 Acc↔HR 1 2 - Z 1
EXAL 0110 0100 Acc↔LR 1 2 - Z 1
EXAM 0101 1000 Acc↔RAM[HL] 1 1 - Z 1
EXHL x 0100 1100 xxxx xx00 LR↔RAM[x],

HR↔RAM[x+1] 2 2 - - 1

(6) Branch

Mnemonic Object code (binary) Operation description Byte Cycle Flag

CZS

SBR a 00aa aaaa If SF=1 then PC←PC

12-6.a5-0

11--1

else null

LBR a 1100 aaaa aaaa aaaa If SF= 1 then PC←a else null 2 2 - - 1
SLBR a 0101 0101 1100 aaaa If SF=1 then PC←a else null 3 3 - - 1

aaaa aaaa (a:1000~1FFFh)

0101 0111 1100 aaaa

aaaa aaaa (a:0000~0FFFh)

(7) Compare

Mnemonic Object code (binary) Operation description Byte Cycle Flag

CZS

CMP #k,y 0100 1011 kkkk yyyy k-RAM[y] 2 2 C Z Z'
CMPA x 0110 1011 xxxx xxxx RAM[x]-Acc 2 2 C Z Z'

* This specification are subject to be changed without notice.

8.16.2001

55

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

CMPAM 0111 0011 RAM[HL] - Acc 1 1 C Z Z'
CMPH #k 0110 1110 1011 kkkk k - HR 2 2 - Z C
CMPIA #k 1011 kkkk k - Acc 1 1 C Z Z'
CMPL #k 0110 1110 0011 kkkk k-LR 2 2 - Z C

(8) Bit manipulation

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

CLM b 1111 00bb RAM[HL]
CLP p,b 0110 1101 11bb pppp PORT[p]
CLPL 0110 0000 PORT[LR
CLR y,b 0110 1100 11bb yyyy RAM[y]
SEM b 1111 01bb RAM[HL]
SEP p,b 0110 1101 01bb pppp PORT[p]
SEPL 0110 0010 PORT[LR
SET y,b 0110 1100 01bb yyyy RAM[y]

TF y,b 0110 1100 00bb yyyy SF←RAM[y]
TFA b 1111 10bb SF←Acc
TFM b 1111 11bb SF←RAM[HL]
TFP p,b 0110 1101 00bb pppp SF←PORT[p]
TFPL 0110 0001 SF←PORT[LR
TT y,b 0110 1100 10bb yyyy SF←RAM[y]
TTP p,b 0110 1101 10bb pppp SF←PORT[p]

←011--1

b

←022--1

b

+4]LR

3-2

←022--1

b

←111--1

b

←122--1

b

+4]LR

3-2

←122--1

b

b

'11--*

b

b

←012--1

1-0

←112 --1

l-0

'22--*

'11--*

b

'22--*

b

+4]LR

3-2

'1 2--*

1-0

22--*

b

22--*

(9) Subroutine

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

LCALL a 0100 0aaa aaaa aaaa STACK[SP]←PC, 2 2 - - -

SP←SP -1, PC←a

SCALL a 1110 nnnn STACK[SP]←PC, 1 2 - - -

SP←SP - 1, PC←a, a = 8n + 6
(n =1∼15),0086h (n = 0)

RET 0100 1111 SP←SP + 1, PC←STACK[SP] 1 2 - - -

(10) Input/output

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

INA p 0110 1111 0100 pppp Acc←PORT[p] 2 2 - Z Z'
INM p 0110 1111 1100 pppp RAM[HL]←PORT[p] 2 2 - - Z'
OUT #k,p 0100 1010 kkkk pppp PORT[p]←k22--1
OUTA p 0110 1111 000p pppp PORT[p]←Acc 2 2 - - 1
OUTM p 0110 1111 100p pppp PORT[p]←RAM[HL] 2 2 - - 1

* This specification are subject to be changed without notice.

8.16.2001

56

EM73A89B

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

(11) Flag manipulation

Preliminary

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

TFCFC 0101 0011 SF←CF', CF←0110-*
TTCFS 0101 0010 SF←CF, CF←1111-*
TZS 0101 1011 SF←ZF 1 1 - - *

(12) Interrupt control

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

CIL r 0110 0011 11rr rrrr IL←IL & r 2 2 - - 1
DICIL r 0110 0011 10rr rrrr EIF←0,IL←IL&r 2 2 - - 1
EICIL r 0110 0011 01rr rrrr EIF←1,IL←IL&r 2 2 - - 1
EXAE 0111 0101 MASK↔Acc 1 1 - - 1
RTI 0100 1101 SP←SP+1,FLAG.PC 1 2 * * *

←STACK[SP],EIF ←1

(13) CPU control

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

NOP 0101 0110 no operation 1 1 - - -

(14) Timer/Counter & Data pointer & Stack pointer control

Mnemonic Object code ( binary ) Operation description Byte Cycle Flag

CZS

LDADPL 0110 1010 1111 1100 Acc←[DP]
LDADPM 0110 1010 1111 1101 Acc←[DP]
LDADPH 0110 1010 1111 1110 Acc←[DP]

L

M

H

22-Z1
22-Z1
22-Z1

LDASP 0110 1010 1111 1111 Acc←SP 2 2 - Z 1
LDATAL 0110 1010 1111 0100 Acc←[TA]
LDATAM 0110 1010 1111 0101 Acc←[TA]
LDATAH 0110 1010 1111 0110 Acc←[TA]
LDATBL 0110 1010 1111 1000 Acc←[TB]
LDATBM 0110 1010 1111 1001 Acc←[TB]
LDATBH 0110 1010 1111 1010 Acc←[TB]

STADPL 0110 1001 1111 1100 [DP]
STADPM 0110 1001 1111 1101 [DP]
STADPH 0110 1001 1111 1110 [DP]

←Acc 2 2 - - 1

L

←Acc 2 2 - - 1

M

←Acc 2 2 - - 1

H

L

M

H

L

M

H

22-Z1
22-Z1
22 -Z1
22-Z1
22-Z1
22-Z1

STASP 0110 1001 1111 1111 SP←Acc 2 2 - - 1

STATAL 0110 1001 1111 0100 [TA]
STATAM 0110 1001 1111 0101 [TA]
STATAH 0110 1001 1111 0110 [TA]
STATBL 0110 1001 1111 1000 [ TB]
STATBM 0110 1001 1111 1001 [TB]
STATBH 0110 1001 1111 1010 [TB]

* This specification are subject to be changed without notice.

←Acc 2 2 - - 1

L

←Acc 2 2 - - 1

M

←Acc 2 2 - - 1

H

←Acc 2 2 - - 1

L

←Acc 2 2 - - 1

M

←Acc 2 2 - - 1

H

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57

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

**** SYMBOL DESCRIPTION

Symbol Description Symbol Description

HR H register LR L register
PC Program counter DP Data pointer
SP Stack pointer STACK[SP] Stack specified by SP
A

CC

CF Carry flag ZF Zero flag
SF Status flag EI Enable interrupt register
IL Interrupt latch MASK Interrupt mask

PORT[p] Port ( address : p ) ΤΑ Timer/counter A
ΤΒ Timer/counter B RAM[HL] Data memory (address : HL )

RAM[x] Data memory (address : x ) ROM[DP]
ROM[DP]
[DP]

M

[TA]L([TB]L) Low 4-bit of timer/counter A [TA]M([TB]M) Middle 4-bit of timer/counter A

[TA]H([TB]H) High 4-bit of timer/counter A LR

LR

3-2

PC

12-6

↔ Exchange + Addition

- Substraction & Logic AND

- -

#k 4-bit immediate data x 8-bit RAM address
y 4-bit zero-page address p 4-bit or 5-bit port address
b Bit address r 6-bit interrupt latch

Accumulator FLAG All flags

Low 4-bit of program memory
Low 4-bit of data pointer register
High 4-bit of data pointer register

High 4-bit of program memory [DP]

H

Middle 4-bit of data pointer register [DP]

L

L

H

(timer/counter B) register (timer/counter B) register

1-0

Contents of bit assigned by bit
(timer/counter B) register 1 to 0 of LR
Bit 3 to 2 of LR a

5-0

Bit 5 to 0 of destination address for

branch instruction

Bit 12 to 6 of program counter ← Transfer

Logic OR ^ Logic XOR
Inverse operation . Concatenation

EM73A89B

* This specification are subject to be changed without notice.

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