Datasheet EM637327TQ-8, EM637327TQ-7, EM637327TQ-6, EM637327TQ-5, EM637327Q-8 Datasheet (ETRON)
...Page 1
EtronTech
EM637327
D
1Mega x 32 SGRAM
Preliminary (08/99)
Features
Fast access time from clock: 4.5/5.5/5.5/6 ns
•
Fast clock rate: 200/166/143/125 MHz
•
Fully synchronous operation
•
Internal pipelined architecture
•
Dual internal banks (512K x 32bit x 2bank)
•
Programmable Mode
•
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
•
Individual byte controlled by DQM0-3
•
Block write and write-per-bit capability
•
Auto Refresh and Self Refresh
•
2048 refresh cycles/32ms
•
Single +3.3V ± 0.3V power supply
•
Interface: LVTTL
•
JEDEC 100-pin Plastic package
•
- QFP (body thickness=2.8mm)
- TQFP1.4 (body thickness=1.4mm)
Key Specifications
EM637327 - 5/6/7/8
Clock Cycle time(min.)
t
CK3
Row Active time(max.)
t
RAS
Access time from CLK(max.)
t
AC3
Row Cycle time(min.)
t
RC
5/6/7/8 ns
25/30/35/40 ns
4.5/5.5/5.5/6 ns
55/60/63/72 ns
Ordering Information
Part Number Frequency Package
EM637327Q-5 200 MHz QFP
EM637327TQ-5 200 MHz TQFP1.4
EM637327Q-6 166 MHz QFP
EM637327TQ-6 166 MHz TQFP1.4
EM637327Q-7 143 MHz QFP
EM637327TQ-7 143 MHz TQFP1.4
EM637327Q-8 125 MHz QFP
EM637327TQ-8 125 MHz TQFP1.4
Pin Assignment (Top View)
DQ29
DQ30
DQ31
VSSQ
DQ0
DQ1
DQ2
V
NC
DD
100
1
DQ3
2
VDDQ
3
DQ4
4
DQ5
5
V
SSQ
6
DQ6
7
DQ7
8
VDDQ
VSSQ
VDDQ
VDD
V
VSSQ
VDDQ
WE#
CS0#
BS
A9
9
10
11
12
13
14
15
16
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
V
A3A2A1
A0
D
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM0
DQM2
CAS#
RAS#
Overview
The EM637327 SGRAM is a high-speed CMOS
synchronous graphics DRAM containing 32 Mbits. It is
internally configured as a dual 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 32 bit banks is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the
SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM637327 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth.
VSSQ
VSS
NCNCNCNCNCNCNCNCNC
81828384858687888990919293949596979899
80
DQ28
79
VDDQ
78
DQ27
77
DQ26
76
V
SSQ
75
DQ25
74
DQ24
73
VDDQ
72
DQ15
71
DQ14
70
VSSQ
69
DQ13
68
DQ12
67
VDDQ
66
VSS
65
V
DD
64
DQ11
63
DQ10
62
VSSQ
61
DQ 9
60
DQ 8
59
VDDQ
58
NC
57
DQM3
56
DQM1
55
CL K
54
CKE
53
DSF
52
NC
51
50494847464544434241403938373635343332
A8 (AP)
A10NCNCNCNCNCNCNCNCNC
A7A6A5A4VSS
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Page 2
EtronTech
Block Diagram
1Mega x 32 SGRAM
EM637327
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
A8
A0
A7
A9
A10
BS
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
ADDRESS
BUFFER
REFRESH
COUNTER
CONTROL
SIGNA L
GENERATOR
MODE
REGIS TER
SPECIAL
MODE
REGIS TER
Row Decoder
COLOR
REGISTE R
MASK
REGISTE R
Row Decoder
Column Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Amplifier
Sense Amplifier
2048 X 256 X 32
CELL ARRAY
(BANK #1)
Column Decoder
DQS
BUFFER
DQM0~3
DQ0
¢x
DQ31
Preliminary
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August 1999
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EtronTech
Pin Descriptions
Symbol Type Description
1Mega x 32 SGRAM
Table 1. Pin Details of EM637327
EM637327
CLK Input
CKE Input
BS Input
A0-A10 Input
CS# Input
Clock:
positive edge of CLK. CLK also increments the internal burst counter and controls the
output registers.
Clock Enable:
low synchronously with clock(set-up and hold time same as other inputs), the internal clock
is suspended from the next clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. When both banks are in the idle state, deactivating the
clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous
except after the device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are disabled
during Power Down and Self Refresh modes, providing low standby power.
Bank Select:
command is being applied. BS is also used to program the 11th bit of the Mode and
Special Mode registers.
Address Inputs:
A0-A10) and Read/Write command (column address A0-A7 with A8 defining Auto
Precharge) to select one location out of the 512K available in the respective bank. During
a Precharge command, A8 is sampled to determine if both banks are to be precharged (A8
= HIGH). The address inputs also provide the op-code during a Mode Register Set or
Special Mode Register Set command.
Chip Select:
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for
external bank selection on systems with multiple banks. It is considered part of the
command code.
CLK is driven by the system clock. All SGRAM input signals are sampled on the
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes
BS defines to which bank the BankActivate, Read, Write, or BankPrecharge
A0-A10 are sampled during the BankActivate command (row address
CS# enables (sampled LOW) and disables (sampled HIGH) the command
RAS# Input
CAS# Input
WE# Input
DSF Input
Row Address Strobe:
with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#
and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate
command or the Precharge command is selected by the WE# signal. When the WE# is
asserted "HIGH," the BankActivate command is selected and the bank designated by BS is
turned on to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the precharge
operation.
Column Address Strobe:
conjunction with the RAS# and WE# signals and is latched at the positive edges of CLK.
When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by
asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE#
"LOW" or "HIGH."
Write Enable:
RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is
used to select the BankActivate or Precharge command and Read or Write command.
Define Special Function:
with the RAS# and CAS# and WE# signals and is latched at the positive edges of CLK.
The DSF input is used to select the masked write disable/enable command and block write
command, and the Special Mode Register Set cycle.
The WE# signal defines the operation commands in conjunction with the
The RAS# signal defines the operation commands in conjunction
The CAS# signal defines the operation commands in
The DSF signal defines the operation commands in conjunction
Preliminary
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EtronTech
1Mega x 32 SGRAM
EM637327
DQM0 -
DQM3
DQ0-
DQ31
NC -
V
DDQ
V
SSQ
V
DD
V
SS
Input
Input/
Output
Supply
Supply
Supply
Supply
Data Input/Output Mask:
controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input
data is masked when DQM is sampled HIGH during a write cycle. Output data is masked
(two-clock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7DQ0.
Data I/O:
CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also serve as
column/byte mask inputs during Block Writes.
No Connect:
DQ Power:
DQ Ground:
Power Supply:
Ground
The DQ0-31 input and output data are synchronized with the positive edges of
These pins should be left unconnected.
Provide isolated power to DQs for improved noise immunity.
Provide isolated ground to DQs for improved noise immunity.
+3.3V±0.3V
DQM0-DQM3 are byte specific, nonpersistent I/O buffer
Preliminary
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1Mega x 32 SGRAM
EM637327
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command State CKE
BankActivate & Masked Write Disable
BankActivate & Masked Write Enable
BankPrecharge
PrechargeAll
Write
Block Write Command
Write and AutoPrecharge
Block Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
Special Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Clock Suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKEn signal is input level when commands are provided.
CKE
signal is input level one clock cycle before the commands are provided.
n-1
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. The Special Mode Register Set is also available in Row Active State.
6. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
7. DQM0-3
(7)
BS A8 A
CS# RAS# CAS# WE# DSF
DDR
Idle
Idle
(3)
(3)
CKEnDQM
n-1
H X X V V V L L H H L
H X X V V V L L H H H
Any H X X V L X L L H L L
Any H X X X H X L L H L L
(3)
Active
Active
Active
Active
Active
Active
H X X V L V L H L L L
(3)
H X X V L V L H L L H
(3)
H X X V H V L H L L L
(3)
H X X V H V L H L L H
(3)
H X X V L V L H L H L
(3)
H X X V H V L H L H L
Idle H X X V L V L L L L L
(5)
Idle
H X X X X V L L L L H
Any H X X X X X L H H H X
(4)
Active
H X X X X X L H H L L
Any H X X X X X H X X X X
Idle H H X X X X L L L H L
Idle H L X X X X L L L H L
Idle L H X X X X H X X X X
(SelfRefresh)
L H H H X
Active H L X X X X X X X X X
(6)
Any
H L X X X X H X X X X
L H H H L
Active L H X X X X X X X X X
Any L H X X X X H X X X X
(PowerDown)
L H H H L
Active H X L X X X X X X X X
Active H X H X X X X X X X X
Preliminary
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EtronTech
Commands
1 BankActivate & Masked Write Disable command
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal.
By latching the row address on A0 to A9 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of t
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of both banks. t
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
T0 T 1 T2 T3 Tn+ 3 Tn+ 4 Tn+5 Tn+6
(min.) specifies the minimum time required between activating
RRD
1Mega x 32 SGRAM
EM637327
(min.)
RCD
CLK
ADDRESS
COM MA ND
Bank A
Row Addr.
Bank A
Activate
RAS# - CAS# delay (
NOP
t
NOP
RCD)
Bank A
Col Addr.
R/W A with
AutoPrecharge
RAS# Cycle time (
..............
..............
..............
Bank B
Row Addr.
Bank B
Activate
t
RC)
AutoPrecharge
Begin
RAS# - RAS# delay time (
NOP
NOP
t
RRD)
: "H" or "L"
BankActivate Command Cycle
(Burst Length = n, CAS# Latency = 3)
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this
command is performed, the Write command and the Block Write command perform the masked
write operation. In the masked write and the masked block write functions, the I/O mask data that
was stored in the write mask register is used.
3 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A8 = "L", A0-A7, A9-A10 = Don't care)
The BankPrecharge command precharges the bank disignated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
t
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
RAS
bank can be active is specified by t
in any active bank within t
(max.). At the end of precharge, the precharged bank is still in the idle
RAS
(max.). Therefore, the precharge function must be performed
RAS
state and is ready to be activated again.
Bank A
Row Addr.
Bank A
Activate
4 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A8 = "L", A0-A7, A9-A10 = Don't
care)The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
5 Read command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A8 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go
Preliminary
(min.) before the Read command is
RCD
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EtronTech
1Mega x 32 SGRAM
EM637327
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
T0 T 1 T2 T3 T4 T5 T6 T7 T8
CLK
COM MA ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
CAS# latency=3
t
, DQ's
CK3
READ A NOP
DOUT A0DOUT A
NOP NOP NOP N OP N OP NOP NOP
DOUT A0DOUT A
Burst Read Operation
DOUT A2DOUT A
1
1
DOUT A0DOUT A
3
DOUT A2DOUT A
DOUT A2DOUT A
1
3
(Burst Length = 4, CAS# Latency = 1, 2, 3)
3
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier
(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function
may be interrupted by a subsequent Read or Write/Block Write command to the same bank or the
other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank too. The interrupt coming from the Read command can
occur on any clock cycle following a previous Read command (refer to the following figure).
T0 T 1 T2 T3 T4 T 5 T6 T 7 T8
CLK
COM MA ND
READ A READ B NOP NOP NOP NOP NO P NOP NOP
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
CAS# latency=3
t
, DQ's
CK3
Read Interrupted by a Read
DOUT A0DOUT B
DOUT A0DOUT B
DOUT B1DOUT B
0
DOUT A0DOUT B
(Burst Length = 4, CAS# Latency = 1, 2, 3)
DOUT B1DOUT B
0
DOUT B
2
DOUT B1DOUT B
0
3
DOUT B
2
3
DOUT B
2
3
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes
from a Write/Block Write command. The DQMs must be asserted (HIGH) at least two clocks prior to
the Write/Block Write command to suppress data-out on the DQ pins. To guarantee the DQ pins
against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the
last read data and the Write/Block Write command (refer to the following three figures). If the data
output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted
(HIGH) at least one clock prior to the Write/Block Write command to avoid internal bus contention.
Preliminary
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EtronTech
CLK
DQM
1Mega x 32 SGRAM
T0 T 1 T2 T3 T4 T5 T6 T7 T8
EM637327
COM MA ND
DQ's
: "H" or "L"
CLK
DQM
COM MA ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
: "H" or "L"
NO P
T0 T 1 T2 T3 T4 T5 T6 T7 T8
NOP NOP NOP READ A WRITE A NOP NOP NOP
READ A NOP NOP NOP NOP WRITE B NOP NOP
DOUT A
Read to Write Interval
BANKA
ACTIVATE
0
Must be Hi-Z before
the Write Command
(Burst Length ≥ 4, CAS# Latency = 3)
1 Clk Interval
Must be Hi-Z before
the Write Command
DIN A
DIN A
DINB
0
DIN A
0
0
DIN A
1
1
DINB
DIN A
DIN A
DINB
1
DIN A
2
DIN A
2
2
3
3
CLK
DQM
COM MA ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
Read to Write Interval
T0 T 1 T2 T3 T4 T5 T6 T7 T8
NOP
NOP
READ A
(Burst Length ≥ 4, CAS# Latency = 1, 2)
NOP WRIT E B N OP NOP NO P
DOUT A
NOP
0
Must be Hi-Z before
the Write Command
DIN B
DIN B
DIN B
0
0
DIN B
1
1
DIN B
DIN B
2
2
: "H" or "L"
Read to Write Interval
(Burst Length ≥ 4, CAS# Latency = 1, 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS# latency.
DIN B
DIN B
3
3
Preliminary
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EtronTech
CLK
1Mega x 32 SGRAM
T0 T 1 T2 T3 T4 T5 T6 T7 T8
EM637327
ADDRESS
COM M A ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
CAS# latency=3
t
, DQ's
CK3
Bank,
Col A
READ A
NOP
DOUT A
NOP Precharge
DOUT A
0
DOUT A
1
0
Read to Precharge
Bank(s)
NOP
DOUT A
DOUT A
DOUT A
DOUT A
2
DOUT A
DOUT A
2
1
1
0
(CAS# Latency = 1, 2, 3)
3
NOP
DOUT A
DOUT A
tRP
NOP
3
DOUT A
2
3
Bank,
Row
Activate
6 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A8 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after
the read operation. Once this command is given, any subsequent command cannot occur within a
time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in
this command and the auto precharge function is ignored.
7 Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A8 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least t
(min.) before the Write command is
RCD
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
T0 T 1 T2 T3 T4 T 5 T6 T 7 T8
NOP
CLK
COM MA ND
DQ0 - DQ3
command is a masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected
column location subject to the data stored in the Mask register. The overall mask consists of the
DQM inputs, which mask on a per-byte basis, and the Mask register, which masks also on a per-bit
basis. This is shown in the following block diagram.
Preliminary
NO P WRITE A
DIN A
0
The first data element and the write
are registered on the same clock edge.
NOP NOP
DIN A
Burst Write Operation
NOP
DIN A
1
DIN A
2
3
Extra data is masked.
NO P
don't care
(Burst Length = 4, CAS# Latency = 1, 2, 3)
NOP
NOP
NOP
Any Write performed to a row that was opened via an BankActivate & Masked Write Enable
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1Mega x 32 SGRAM
EM637327
DSF
BankA ctivate
command
D
CK
MR7
MR6
MR5
MR4
MR3
MR2
Q
DQM0
DRAM
CE LL
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
MR1
DQ0
MR0
0 = Masked
1 = Not Masked
Note:
Only the lower byte is shown. The operation is identical for other bytes.
Write Per Bit (I/O Mask) Block Diagram
A write burst without the auto precharge function may be interrupted by a subsequent
Write/Block Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst
length. An interrupt coming from Write/Block Write command can occur on any clock cycle
following the previous Write command (refer to the following figure).
T0 T 1 T2 T3 T4 T5 T6 T7 T8
CLK
COMM AND
DQ's
NO P WRITE A
1 Clk Interval
DIN A
WRIT E B NOP
DIN B
0
NOP
DIN B
0
NOP
DIN B
1
DIN B
2
3
NO P
NOP
NO P
Write Interrupted by a Write
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to
avoid data contention, input data must be removed from the DQs at least one clock cycle before the
Preliminary
(Burst Length = 4, CAS# Latency = 1, 2, 3)
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EtronTech
1Mega x 32 SGRAM
EM637327
first read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
T0 T 1 T2 T3 T4 T5 T6 T7 T8
CLK
COM MA ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
CAS# latency=3
t
, DQ's
CK3
NOP WRITE A
DIN A
0
DIN A
0
DIN A
0
Input data for the write is masked.
READ B N O P
don't care
don't care don't care
NOP
Write Interrupted by a Read
NOP
DOUT B0DOUT B
DOUT B
Input data must be removed from the DQ's at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DOUT B
1
DOUT B
0
DOUT B
(Burst Length = 4, CAS# Latency = 1, 2, 3)
NOP
DOUT B
2
DOUT B
1
DOUT B
0
NOP
3
DOUT B
2
1
DOUT B
3
2
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
T0 T 1 T2 T3 T4 T5 T6
CLK
NOP
DOUT B
3
DQM
t
RP
COMMAND
ADDRESS
DQ
WRITE
BANK
COL n
DIN
n
NOP
DIN
n + 1
BANK (S)
t
WR
NOPPrecharge NOP NOP Activate
ROW
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
When the Burst-Read-Single-Write mode is selected, the write burst length is 1 regardless of
the read burst length (refer to Figures 21 and 22 in Timing Waveforms).
8 Block Write command
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "H", BS = Bank, A8 = "L", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The block writes are non-burst accesses that write to eight column locations simultaneously. A
single data value, which was previously loaded in the Color register, is written to the block of eight
consecutive column locations addressed by inputs A3~A7. The information on the DQs which are
Preliminary
11
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Page 12
EtronTech
1Mega x 32 SGRAM
CR0
CR 1CR2
CR3
CR4
CR5
CR6
CR7
registered coincident with the Block Write command is used to mask specific column/byte
combinations within the block. The mapping of the DQ inputs to the column/byte combinations is
shown in following table.
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following figure. The DQM and Mask
register masking operates normally as for a Write command, with the exception that the mask
information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is
written only if a "0" is registered for the corresponding DQM input, a "1" is registered for the
corresponding DQ signal, and the corresponding bit in the Mask register is "1".
Block of Columns
(selected by A3-A7 registered
coincident with Block Write command)
Row in Bank
(selected by A0-A9,
and BS registered
coincident with BankActivate
Command)
EM637327
Write Command
BankActivate
command
Mask Register
(previously loaded
from corresponding
DQ inputs)
Column Mask
on the DQ
inputs
(registered
coincident
with Block
DSF
CK
MR0
MR 1
MR2
MR3
MR4
MR5
MR6
MR7
QD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM0
Note:
Preliminary
Only the lower byte is shown. The operation is identical for other bytes.
Block-Write Masking Block Diagram
August 1999
12
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EtronTech
1Mega x 32 SGRAM
EM637327
DQ Column Address DQ Planes DQ Column Address DQ Planes
Inputs A2 A1 A0 Controlled Inputs A2 A1 A0 Controlled
DQ0 0 0 0 0~7 DQ16 0 0 0 16~23
DQ1 0 0 1 0~7 DQ17 0 0 1 16~23
DQ2 0 1 0 0~7 DQ18 0 1 0 16~23
DQ3 0 1 1 0~7 DQ19 0 1 1 16~23
DQ4 1 0 0 0~7 DQ20 1 0 0 16~23
DQ5 1 0 1 0~7 DQ21 1 0 1 16~23
DQ6 1 1 0 0~7 DQ22 1 1 0 16~23
DQ7 1 1 1 0~7 DQ23 1 1 1 16~23
DQ8 0 0 0 8~15 DQ24 0 0 0 24~31
DQ9 0 0 1 8~15 DQ25 0 0 1 24~31
DQ10 0 1 0 8~15 DQ26 0 1 0 24~31
DQ11 0 1 1 8~15 DQ27 0 1 1 24~31
DQ12 1 0 0 8~15 DQ28 1 0 0 24~31
DQ13 1 0 1 8~15 DQ29 1 0 1 24~31
DQ14 1 1 0 8~15 DQ30 1 1 0 24~31
DQ15 1 1 1 8~15 DQ31 1 1 1 24~31
A block write access requires a time period of t
NOP cycles(m equals (t
- tCK)/tCK rounded up to the next whole number), after the Block Write
BWC
to execute, so in general, there should be
BWC
m
command. However, BankActivate or BankPrecharge commands to the other bank are allowed.
When following a Block Write with a BankPrecharge or PrechargeAll command to the same bank,
t
must be met.
BPL
9 Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", DSF = "L", BS = Bank, A8 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after
the write operation. Once this command is given, any subsequent command can not occur within a
time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is
performed in this command and the auto precharge function is ignored.
T0 T 1 T2 T3 T4 T 5 T6 T7 T8
CLK
COM MA ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
CAS# latency=3
t
, DQ's
CK3
Burst Write with Auto-Precharge
Bank A
Activate
tDAL= tWR + tRP
NO P NO P
NOP N O P
Write A
AutoPrecharge
DIN A
0
DIN A
0
DIN A
0
NOP
DIN A
DIN A
DIN A
NO P
DAL
t
1
*
tDAL
1
*
tDAL
1
*
Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
*
(Burst Length = 2, CAS# Latency = 1, 2, 3)
NOP
Preliminary
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EtronTech
1Mega x 32 SGRAM
EM637327
10 Block Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "H", BS = Bank, A8 = "H", A3-A7 = Column Address,
DQ0-DQ31 = Column Mask)
The Block Write and AutoPrecharge command performs the precharge operation automatically
after the block write operation. Once this command is given, any subsequent command can not
occur within a time delay of {t
+ tRP(min.)}.
BPL
11 Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", DSF = "L", BS, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SGRAM. The
Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst
Length in the Mode register to make SGRAM useful for a variety of different applications. The
default values of the Mode Register after power-up are undefined; therefore this command must be
issued at the power-up sequence. The state of pins A0~A8 and BS in the same cycle is the data
written to the mode register. One clock cycle is required to complete the write in the mode register
(refer to the following figure). The contents of the mode register can be changed using the same
command and the clock cycle requirements during operation as long as both banks are in the idle
state.
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CLK
t
CK2
CKE
Clock min.
CS#
RAS#
CAS#
WE#
DSF
BS
A 9
A0-A8
DQM
DQ
Hi-Z
Address Key
RP
t
The mode register is divided into various fields depending on functionality.
Preliminary
PrechargeAll
Mode Register
Set Command
Mode Register Set Cycle
14
Any
Command
(CAS# Latency = 1, 2, 3)
August 1999
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EtronTech
1Mega x 32 SGRAM
• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the
Burst Length to be 1, 2, 4, 8, or full page.
A2 A1 A0 Burst Length
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page
• Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, Interleave Mode or Sequential Mode.
Sequential Mode supports burst length of 1, 2, 4, 8, or full page, but Interleave Mode only
supports burst length of 4 and 8.
A3 Addressing Mode
0 Sequential
1 Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column
address which is input to the device. The internal column address is varied by the Burst
Length as shown in the following table. When the value of column address, (n + m), in
the table is larger than 255, only the least significant 8 bits are effective.
EM637327
Data n 0 1 2 3 4 5 6 7 - 255 256 257 -
Column Address
Burst Length 4 words:
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting
the address bits in the sequence shown in the following table.
Data n Column Address Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 -
2 words:
8 words:
Full Page: Column address is repeated until terminated.
Preliminary
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EtronTech
1Mega x 32 SGRAM
• CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS# Latency depends on the frequency
of CLK. The minimum whole value satisfying the following formula must be programmed
into this field. t
A6 A5 A4 CAS# Latency
0 0 0 Reserved
0 0 1 1 clock
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved
• Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal
operation.
A8 A7 Test Mode
0 0 normal mode
0 1 Vendor Use Only
1 X Vendor Use Only
(min) ≤ CAS# Latency X t
CAC
CK
EM637327
• Single Write Mode (A9)
This bit is used to select the write mode. When the A9 bit is "0", the Burst-Read-Burst-
Write mode is selected. When the A9 bit is "1", the Burst-Read-Single-Write mode is
selected.
A9 Single Write Mode
0 Burst-Read-Burst-Write
1 Burst-Read-Single-Write
12 Special Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", DSF = "H", BS, A0-A9 = Register Data)
The special mode register is used to load the Color and Mask registers, which are used in Block
Write and masked Write cycles. The control information being written to the Special Mode register
is applied to the address inputs and the data to be written to either the Color register or the Mask
register is applied to the DQs. When A6 is "HIGH" during a Special Mode Register Set cycle, the
Color register will be loaded with the data on the DQs. Similarly, when A5 is "HIGH" during a
Special Mode Register Set cycle, the Mask register will be loaded with the data on the DQs.
A6=A5=1 in the Special Mode Register Set cycle is illegal.
Functions BS A9 ~ A7 A6 A5 A4 ~ A0
Leave Unchanged X X 0 0 X
Load Mask Register X X 0 1 X
Load Color Register X X 1 0 X
Illegal X X 1 1 X
One clock cycle is required to complete the write in the Special Mode register. This command
can be issued during the active state. As in a write operation, this command accepts the data
needed through DQ pins. Therefore, it should be attended not to induce bus contention.
13 No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SGRAM which is selected (CS#
is Low). This prevents unwanted commands from being registered during idle or wait states.
Preliminary
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EtronTech
1Mega x 32 SGRAM
14 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L", DSF = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS# latency (refer to the following figure). The
termination of a write burst is shown in the following figure.
T0 T 1 T2 T3 T4 T5 T6 T7 T8
CLK
EM637327
COM MA ND
CAS# latency=1
t
, DQ's
CK1
CAS# latency=2
t
, DQ's
CK2
CAS# latency=3
t
, DQ's
CK3
READ A
NOP
DOUT A0DOUT A
NOP Burst Stop
DOUT A0DOUT A
1
Termination of a Burst Read Operation
T0 T 1 T2 T3 T4 T 5 T6 T7 T8
CLK
COM MA ND
CAS# latency=1, 2, 3
DQ's
NOP WRITE A
DIN A
NOP Burst Stop
DIN A
0
1
Termination of a Burst Write Operation
NOP
DOUT A2DOUT A
1
DOUT A0DOUT A
3
DOUT A2DOUT A
1
(Burst Length > 4, CAS# Latency = 1, 2, 3)
NOP
DIN A
don't care
2
Input data for the Write is masked.
(Burst Length = X, CAS# Latency = 1, 2, 3)
NO P
The burst ends after a delay equal to the CAS# latency.
DOUT A2DOUT A
NOP
NOP
3
NOP
NOP
3
NOP
NOP
NO P
15 Device Deselect command
(CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
16 AutoRefresh command (refer to Figures 3 & 4 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "H", BS, A0-A9 = Don't care)
The AutoRefresh command is used during normal operation of the SGRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 2048 times within 32ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, both banks need
to be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
Preliminary
17
August 1999
Page 18
EtronTech
1Mega x 32 SGRAM
17 SelfRefresh Entry command (refer to Figure 5 in Timing Waveforms)
(RAS# = "L", CAS# = "L", WE# = "H", DSF = "L", CKE = "L", BS, A0-A9 = Don't care)
The SelfRefresh is another refresh mode available in the SGRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SGRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SGRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited
by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
18 SelfRefresh Exit command (refer to Figure 5 in Timing Waveforms)
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered,
NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 2048 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
19 Clock Suspend Mode Entry / PowerDown Mode Entry command (refer to Figures 6, 7, and 8 in
Timing Waveforms)
(CKE = "L")
When the SGRAM is operating the burst cycle, the internal CLK is suspended(masked) from
the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when both banks are in the idle state, this
command performs entry into the PowerDown mode. All input and output buffers (except the CKE
buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or
PowerDown state longer than the refresh period (32ms) since the command does not perform any
refresh operations.
EM637327
20 Clock Suspend Mode Exit / PowerDown Mode Exit command (refer to Figures 6, 7, and 8 in Timing
Waveforms)
(CKE= "H")
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated
from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is
in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the
active state. t
subsequent commands can be issued after one clock cycle from the end of this command.
21 Data Write / Output Enable, Data Mask / Output Disable command
(DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of
the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is
also used for device selection, byte selection and bus control in a memory system. DQM0 controls
DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and DQM3 controls
DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a
state of write-per-bit masking or pixel masking. Each DQM0-3 corresponds to DQ0-7, DQ8-15,
DQ16-23, and DQ24-31.
(min.) is required when the device exits from the PowerDown mode. Any
PDE
Preliminary
18
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Page 19
EtronTech
1Mega x 32 SGRAM
EM637327
Absolute Maximum Rating
Symbol Item Rating Unit Note
VIN, V
VDD, V
T
OPR
T
STG
T
SOLDER
P
I
OUT
OUT
DDQ
D
Input, Output Voltage - 0.3~VDD + 0.3 V 1
Power Supply Voltage - 0.3~4.6 V 1
Operating Temperature 0~70 °C 1
Storage Temperature - 55~150 °C 1
Soldering Temperature (10s) 260 °C 1
Power Dissipation 1 W 1
Short Circuit Output Current 50 mA 1
Recommended D.C. Operating Conditions (Ta = 0~70°C)
Symbol Parameter Min. Typ. Max. Unit Note
V
V
V
V
DD
DDQ
IH
IL
Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2
Power Supply Voltage 3.0 3.3 3.6 V 2
LVTTL Input High Voltage 2.0
LVTTL Input Low Voltage - 0.3
¡Ð
¡Ð
VDD + 0.3 V 2
0.8 V 2
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol Parameter Min. Max. Unit
C
I
C
I/O
Note: These parameters are periodically sampled and are not 100% tested.
Input Capacitance
Input/Output Capacitance
¡Ð
¡Ð
5 pF
7 pF
Preliminary
19
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Page 20
EtronTech
1Mega x 32 SGRAM
EM637327
Recommended D.C. Operating Conditions (VDD = 3.3V±0.3V, Ta = 0~70°C)
- 5/6/7/8
Description/Test condition Symbol
Operating Current
t
≥ tRC(min), Outputs Open
RC
Address changed once during t
CK
(min).
1 bank operation
Burst Length = 2
Precharge Standby Current in non-power down mode
tCK = tCK(min), CS# ≥ VIH, CKE ≥ VIH(min)
Input signals are changed once during 30ns.
Precharge Standby Current in non-power down mode
tCK = ∞, CKE ≥ VIH(min), Input signals are stable.
Precharge Standby Current in power down mode
tCK = tCK(min), CKE ≤ VIL(max)
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = tCK(min)
Active Standby Current in non-power down mode
CKE ≥ VIH(min), tCK = tCK(min)
Operating Current (Burst mode)
tCK=tCK(min), Outputs Open, Multi-bank interleave,gapless data
Refresh Current
tRC ≥ tRC(min)
Self Refresh Current
CKE ≤ 0.2V
Operating Current (Block Write)
t
= tCK(min), Outputs Open, t
CK
BWC
= t
BWC
(min).
I
DD1
I
DD2N
I
DD2NS
I
DD2P
I
DD2PS
I
DD3P
I
DD3N
I
DD4
I
DD5
I
DD6
I
DD7
Min Max.
200/180/160/150 3
30
15
2 3
2 mA
3 3
50
290/260/230/200 3, 4
200/180/160/150 3
2
230/200/170/150
Unit
Note
3
Parameter Description Min. Max. Unit Note
I
IL
Input Leakage Current
- 5 5
µA
( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )
I
OL
V
OH
V
OL
Output Leakage Current
Output disable, 0V ≤ V
OUT
≤ V
LVTTL Output "H" Level Voltage
( I
= -2mA )
OUT
LVTTL Output "L" Level Voltage
( I
= 2mA )
OUT
DDQ
- 5 5
µA
)
2.4
¡Ð
¡Ð
0.4 V
V
Preliminary
20
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Page 21
EtronTech
1Mega x 32 SGRAM
EM637327
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
- 5/6/7/8
Symbol A.C. Parameter
t
RC
t
RCD
t
RP
Row cycle time (same bank)
RAS# to CAS# delay (same bank)
Precharge to refresh/row activate command
(same bank)
t
RRD
Row activate to row activate delay
(different banks)
t
RAS
t
WR
t
CK1
t
CK2
t
CK3
t
CH
t
CL
t
AC1
t
AC2
t
AC3
t
CCD
t
OH
t
LZ
t
HZ
t
IS
t
IH
t
SRX
t
PDE
t
RSC
t
BWC
t
BPL
t
REF
Row activate to precharge time (same bank)
Write recovery time
Clock cycle time CL* = 2
Clock high time
Clock low time
Access time from CLK CL* = 1
(positive edge) CL* = 2
CAS# to CAS# Delay time
Data output hold time
Data output low impedance
Data output high impedance
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
Minimum CKE "High" for SelfRefresh exit
PowerDown Exit set-up time
(Special) Mode Register Set Cycle time
Block Write Cycle time
Block Write to Precharge command period
Refresh time
CL* = 1
CL* = 3
CL* = 3
Min. Max. Unit Note
55/60/63/72 9
15/18/21/24 9
15/18/21/24 9
10/12/14/16 9
25/30/35/40 100,000 9
5/6/7/8
ns
-/18/21/24
-/9/10/12
5/6/7/8
2/2/2.5/3
2/2/2.5/3
-/16/19/22
-/7/8/10
4.5/5.5/5.5/6
1 Cycle
2 10
1/1/1/2
3/4/5/6 8
1.5 11
1 11
5/6/7/8
ns
3/4/5/6 11
5/6/7/8 9
10/12/14/16
10/12/14/16
32 ms
10
11
11
11
* CL is CAS# Latency.
Preliminary
21
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EtronTech
1Mega x 32 SGRAM
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 10.
6. A.C. Test Conditions
EM637327
LVTTL Interface
Reference Level of Output Signals 1.4V / 1.4V
Output Load Reference to the Under Output Load (B)
Input Signal Levels 2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals 1ns
Reference Level of Input Signals 1.4V
3.3V
1.2kΩ
50Ω
Output
30pF
LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference
levels.
9. These parameters account for the number of clock cycle and depend on the operating frequency of the
clock as follows:
the number of clock cycles = specified value of timing/Clock cycle time
(count fractions as a whole number)
10.If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
11.Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e.,
[ ( tR + tF ) / 2 -1] ns should be added to the parameter.
870Ω
Output
Z0=
1.4V
50Ω
30pF
Preliminary
22
August 1999
Page 23
EtronTech
12. Power up Sequence
Power up must be performed in the following sequence.
1Mega x 32 SGRAM
EM637327
1) Power must be applied to VDD and V
and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200µseconds minimum is required. Then, it is recommended that DQM
is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device.
(simultaneously) when all input signals are held "NOP" state
DDQ
Preliminary
23
August 1999
Page 24
EtronTech
Timing Waveforms
Bank A
Ban
k B
1Mega x 32 SGRAM
EM637327
Figure 1. AC Parameters for Write Timing
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
tCH
tCL
tIS
tIS
tIH
tCK2
Begin AutoPrecharge
Bank A
(Burst Length=4, CAS# Latency=2)
Begin AutoPrecharge
Bank B
tIS
A 8
A0-A7
DQM
DQ
Hi-Z
tIS
RAx
RBx
Activate
Command
Bank A
t
IH
RBx
CAx
t
RCD
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Write with
AutoPrecharge
Command
RBx
tRC
Activate
Command
Bank B
CBx RAy
Write with
AutoPrecharge
Command
t
DAL
RAy
Activate
Command
Bank A
tIS
CAy
Write
Command
Bank A
tIH
tWR
Precharge
Command
Bank A
t
RP
RAz
RAz
Activate
Command
Bank A
t
RRD
RBy
RBy
Activate
Command
Bank B
Preliminary
24
August 1999
Page 25
EtronTech
1Mega x 32 SGRAM
Ban
k B
EM637327
Figure 2. AC Parameters for Read Timing
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T13
CLK
tCK2
IS
t
IH
t
IH
t
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
tCH
CL
t
IS
t
(Burst Length=2, CAS# Latency=2)
Begin AutoPrecharge
Bank B
IH
t
A 8
A0-A7
DQM
DQ
Hi -Z
IS
t
Activate
Command
RAx
RAx
Bank A
tRCD
CAx RBx
RRD
t
tAC2
t
Read
Command
Bank A
LZ
RBx
AC2
t
Ax0
Activate
Command
Bank B
tRAS
tOH
CBx
tRC
HZ
t
Ax1
Read with
Auto Precharge
Command
Bx0 Bx1
Precharge
Command
Bank A
tRP
HZ
t
RAy
RAy
Activate
Command
Bank A
Preliminary
25
August 1999
Page 26
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 3. Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CK2
t
CKE
CS#
RAS#
CA S#
WE#
DSF
(Burst Length=4, CAS# Latency=2)
BS
A 8
A0~A7
DQM
DQ
PrechargeAll
Command
tRP
AutoRefresh
Command
RAx
RAx CAx
RC
t
AutoRefresh
Command
RC
t
Activate
Command
Bank A
Read
Command
Ax0
Ax1
Ax2
Ax3
Preliminary
26
August 1999
Page 27
EtronTech
1Mega x 32 SGRAM
sta
ble fo
r 200 µ
s
Figure 4. Power on Sequene and Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T1 0 T 11 T12 T13 T14 T15 T16 T17 T18 T1 9 T20 T21 T22
CLK
tCK2
EM637327
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
A 8
A0-A7
High level
is reauired
Minimum of 2 Refresh Cycles are required
Address Key
DQM
DQ
Hi-Z
Inputs must be
PrechargeALL
Command
tRP
Mode Register
Set Command
1st AutoRefresh
Command
2nd Auto Refresh
Command
tRC
Any
Command
Preliminary
27
August 1999
Page 28
EtronTech
Figure 5. Self Refresh Entry & Exit Cycle
T6
Sel
f Refr
esh En
ter
Self
Refresh
Exit
Aut
oRef
resh
1Mega x 32 SGRAM
EM637327
Clock
CKE
CS#
RAS#
CAS#
BS
A0-A 8
T0 T1 T2 T3 T4 T5
*Note 2
*Note 1
tIS
*Note 8
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
*Note 4
*Note 3
tRC(min) *Note 7
tSRX
*Note 5
*Note 6
tPDE
*Note 8
WE#
DSF
DQ M
DQ
Hi-Z
Hi-Z
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
Once the device enters SelfRefresh mode, minimum t
is required before exit from SelfRefresh.
RAS
Note: To Exit SelfRefresh Mode
4. System clock restart and be stable before returning CKE high.
5. Enable CKE and CKE should be set high for minimum time of t
SRX
.
6. CS# starts from high.
7. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
8. 1024 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Preliminary
28
August 1999
Page 29
EtronTech
1Mega x 32 SGRAM
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T1 0 T 11 T12 T13 T14 T15 T16 T17 T18 T1 9 T20 T21 T22
tCK1
EM637327
BS
A 8
A0-A7
DQM
Hi-Z
DQ
Note:
CKE to CLK disable/enable = 1 clock
RAx
RAx CAx
Activate
Command
Bank A
Read
Command
Bank A
Ax0 Ax1
Clock Suspend
1 Cycle
Ax2
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
t
HZ
Preliminary
29
August 1999
Page 30
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T1 8 T1 9 T20 T21 T22
t
CK2
EM637327
BS
A 8
A0-A7
DQM
Hi-Z
DQ
Note:
CKE to CLK disable/enable = 1 clock
RAx
RAx
Activate
Command
CAx
Read
Command
Ax0 Ax1
Clock Suspend
1 Cycle
Ax2
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
tHZ
Preliminary
30
August 1999
Page 31
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Figure 6.3. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
EM637327
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
A 8
T0 T 1 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T1 9 T20 T21 T22
RAx
t
T 2
CK3
A0-A7
DQM
Hi-Z
DQ
Note:
CKE to CLK disable/enable = 1 clock
RAx
Activate
Command
CAx
Read
Command
Ax0 Ax1 Ax2
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Ax3
Clock Suspend
3 Cycles
tHZ
Preliminary
31
August 1999
Page 32
EtronTech
1Mega x 32 SGRAM
Figure 7.1. Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T1 0 T 11 T12 T13 T14 T15 T16 T17 T18 T1 9 T20 T21 T22
CLK
CK1
t
CKE
CS#
RAS#
CAS#
WE#
DSF
EM637327
BS
A 8
A0-A7
DQM
DQ
Hi-Z
Note:
CKE to CLK disable/enable = 1 clock
RAx
RAx CAx
Activate
Command
Bank A
DAx0
Clock Suspend
Write
Command
Bank A
1 Cycle
DAx1
Clock Suspend
2 Cycles
DAx2 DAx3
Clock Suspend
3 Cycles
Preliminary
32
August 1999
Page 33
EtronTech
1Mega x 32 SGRAM
Bank A
Figure 7.2. Clock Suspension During Burst Write (Using CKE)
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
t
CK2
EM637327
T22
BS
A 8
A0-A7
DQM
Hi-Z
DQ
Note:
CKE to CLK disable/enable = 1 clock
RAx
RAx CAx
Activate
Command
Bank A
DAx0
Clock Suspend
Write
Command
1 Cycle
DAx1
Clock Suspend
2 Cycles
DAx2 DAx3
Clock Suspend
3 Cycles
Preliminary
33
August 1999
Page 34
EtronTech
1Mega x 32 SGRAM
Bank A
Figure 7.3. Clock Suspension During Burst Write (Using CKE)
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
tCK3
EM637327
BS
A 8
A0-A7
DQM
DQ
Note:
CKE to CLK disable/enable = 1 clock
Hi-Z
RAx
RAx
Activate
Command
Bank A
CAx
DAx0
Clock Suspend
Write
Command
1 Cycle
DAx1
Clock Suspend
2 Cycles
DAx2 DAx3
Clock Suspend
3 Cycles
Preliminary
34
August 1999
Page 35
EtronTech
1Mega x 32 SGRAM
Mode
Entry
EM637327
Figure 8. Power Down Mode and Clock Mask
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S #
WE#
BS
IS
t
(Burst Lenght=4, CAS# Latency=2)
tPDE
Valid
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
Activate
Command
Bank A
Power Down
Mode Entry
ACTIVE
STANDBY
Command
Bank A
Power Down
Mode Exit
CAx
Read
Ax0
Clock Mask
Start
Ax1
Ax2
Clock Mask
End
HZ
t
Ax3
Precharge
Command
Bank A
Power Down
PRECHARGE
STANDBY
Power Down
Mode Exit
Command
Any
Preliminary
35
August 1999
Page 36
EtronTech
1Mega x 32 SGRAM
Bank A
Figure 9.1. Random Column Read (Page within same Bank)
CLK
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RAw
RAw
Activate
Command
Bank A
Command
CAw
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1
Command
Read
Bank A
CAx
Read
CAy
Read
Command
Bank A
Ay0
Ay1 Ay2 Ay3
Precharge
Command
Bank A
RAz
RAz
Activate
Command
Bank A
CAz
Read
Command
Bank A
Az0
Az1 Az2 Az3
Preliminary
36
August 1999
Page 37
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Figure 9.2. Random Column Read (Page within same Bank)
CLK
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RAw
RAw
Activate
Command
CAw CAx
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1
Read
Command
Read
Command
CAy
Read
Command
Ay0
Ay1 Ay2 Ay3
Precharge
Command
RAz
RAz
Activate
Command
CAz
Read
Command
Az0
Az1 Az2 Az3
Preliminary
37
August 1999
Page 38
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
Figure 9.3. Random Column Read (Page within same Bank)
CLK
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RAw
RAw
Activate
Command
CAw
Read
Command
CAx CAy
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1
Read
Command
Read
Command
Ay0
Ay1 Ay2 Ay3
Precharge
Command
RAz
RAz
Activate
Command
CAz
Read
Command
Az0
Preliminary
38
August 1999
Page 39
EtronTech
1Mega x 32 SGRAM
Ban
k B
Ban
k B
Figure 10.1. Random Column Write (Page within same Bank)
CLK
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi -Z
RBw
CBw
RBw
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1
Activate
Command
Bank A
Write
Command
CBx
Write
Command
Bank A
CBy
DBy0
Write
Command
Bank B
DBy1 DBy2 DBy3
Precharge
Command
Bank B
RBz
RBz
Activate
Command
CBz
DBz0
Write
Command
Bank B
DBz1 DBz2 DBz3
Preliminary
39
August 1999
Page 40
EtronTech
1Mega x 32 SGRAM
Bank A
Ban
k B
Ban
k B
Ban
k B
Ban
k B
Ban
k B
Ban
k B
Figure 10.2. Random Column Write (Page within same Bank)
CLK
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RBw
RBw
Activate
Command
CBw CBx
DBw0 DBw1DBw2 DBw3 DBx0 DBx1
Write
Command
Write
Command
CBy
DBy0
Write
Command
DBy1 DBy2 DBy3
Precharge
Command
RBz
RBz
Activate
Command
CBz
DBz0
Write
Command
DBz1
DBz2 DBz3
Preliminary
40
August 1999
Page 41
EtronTech
1Mega x 32 SGRAM
Bank A
Ban
k B
Ban
k B
Ban
k B
Ban
k B
Ban
k B
Ban
k B
Figure 10.3. Random Column Write (Page within same Bank)
CLK
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
EM637327
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RBw
RBw
Activate
Command
CBw
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1
Write
Command
CBx
Write
Command
CBy
DBy0
Write
Command
DBy1 DBy2 DBy3
Precharge
Command
RBz
RBz
Activate
Command
CBz
DBz0
Write
Command
DBz1
DBz2
Preliminary
41
August 1999
Page 42
EtronTech
1Mega x 32 SGRAM
Bank A
Figure 11.1. Random Row Read (Interleaving Banks)
CLK
CKE
High
CS#
RAS#
CAS#
WE#
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RBx
RBx
tRCD
Activate
Command
Bank B
CBx
t
AC1
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5
Read
Command
Bank B
RAx
Bx6
Activate
Command
Bank A
CAxRAx
Bx7
Precharge
Command
Read
Command
tRP
Ax0 Ax1
Bank B
Command
RBy
RBy
Ax2 Ax3 Ax4 Ax5 Ax6 Ax7
Activate
Bank B
CBy
Read
Command
Bank B
By0 By1 By2
Precharge
Command
Bank A
Preliminary
42
August 1999
Page 43
EtronTech
1Mega x 32 SGRAM
Bank A
Figure 11.2. Random Row Read (Interleaving Banks)
CLK
High
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RBx
RBx
Activate
Command
Bank B
CBx
tRCD tAC2
Read
Command
Bank B
RAx
RAx
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7
Activate
Command
Bank A
CAx
Read
Command
Precharge
Command
Bank B
tRP
Ax0
RBy
RBy
Ax1
Activate
Command
Bank B
Ax2 Ax3
Ax4 Ax5
CBy
Ax6 Ax7
Read
Command
Bank B
By0 By1
Preliminary
43
August 1999
Page 44
EtronTech
1Mega x 32 SGRAM
Ban
k B
Figure 11.3. Random Row Read (Interleaving Banks)
CLK
High
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
EM637327
DSF
BS
A 8
A0~A7
DQM
DQ
RBx
t
RCD
CBx
Read
Command
t
AC3
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5
RBx RBy
Hi-Z
Activate
Command
Bank B
RAx
RAx
Activate
Command
Bank A
CAx
Read
Command
Bank A
Bx6
Bx7 Ax0 Ax1
Precharge
Command
Bank B
RBy
t
RP
Ax2 Ax3 Ax4 Ax5 Ax6
Activate
Command
Bank B
CBy
Read
Command
Bank B
Ax7 By0
Precharge
Command
Bank A
Preliminary
44
August 1999
Page 45
EtronTech
1Mega x 32 SGRAM
Bank A
Figure 12.1. Random Row Write (Interleaving Banks)
CLK
High
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
EM637327
BS
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
CAx
tRCD
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5
Activate
Command
Bank A
Write
Command
RBx
RBx
DAx6
DAx7 DBx0 DBx1
Activate
Command
Bank B
CBx
Write
Command
Bank B
RAy
RAy
tRP tWR
DBx2 DBx3 DBx4 DBx5 DBx6
Precharge
Command
Bank A
Activate
Command
Bank A
DBx7
Precharge
Command
Bank B
CAy
DAy0 DAy1 DAy2
Write
Command
Bank A
DAy3
Preliminary
45
August 1999
Page 46
EtronTech
1Mega x 32 SGRAM
Bank A
Ban
k B
Figure 12.2. Random Row Write (Interleaving Banks)
CLK
High
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
EM637327
BS
A 8
A0~A7
DQM
Hi-Z
DQ
Activate
Command
Bank A
*
tWR > tWR(min.)
RAx
RAx
RBx
CAx CBx
t
RCD
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5
Write
Command
Bank A
RBx
DAx6
Activate
Command
Bank B
t
WR*
DAx7 DBx0 DBx1
Write
Command
Bank B
Precharge
Command
RAy
RAy
t
RP
DBx2 DBx3 DBx4 DBx5 DBx6
Activate
Command
Bank A
CAy
t
WR*
DBx7
DAy0 DAy1DAy2 DAy4
Write
Command
Bank A
Precharge
Command
DAy3
Preliminary
46
August 1999
Page 47
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Figure 12.3. Random Row Write (Interleaving Banks)
CLK
High
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
EM637327
BS
A 8
A0~A7
RAx
RAx RAy
DQM
Hi-Z
DQ
Activate
Command
*
tWR > tWR(min.)
RBx
CAx CBx
t
RCD
DAx0 DAx1
Write
Command
Bank A
DAx2 DAx3 DAx4 DAx5
RBx
Activate
Command
Bank B
DAx6
DAx7 DBx0 DBx1
t
WR* t
Write
Command
Bank B
RP t
DBx2 DBx3 DBx4
Precharge
Command
Bank A
RAy
DBx5 DBx6
Activate
Command
Bank A
CAy
DBx7
DAy0 DAy1 DAy2
Write
Command
WR*
Precharge
Command
Bank B
DAy3
Preliminary
47
August 1999
Page 48
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 13.1. Read and Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx CAx
Activate
Command
Bank A
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1
Read
Command
CAy CAz
DAy3 Az0 Az1
Write
The Write Data
Command
is Masked with a
Bank A
Zero Clock
Latency
Read
Command
Bank A
Az3
The Read Data
is Masked with a
Two Clock
Latency
Precharge
Command
Bank B
Preliminary
48
August 1999
Page 49
EtronTech
1Mega x 32 SGRAM
La
ten
cy
La
ten
cy
EM637327
Figure 13.2. Read and Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx CAx
Activate
Command
Bank A
Read
Command
Bank A
CAy
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1
The Write Data
Write
is Masked with a
Command
Bank A
Zero Clock
CAz
Read
Command
Bank A
Az3DAy3 Az0 Az1
The Read Data
is Masked with a
Two Clock
Preliminary
49
August 1999
Page 50
EtronTech
1Mega x 32 SGRAM
La
ten
cy
La
ten
cy
EM637327
Figure 13.3. Read and Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=3)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
Activate
Command
Bank A
CAx
Read
Command
Bank A
CAy CAz
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1
Write
Bank A
is Masked with a
Command
The Write Data
Zero Clock
Read
Command
Bank A
The Read Data
is Masked with a
Two Clock
Az3DAy3 Az0 Az1
Preliminary
50
August 1999
Page 51
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 14.1. Interleaving Column Read Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
CS#
RAS#
CA S #
WE#
DSF
BS
(Burst Length=4, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
t
RCD t
Activate
Command
Bank A
Command
RBw
RBw
Activate
Command
Bank B
Command
CBw
Read
Bank B
CBx
Bw0 Bw1 Bx0 Bx1 By1 Ay0
Read
Command
Bank B
RAx
AC1
Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1
Read
CBy
Read
Command
Bank B
CAy
Read
Command
Bank A
CBz
Read
Command
Bank B
Bz0
Precharge
Command
Bank A
Bz2 Bz3
Precharge
Command
Bank B
Preliminary
51
August 1999
Page 52
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 14.2. Interleaving Column Read Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
Activate
Command
Bank A
CAy
tRCD tAC2
Read
Command
Bank A
RAx
RAx
Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1
Activate
Command
Bank B
CBw
Read
Command
Bank B
CBx CBy CAy CBz
Bw0 Bw1 Bx0 Bx1 By1 Ay0
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bz0
Bz2 Bz3
Precharge
Command
Bank B
Preliminary
52
August 1999
Page 53
EtronTech
1Mega x 32 SGRAM
Ban
k B
EM637327
Figure 14.3. Interleaved Column Read Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=3)
A 8
A0~A7
DQM
DQ
Hi -Z
RAx
RAx
Activate
Command
Bank A
tRCD
CAx RBx
Read
Command
Bank A
RBx
tAC3
Activate
Command
CBx
Ax0 Ax1 Ax2 Ax3 Bz0 Ay1 Ay3
Read
Command
Bank B
CBy
Read
Command
Bank B
CBz
Bx0 Bx1 By0 By1 Bz1 Ay0
Read
Command
Bank B
CAy
Read
Command
Bank A
Prechaerge
Command
Bank B
Precharge
Command
Bank A
Ay2
Preliminary
53
August 1999
Page 54
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 15.1. Interleaved Column Write Cycle
CLK
CKE
CS#
RAS#
CA S #
WE#
DSF
BS
T0 T 1 T2 T3 T4 T5 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
T6
(Burst Length=4, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
t
RCD
Activate
Command
Bank A
Command
RBw
CAx RBw
t
RRD
DAx0
DAx1 DAx2 DAx3 DBy0 DAy1 DBz0
Activate
Command
Bank B
Write
CBw
DBw0 DBw1 DBx0 DBx1 DBy1 DAy0
Write
Command
Bank B
CBx
Write
Command
Bank B
CBy
Write
Command
Bank B
Command
CAy
Write
Bank A
tRP
Precharge
Command
Bank A
CBz
Write
Command
Bank B
DBz1
DBz2
DBz3
tWRt
Precharge
Command
Bank B
RP
Preliminary
54
August 1999
Page 55
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 15.2. Interleaved Column Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CA S #
WE#
DSF
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
Activate
Command
Bank A
t
RCD
RBw
CAx
t
RRD
DAx0
Write
Command
Bank A
RBw
DAx1 DAx2 DAx3 DBy0 DAy1 DBz0
Activate
Command
Bank B
CBw CBx CBy
DBw0 DBw1 DBx0 DBx1 DBy1 DAy0
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
CAy
Write
Command
Bank A
CBz
Write
Command
Bank B
Precharge
Command
DBz1
t
RP
DBz2
DBz3
t
WR
Precharge
Command
Bank B
t
RP
Preliminary
55
August 1999
Page 56
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 15.3. Interleaved Column Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=3)
A 8
A0~A7
DQM
DQ
Hi-Z
RAx
RAx
Activate
Command
Bank A
CAx RBw
tRCD
t
RRD > tRRD(min)
DAx0
Write
Command
Bank A
RBw
CBw CBx CBy
DAx1 DAx2 DAx3 DBy0 DAy1 DBz0
Activate
Command
Bank B
DBw0 DBw1 DBx0 DBx1 DBy1 DAy0
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
CAy
Write
Command
Bank A
Command
CBz
tWR
Write
Bank B
DBz1
Precharge
Command
tRP
DBz2
DBz3
tWR(min)
Precharge
Command
Bank B
Preliminary
56
August 1999
Page 57
EtronTech
1Mega x 32 SGRAM
Bank A
Ban
k B
EM637327
Figure 16.1. Auto Precharge after Read Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
CAx
Read
Command
Bank A
RBx
CBx
RBx
Ax1 Ax2 Ax3 Ay0 Ay3 By0
Ax0
Activate
Command
Bank B
Auto Precharge
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
Read with
Command
Bank B
Auto Precharge
RBy RBz
RBy CBy
CAy
Activate
Command
Bank B
Read with
Command
Read with
Auto Precharge
Command
Bank B
By1
By2
By3
RBz
Activate
Command
Bank B
Read with
Auto Precharge
Command
CBz
Bz0 Bz1
Bz2
Bz3
Preliminary
57
August 1999
Page 58
EtronTech
1Mega x 32 SGRAM
Ban
k B
Bank A
Ban
k B
Bank A
EM637327
Figure 16.2. Auto Precharge after Read Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
DSF
WE#
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
Hi-Z
Activate
Command
Bank A
RAx
RAx
CAx
Read
Command
Bank A
RBx
RBx
Ax0
Activate
Command
Bank B
CBx
Ax1 Ax2 Ax3 Ay0 Ay3 By0
Read with
Auto Precharge
Command
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
RAy CBy
Read with
Auto Precharge
Command
RBy
RBy
Activate
Command
Bank B
Read with
Auto Precharge
Command
RAz
RAz
Activate
Command
Bank A
CAz
By1
By2
Read with
Auto Precharge
Command
By3
Az0 Az1
Az2
Preliminary
58
August 1999
Page 59
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 16.3. Auto Precharge after Read Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=3)
A 8
A0~A7
DQM
DQ
Hi-Z
Activate
Command
Bank A
RAx
RAx
CAx
Read
Command
Bank A
RBx
RBx
Activate
Command
Bank B
RBy
CBx
Ax0
Ax1 Ax2 Ax3 Ay0 Ay3 By0
Read with
Auto Precharge
Command
Bank B
CAy
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
Read with
Auto Precharge
Command
RBy
Activate
Command
Bank B
CBy
Read with
Auto Precharge
Command
Bank B
By1
By2
By3
Preliminary
59
August 1999
Page 60
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 17.1. Auto Precharge after Write Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=1)
T 11
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
RBx
CAx
DAx0
Write
Command
Bank A
RBx
DAx1 DAx2 DAx3 DAy0 DAy3 DBy0
Activate
Command
Bank B
CBx
DBx0 DBx1 DBx2 DBx3 DAy1 DAy2
Write with
Auto Precharge
Command
Bank B
CAy
Write with
Auto Precharge
Command
Bank A
RBy
RBy
Activate
Command
Bank B
CBy
DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
RAz
RAz
Activate
Command
Bank A
Write with
Auto Precharge
Command
CAz
DAz0 DAz0
DAz0 DAz0
Preliminary
60
August 1999
Page 61
EtronTech
1Mega x 32 SGRAM
Ban
k B
Bank A
Ban
k B
Bank A
EM637327
Figure 17.2. Auto Precharge after Write Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
Hi-Z
Activate
Command
Bank A
RAx
RAx
RBx
CAx
DAx0
Write
Command
Bank A
RBx
DAx1 DAx2 DAx3 DAy0 DAy3 DBy0
Activate
Command
Bank B
CBx
DBx0 DBx1 DBx2 DBx3 DAy1 DAy2
Write with
Auto Precharge
Command
CAy
Write with
Auto Precharge
Command
RBy
RBy
Activate
Command
Bank B
CBy
DBy1
Write with
Auto Precharge
Command
RAz
RAz
DBy2 DBy3
Activate
Command
Bank A
CAz
DAz0 DAz1
Write with
Auto Precharge
Command
DAz2 DAz3
Preliminary
61
August 1999
Page 62
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 17.3. Auto Precharge after Write Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
High
CKE
CS#
RAS#
CA S #
WE#
DSF
BS
(Burst Length=4, CAS# Latency=3)
`
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
RBx
RBx
DAx0
DAx1 DAx2 DAx3 DAy0 DAy3 DBy0
Activate
Command
Bank B
Write
Command
CBx
DBx0 DBx1 DBx2 DBx3 DAy1 DAy2
Write with
Auto Precharge
Command
Bank B
CAyCAx
Write with
Auto Precharge
Command
Bank A
RBy
RBy
Activate
Command
Bank B
CBy
DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
Preliminary
62
August 1999
Page 63
EtronTech
1Mega x 32 SGRAM
bu
rsting b
egi
nning wi
th
the star
tin
g addres
s.
EM637327
Figure 18.1. Full Page Read Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
RBx
RBx RBy
CAx
CBx
tRRD
Command
Read
Command
Bank A
Ax+1
Ax
Activate
The burst counter wraps
Bank B
from the highest order
page address back to zero
during this time interval
Ax+2
Ax-2 Ax-1 Bx+2 Bx+5
Ax Ax+1 Bx
Read
Command
Bank B
Bx+1
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
Bx+3 Bx+4
Bx+6 Bx+7
Precharge
Command
Burst Stop
Command
Bank B
RBy
t
RP
Activate
Command
Bank B
Preliminary
63
August 1999
Page 64
EtronTech
1Mega x 32 SGRAM
Comma
nd
EM637327
Figure 18.2. Full Page Read Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CA S #
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
RBx
RBxCAx RBy
Ax
Activate
Command
Bank B
Ax+2 Ax-2 Ax-1 Bx+2 Bx+5
Ax+1
The burst counter wraps
from the highest order
page address back to zero
during this time interval
CBx
Ax Ax+1 Bx Bx+1 Bx+3 Bx+4
Read
Full Page burst operation does not
Command
terminate when the burst length is satisfied;
Bank B
the burst counter increments and continues
bursting beginning with the starting address.
Precharge
Command
Burst Stop
Bx+6
Bank B
RP
t
RBy
Activate
Command
Bank B
Preliminary
64
August 1999
Page 65
EtronTech
1Mega x 32 SGRAM
du
ring
th
is t
ime
in
terv
al
EM637327
Figure 18.3. Full Page Read Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=3)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
Read
Command
Bank A
RBx
RBxCAx
Activate
Command
Bank B
Ax+1
Ax
Ax+2 Ax-2 Ax-1 Bx+2 Bx+5
The burst counter wraps
from the highest order
page address back to zero
CBx
Ax Ax+1 Bx Bx+1 Bx+3 Bx+4
Read
Full Page burst operation does not
Command
terminate when the burst length is
Bank B
satisfied; the burst counter
increments and continues
bursting beginning with the
starting address.
Precharge
Command
Burst Stop
Command
Bank B
RBy
RBy
t
RP
Activate
Command
Bank B
Preliminary
65
August 1999
Page 66
EtronTech
1Mega x 32 SGRAM
be
gin
ning wit
h t
he
starting
ad
dre
ss.
EM637327
Figure 19.1. Full Page Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
Write
Command
Bank A
RBx
RBxCAx
DAx+ 1DAx
DAx+ 2 DAx+3 DA x- 1 DAx
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
CBx
DBx DBx+1
DAx+ 1
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
DBx+2
DBx+3
DBx+4 DBx+ 5 DBx+6 DBx+7
Data is ignored
Precharge
Command
Burst Stop
Command
Bank B
RBy
RBy
Activate
Command
Bank B
Preliminary
66
August 1999
Page 67
EtronTech
1Mega x 32 SGRAM
be
gin
ning wit
h t
he
starting
ad
dre
ss.
EM637327
Figure 19.2. Full Page Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
CAx
Write
Command
Bank A
RBx
RBx
DAx+ 1DAx
DAx+ 2 DAx+3 DA x- 1 DAx
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
CBx
DAx+ 1
DBx DBx+1
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
DBx+2
DBx+3
DBx+4 DBx+ 5 DBx+6
Data is ignored
Precharge
Command
Burst Stop
Command
Bank B
RBy
RBy
Activate
Command
Bank B
Preliminary
67
August 1999
Page 68
EtronTech
1Mega x 32 SGRAM
be
gin
ning wit
h t
he
starting
ad
dre
ss.
EM637327
Figure 19.3. Full Page Write Cycle
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK3
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=3)
A 8
A0~A7
DQM
DQ
RAx
RAx
Hi-Z
Activate
Command
Bank A
Write
Command
Bank A
RBx
RBxCAx
DAx+ 1DAx
DAx+ 2 DAx+3 DA x- 1 DAx
Activate
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
CBx
DBx DBx+1
DAx+ 1
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
DBx+2
DBx+3
DBx+4 DBx+ 5
Precharge
Command
Burst Stop
Command
Data is ignored
Bank B
RBy
RBy
Activate
Command
Bank B
Preliminary
68
August 1999
Page 69
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 20. Byte Write Operation
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T 16 T17 T 18 T19 T20 T 21 T22
CLK
tCK2
High
CKE
CS#
RAS#
CAS#
WE #
DSF
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
RAx
RAx
Activate
Command
Bank A
CAx
Re ad
Command
Bank A
Ax0 Ax1 Ax2
Upper 3 Bytes
are masked
Ax1 Ax2 Ax3
Lower Byte
is masked
CAy
DAy2
DAy1
DAy0 DAy1 DAy3
Write
Upper 3 Bytes
Command
Bank A
are masked
CAz
Read
Command
Az0
Lower Byte
is masked
Az1 Az2
Az1 Az2
Az3
Lower Byte
is masked
Preliminary
69
August 1999
Page 70
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Bank A
Bank A
Bank A
Bank A
EM637327
Figure 21. Burst Read and Single Write Operation
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=4, CAS# Latency=2)
A 8
A0~A7
DQM 0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
RAx
RAx
Hi-Z
H i-Z
Activate
Command
CAx
Read
Command
Ax0 Ax1 Ax2
Ax1 Ax2 Ax3
Ax0
Ax3
CAw
DQw0
DQw0
Single Write
Command
CAx
DQx0
Single Write
Command
CAy
Read
Command
Ay0 Ay1
Ay0
Lower Byte
is masked
Lower Byte
is masked
Ay2
Ay3
Ay3
CAz
Az0
Az0
Single Write
Command
Lower Byte
is masked
Preliminary
70
August 1999
Page 71
EtronTech
1Mega x 32 SGRAM
Bank A
Bank A
Bank A
Bank A
Figure 22. Full Page Burst Read and Single Write Operation
CLK
CKE
CS#
RAS#
CAS#
WE#
(Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
High
EM637327
DSF
BS
A 8
A0~A7
DQM 0
DQM1~3
DQ0 - DQ7
DQ8 - DQ31
RAv
RAv
Activate
Command
CAv
Read
Command
Bank A
Av0
Av0
Burst Stop
Command
Av1
Av2
Av3
Av1 Av2 Av3
CAw
DQw0
DQw0
Single Write
Command
CAx
DQx0
DQx0
Single Write
Command
CAy
Read
Command
Ay0
Ay0
Burst Stop
Command
Ay1
Ay1
Ay2
Ay2
Ay3
Ay3
Preliminary
71
August 1999
Page 72
EtronTech
1Mega x 32 SGRAM
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Precha
rge
Figure 23. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK1
CKE
CS#
RAS#
CA S #
WE#
High
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
EM637327
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
DSF
BS
A 8
A0~A7
DQM
DQ
RBu
RBu
Activate
Command
Bank B
CBw
t
Command
Read
Bank B
with Auto
RAw
RAw
RP
Activate
Bank A
CAw
t
RP
Command
Read
Bank A
with Auto
RBx
RBx
Activate
Bank B
t
Command
Read
Bank A
with Auto
RBv
RBv
RP
Activate
Bank B
RAu
CBu
RAu CAu
Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1 Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0
Activate
Command
Bank A
Read
Bank B
with Auto
CBv
t
RP
Command
Read
Bank B
with Auto
RAv
RAv
Activate
Bank A
CAv
t
Command
Read
Bank A
with Auto
RBw
RBw
RP
Activate
Bank B
CBx
t
RP
Read
Bank B
with Auto
RAx
RAx CAx
Activate
Command
Bank A
t
RP
Command
Read
Bank A
with Auto
RBy
RBy CBy
Activate
Bank B
Read
Bank B
with Auto
RAy
RAy CAy
t
RP
Activate
Command
Bank A
Read
Bank A
with Auto
RBz
RBz CBz
t
RP
Activate
Command
Bank B
t
RP
Command
Read
Bank B
with Auto
RAz
RAz
Activate
Bank A
Preliminary
72
August 1999
Page 73
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 24. Full Page Random Column Read
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
RAx
RAx
Activate
Command
Bank A
RRD
t
RBx
RBx CAx
Activate
Command
Bank B
CBx CAy CBy
RCD
t
Read
Command
Bank B
Read
Command
CAz
Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank A
CBz
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
RP
t
RBw
RBw
Activate
Command
Bank B
Preliminary
73
August 1999
Page 74
EtronTech
1Mega x 32 SGRAM
is
mask
ed
EM637327
Figure 25. Full Page Random Column Write
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
tCK2
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=2)
A 8
A0~A7
DQM
DQ
RAx
RAx
Activate
Command
Bank A
t
RRD
RBx
RBx CAx
Activate
Command
Bank B
CBx CAy CBy
t
RCD
DAx0 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1
Write
Command
Bank A
Write
Command
Bank B
Command
Write
Bank A
Write
Command
Bank B
CAz
Write
Command
Bank A
CBz
Write
Command
Bank B
tWR
tRP
DBz2
Precharge
Command Bank B
(Precharge Temination)
Write Data
RBw
RBw
Activate
Command
Bank B
Preliminary
74
August 1999
Page 75
EtronTech
1Mega x 32 SGRAM
Bank A
EM637327
Figure 26.1. Precharge Termination of a Burst
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK1
CKE
CS#
RAS#
CAS#
WE#
DSF
BS
(Burst Length=Full Page, CAS# Latency=1)
A 8
A0~A7
DQM
DQ
RAx
RAx
CAx RAy
DAx0 DAx1 DAx2 DAx3 DAx4
Activate
Command
Bank A
Precharge Termination
Write data is masked.
Write
Command
Bank A
of a Write Burst.
t
WR t
Precharge
Command
Bank A
RAy
RP
Activate
Command
CAy
Read
Command
Bank A
Ay0 Ay1 Ay2
Precharge
Command
Bank A
RAz
RAz
tRP
Activate
Command
Bank A
CAz
Precharge
Termination of
a Read Burst.
DAz1 DAz4 DAz5
Write
Command
Bank A
DAz3DAz2DAz0
DAz6 DAz7
Preliminary
75
August 1999
Page 76
EtronTech
1Mega x 32 SGRAM
Write
data is ma
sked.
Figure 26.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
High
CKE
CS#
RAS#
CAS#
WE#
DSF
EM637327
BS
A 8
A0~A7
DQM
DQ
RAx
RAx
Activate
Command
Bank A
CAx
DAx0 DAx1DAx2 DAx3
Write
Command
Bank A
Precharge Termination
of a Write Burst.
tWR
Precharge
Command
Bank A
tRP
Activate
Command
Bank A
RAy
RAy CAy
Read
Command
Bank A
Precharge
Command
Bank A
tRP
Ay2Ay0 Ay1
RAz
RAz
Activate
Command
Bank A
CAz
Read
Command
Bank A
Precharge Termination
of a Read Burst
tRP
Az0 Az1 Az2
Precharge
Command
Bank A
Preliminary
76
August 1999
Page 77
EtronTech
1Mega x 32 SGRAM
of a Write Burst
Figure 26.3. Precharge Termination of a Burst
CLK
High
CKE
CS#
RAS#
CAS#
WE#
DSF
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T1 3 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK3
EM637327
BS
A 8
A0~A7
DQM
DQ
RAx
RAx
Activate
Command
Bank A
CAx
DAx0
Write
Command
Bank A
Write Data
is masked
t
WR
DAx1
Precharge
Command
Bank A
Precharge Termination
t
RP
RAy
RAy
Activate
Command
Bank A
CAy
Read
Command
Bank A
Ay0 Ay1 Ay2
Precharge
Command
Bank A
t
RP
RAz
RAz
Activate
Command
Bank A
Precharge Termination
of a Read Burst
Preliminary
77
August 1999
Page 78
EtronTech
1Mega x 32 SGRAM
100 Pin 14x20 mm Package Outline Drawing Information
D
D1
(D3)
EM637327
E 1(E3)
E
A
A
θ
L
(L1)
PIN #1
SECTION A - A
e
A 2
A
A 1
y
b
Packaging Dimensions
Unit = mm
EM637327Q-XX EM637327TQ-XX
Symbol Definition min normal max min normal max
A Overall Height 3.40 1.60
A1 Stand Off 0.25 0.05 0.10 0.15
A2 Body Thickness 2.60 2.80 3.00 1.35 1.40 1.45
b Lead Width 0.22 0.30 0.38 0.22 0.32 0.38
C Lead Thickness 0.13 0.15 0.23 0.09 0.20
D Terminal Dimension 22.95 23.20 23.45 21.90 22.00 22.10
D1 Package Body 19.90 20.00 20.10 19.90 20.00 20.10
D3 Reference 18.85 REF. 18.85 REF.
E Terminal Dimension 16.95 17.20 17.45 15.90 16.00 16.10
E1 Package Body 13.90 14.00 14.10 13.90 14.00 14.10
E3 Reference 12.35 REF. 12.35 REF.
e
Lead Pitch 0.65 REF. 0.65 REF.
L Foot Length 0.65 0.80 0.95 0.45 0.60 0.75
L1 Lead Length 1.60 REF. 1.00 REF.
y Coplanarity 0.10 0.10
Lead Angle
θ
0.00° 7.00° 0.00° 7.00°
SEATING PLANE
C
Preliminary
78
August 1999
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