Page 1
EL2004/EL2004C
350 MHz FET Buffer
EL2004/EL2004C November 1993 Rev G
Features
# Slew rateÐ2500 V/ms
# Rise timeÐ1 ns
# BandwidthÐ350 MHz
# ELH0033Ðpin compatible
g
#
5tog15V operation
# 100 mA output current
# MIL-STD-883B Rev. C devices
manufactured in U.S.A.
Applications
# Coaxial cable driver
# Fast op amp booster
# Flash converter driver
# Video line driver
# High-speed sample and hold
# Pulse transformer driver
# A.T.E. pin driver
Ordering Information
Part No. Temp. Range Package Outline
EL2004CGb25§Ctoa85§C TO-8 MDP0002
EL2004G
EL2004L
EL2004L/MILb55§Ctoa125§C 52-Pad LCC MDP0013
5962-89659 is the SMD version of this device.
b
55§Ctoa125§C TO-8 MDP0002
b
55§Ctoa125§C 52-Pad LCC MDP0013
General Description
The EL2004 is a very high-speed, FET input buffer/line driver
designed for unity gain applications at both high current (up to
100 mA) and at frequencies up to 350 MHz. The 2500 V/ms slew
rate and wide bandwidth ensures the stability of the circuit
when the EL2004 is used inside op amp feedback loops.
Applications for the EL2004 include line drivers, video buffers,
wideband instrumentation, and high-speed drivers for inductive
and capacitive loads. The performance of the EL2004 makes it
an ideal buffer for video applications including input buffers for
flash A/D converters, and output buffers for video DACs. Its
excellent phase linearity is particularly advantageous in digital
signal processing applications.
Elantec facilities comply with MIL-I-45208A and are MILSTD-1772 certified. Elantec’s Military devices comply with
MIL-STD-883B Revision C and are manufactured in our rigidly
controlled, ultra-clean facilities in Milpitas, California. For additional information on Elantec’s Quality and Reliability Assurance Policy and procedures request brochure QRA-1.
Simplified Schematic
Ý
Connection Diagram
Case is Electrically Isolated
Top View
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ‘‘controlled document’’. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. Patent pending.
©
1989 Elantec, Inc.
2004– 1
2004– 3
Page 2
EL2004/EL2004C
350 MHz FET Buffer
Absolute Maximum Ratings
V
S
V
IN
P
D
I
OC
I
OP
Important Note:
All parameters having Min/Max specifications are guaranteed. The Test Level column indicates the specific device testing actually
performed during production and Quality inspection. Elantec performs most electrical tests using modern high-speed automatic test
equipment, specifically the LTX77 Series system. Unless otherwise noted, all tests are pulsed tests, therefore T
Test Level Test Procedure
g
15V DC Electrical Characteristics
e
V
S
Supply Voltage (VabVb) 40V
Input Voltage 40V
Power Dissipation (See curves) 1.5W
Continuous Output Current
Peak Output Current
I 100% production tested and QA sample tested per QA test plan QCX0002.
II 100% production tested at T
III QA sample tested per QA test plan QCX0002.
IV Parameter is guaranteed (but not tested) by Design and Characterization Data.
V Parameter is typical value at T
g
15V, T
MIN
T
and T
MAX
k
T
A
k
T
MIN
MAX,VIN
A
per QA test plan QCX0002.
e
0V, R
e
(T
25§C)
A
T
Operating Temperature Range
A
EL2004
EL2004C
g
100 mA
g
250 mA
T
Operating Junction Temperature 175§C
J
T
Storage Temperature
ST
Lead Temperature
(Soldering, 10 seconds) 300
e
25§C and QA sample tested at T
e
25§C for information purposes only.
A
e
1kXunless otherwise specified (Note 1)
L
A
e
25§C,
b
55§Ctoa125§C
b
25§Ctoa85§C
b
65§Ctoa150§C
e
e
T
J
C
§
TA.
EL2004 EL2004C
Parameter Description Test Conditions
V
A
R
R
V
I
I
OS
V
IN
OUT
O
IN
S
Output Offset R
Voltage
Voltage Gain V
Input Impedance T
Output V
Impedance DR
Output Voltage V
Swing
Input Current T
s
100 kX,T
S
s
R
100 kX 15 I 25 III mV
S
e
g
IN
e
R
100X,V
L
e
25§C, V
J
e
g
IN
e
L
e
g
IN
e
g
V
IN
e
T
25§C
A
e
25§C (Note 2) 0.25 I 2.0 I nA
J
e
T
25§C (Note 3) 2.5 IV 20 IV nA
A
e
T
T
J
A
eb
V
IN
Supply Current 20 24 I 20 24 II mA
e
25§C 5 10 I 12 20 I mV
J
10V 0.97 0.98 1.0 I 0.96 0.98 1.0 II V/V
e
IN
e
g
IN
1VDC,
100X to Infinity
14V
T
MAX
e
L
10.5V, R
e
10V 20 V 20 V nA
Min Typ Max
g
10V 0.92 0.95 0.98 I 0.90 0.95 0.98 II V/V
1V 10810
11
Test
Min Typ Max
Level Level
I10810
11
4 8 I 4 10 II X
100X
g12g
g9g
13 I
9.8 I
g12g
13 II V
g9g
9.8 I V
10 I 50 III nA
Test
I X
Units
C
TDis 3.2in
2
Page 3
EL2004/EL2004C
350 MHz FET Buffer
g
5V DC Electrical Characteristics
e
g
V
5V, T
S
Parameter Description Test Conditions
V
OS
A
V
R
IN
R
OUT
V
O
I
IN
PSRR Power Supply V
I
S
Note 1: When operating at elevated temperatures the power dissipation of the EL2004 must be limited to the values shown in the
typical performance curve ‘‘Maximum Power Dissipation vs Temperature’’. Junction to case thermal resistance is 31
when dissipation is spread among the transistors in a normal AC steady-state condition. In special conditions where heat is
concentrated in one output device, junction temperature should be calculated using a thermal resistance of 70
Note 2: Specification is at 25
temperatures will exceed the value at T
may rise 40
I
IN
Note 3: Measured in still air seven minutes after application of power. See graph of Input Current During Warm-up for further
information.
Note 4: Bandwidth is calculated from the rise time. The EL2004 has a single pole gain and phase response up to the
frequency.
Note 5: Slew rate is measured between V
Note 6: Slew rate is measured between V
k
MIN
k
T
T
A
MAX,VIN
e
0V, R
e
50X unless otherwise specified
L
EL2004 EL2004C
Min Typ Max
Output Offset R
Voltage
Voltage Gain V
Input Impedance T
Output V
Impedance DR
Output Voltage V
Swing
Input Current T
Rejection Ratio R
Supply Current R
C junction temperature due to requirements of high-speed automatic testing. Actual values at operating
§
Cto60§C above ambient and more under load conditions. Accordingly, VOSmay change one to several mV, and
§
will change significantly during warm-up. Refer to IINvs Temperature graph for expected values.
s
100 kX,T
S
s
R
100 kX 35 I 35 III mV
S
e
g
IN
e
g
V
IN
e
25§C, V
J
e
g
IN
e
L
e
g
IN
e
25§C (Note 2) 250 I 500 I pA
J
e
T
25§C (Note 3) 2.5 IV 5 IV nA
A
e
T
T
J
A
e
g
S
e
1kX
L
e
1kX 17.5 20 I 17.5 20 II mA
L
OUT
OUT
e
25§C 10 30 I 10 30 I mV
J
e
1V, R
1kX 0.90 0.95 1.0 I 0.90 0.95 1.0 II V/V
L
1V 0.80 0.88 0.95 I 0.80 0.88 0.95 II V/V
e
g
1V 10810
IN
1VDC,
50X to Infinity
4V
e
T
MAX
g
5V tog15V
e
25§C. When supply voltages areg15V, no-load operating junction temperatures
J
ea
2.5V andb2.5V for this test.
ea
1V andb1V for this test. Pulse repetition rate isk50 MHz.
11
4 8 I 4 10 II X
2.0g2.9 I
60 V 60 V dB
Test
Min Typ Max
Level Level
I101010
g
11
2.0g2.9 III V
10 I 20 III nA
Test
I X
C/W.
§
Units
C/W
§
b
3dB
TDis 3.2inTDis 1.3in
g
15V AC Electrical Characteristics
e
g
V
S
15V, R
L
e
1kX,R
S
e
50X,T
e
25§C unless otherwise specified
J
EL2004 EL2004C
Parameter Description Test Conditions
Min Typ Max
Test
Min Typ Max
Level Level
Test
Units
BW Bandwidth (Note 4) 200 350 I 200 350 I MHz
e
R
50X 140 200 I 140 200 I MHz
L
e
t
s
C
in
Settling Time to 1% DV
IN
Input Capacitance 3 V 3 V pF
e
1V, t
3ns 6 V 6 V ns
r
3
Page 4
EL2004/EL2004C
350 MHz FET Buffer
g
15V AC Electrical Characteristics
e
g
V
S
Parameter Description Test Conditions
SR Slew Rate V
t
r
t
p
R
OUT
a
PSRR Power Supply DV
b
PSRR Power Supply DV
g
5V AC Electrical Characteristics
e
g
V
S
Parameter Description Test Conditions
BW Bandwidth R
t
s
C
in
SR Slew Rate V
t
r
t
p
R
OUT
a
PSRR Power Supply DV
b
PSRR Power Supply DV
15V, R
e
L
1kX,R
S
e
50X,T
e
25§C unless otherwise specified Ð Contd.
J
e
g
5V (Note 5) 2000 2500 I 2000 2500 I V/ms
IN
e
C
100 pF, V
L
(Note 5)
IN
Rise Time DVINP 0.6V 1.0 1.7 I 1.0 1.7 I ns
Note: See Test Figure
Propagation Delay
Note: See Test Figure
Output fe1 MHz, V
Impedance DR
Rejection Ratio fe1 kHz
Rejection Ratio f
5V, R
e
L
50X,R
e
50X,T
S
DV
P 0.6V, R
IN
DV
P 0.6V 1.0 2.0 I 1.0 2.0 I ns
IN
e
100X to Infinity
L
ae
S
be
S
e
1 kHz
e
25§C unless otherwise specified
J
e
1kX 175 220 I 175 220 I MHz
L
g
g
IN
1.5 V
1.5 V
L
e
peak
e
peak
(Note 4) 125 150 IV 125 150 IV MHz
e
Settling Time to 1% DV
IN
e
1V, t
3ns 8 V 8 V ns
r
Input Capacitance 3 V 3 V pF
e
g
2V (Note 6) 900 1200 I 900 1200 I V/ms
IN
e
C
100 pF, V
L
e
R
L
Rise Time R
Note: See Test Figure
Propagation Delay R
Note: See Test Figure
e
L
e
R
L
e
L
Output fe1 MHz, V
e
e
L
be
S
ae
S
1 kHz
Impedance DR
Rejection Ratio fe1 kHz
Rejection Ratio f
IN
1kX(Note 6)
1kX,DVINP 0.6V 1.6 2.0 I 1.6 2.0 I ns
50X, DVINP 0.6V 2.3 2.8 IV 2.3 2.8 IV ns
1kX,DVINP 0.6V
e
IN
100X to Infinity
g
0.5 V
peak
g
0.5 V
peak
EL2004 EL2004C
Min Typ Max
e
g
5V
1200 V 1200 V V/ms
Test
Min Typ Max
Level Level
Test
50X 1.7 2.5 I 1.7 2.5 I ns
1V
RMS
4V4VX
40 V 40 V dB
40 V 40 V dB
EL2004 EL2004C
Min Typ Max
e
g
2V
500 V 500 V V/ms
Test
Min Typ Max
Level Level
Test
1.2 2.4 I 1.2 2.4 I ns
1V
RMS
4V4VX
30 V 30 V dB
30 V 30 V dB
Units
TDis 2.7inTDis 3.4in
Units
4
Page 5
AC Test Circuit
Typical Performance Curves
TO-8
Maximum Power
Dissipation
EL2004/EL2004C
350 MHz FET Buffer
2004– 4
2004– 5
Gain vs Input Voltage Output Current
5
Output Resistance vs
2004– 7
Page 6
EL2004/EL2004C
350 MHz FET Buffer
Typical Performance Curves
Rise Time vs
Temperature
Frequency Response Voltage
Ð Contd.
Small Signal Pulse
Response
Offset Voltage vs Supply
Large Signal Pulse
Response
Normalized Input Bias
Current During
Warm-up
Supply Current vs
Supply Voltage
Output Voltage vs
Supply Voltage
2004– 8
6
Page 7
EL2004/EL2004C
350 MHz FET Buffer
Applications Information
The EL2004 is one member of a family of high
performance buffers manufactured by Elantec.
The 2004 is optimized for speed while others offer
choices of input DC parameters or output drive
or cost. The following table illustrates those
members available at the time of this printing.
Consult the factory for the latest capabilities in
this developing line.
Elantec’s Buffer Family
Slew
Ý
Part
ELH0002 200 50 6 mA 400 7
ELH0033 1500 100 2.5 nA 250 2.9
EL2004 2500 350 2.5 nA 250 1.0
EL2005 1500 140 0.1 nA 250 2.5
Bandwidth
Rate
V/ms (Warm) mA ns
MHz
Input Peak Rise
Current I
OUT
Time
Recommended Layout Precautions
The very high-speed performance of the EL2004
can only be realized by taking certain precautions in circuit layout and power supply decoupling. Low inductance ceramic chip or disc power
supply decoupling capacitors of 0.1 mF or more
should be connected with the shortest practical
lead lengths between the device supply leads and
a ground plane. In addition, it can be helpful to
parallel these with 4.7 mF electrolytics (Tantalum preferred). Failure to follow these precautions can result in oscillation.
Circuit Operation
The EL2004 is effectively an ideal unity gain amplifier with almost infinite input impedance and
about 6X output impedance.
Input Characteristics
The input impedance of a junction FET is a
strong function of temperature and input voltage. Nominal input resistance of EL2004 is 10
at 25§C junction, but as IBdoubles every 11§Cin
the JFET, the input resistance falls. During
warm-up, self-heating raises the junction temperature up to 60
operating I
sheet 25
C or more (without heatsink) so
§
will be much higher than the data
B
C specification.
§
Another factor which can increase bias current is
input voltage. If the input voltage is more than
20V below the positive supply, the input current
rises exponentially. (See Curve.)
12
Input Bias Current vs
Temperature
Input Bias Current vs
Input Voltage
In applications such as sample and hold circuits
where it is important to maintain low input bias
current over input voltage range, the EL2005
High Accuracy Fast Buffer is recommended.
The input capacitance of EL2004 comprises the
FET device gate-to-source capacitance (which is
a function of input voltage) and stray capacitance to the case. Effective input capacitance can
be minimized by connecting the case to the output since it is electrically isolated. Or, for reduced
radiation, the case may be grounded. The AC
characteristics specified in this data sheet were
obtained with the case floating.
Offset Voltage Adjustment
The EL2004’s offset voltages have been actively
laser trimmed at
g
15V supplies to meet specified
limits when the offset adjust pin is shorted to the
offset preset pin. If external offset null is required, the offset adjust pin should be connected
to a 200X trim pot connected to the negative supply.
7
2004– 9
Page 8
EL2004/EL2004C
350 MHz FET Buffer
Circuit Operation
Offset Zero Adjust
Ð Contd.
2004– 10
Capacitive Loading
The EL2004 is designed to drive capacitive loads
up to several thousand picofarads without oscillation. However, peak current resulting from
charging currents on fast edges should be limited
below the absolute maximum peak current rating
of 250 mA. In some cases it may be necessary to
employ one of the current limit schemes shown
below.
Short Circuit Protection
Dynamic response of the EL2004 was preserved
by excluding current limit circuits which are not
needed in most applications. However, in situations where operating conditions are not controlled, short circuit protection can be added by
inserting resistors between the output device collectors and supplies as illustrated.
Using Resistor
Current Limiting
2004– 11
Suitable resistor values can be calculated as follows:
a
e
R
SC
where I
V
I
SC
SC
b
V
e
I
SC
s
100 mA for EL2004.
Current Limiting
Using Current Sources
The inclusion of limiting resistors in the collectors of the output devices will reduce the output
voltage swing and speed. Decoupling V
b
V
pins with capacitors to ground will retain
C
C
full output swing for transient pulses.
An alternate active current limit technique that
retains full DC output swing is shown above.
Here the current sources are saturated during
normal operation thus applying full supply voltage to the V
pins. Under fault conditions, the
C
voltage decreases as the current source reaches its
limit.
R
LIM
e
V
BE
I
SC
e
100 mA
0.6V
e
6X
Power Supplies
The EL2004 has been characterized for bothg15
g
and
5V dual supply operation, but other combinations can also be useful. For example, in many
video applications it is only necessary for the output to swing
g
2V or less, but speed and distortion are important. In this situation, the input
stage can be operated at the full
g
15V supply
while the output collectors are returned to
The speed and distortion will be almost as good
as if the whole circuit was operating at
but the dissipation is substantially reduced and
higher load currents can be safely accommodated.
8
a
g
2004– 12
and
g
15V,
5V.
Page 9
EL2004/EL2004C
350 MHz FET Buffer
Circuit Operation
Ð Contd.
Increasing Operating Voltage
and Reducing Thermal Tail
When driving heavy loads, the changing dissipation in the output transistors can sometimes
cause temperature gradients in the circuit which
cause a shift in offset voltage and the phenomenon known as ‘‘thermal tail’’. Bootstrapping the
output as illustrated substantially reduces the
power in the output transistors and mitigates the
effect.
High Voltage Inputs can be Accommodated
with Bootstrapped Supplies
2004– 13
Hardware
In order to utilize the full drive capabilities of the
EL2004, it should be mounted with a heatsink,
particularly for extended temperature operation.
Suitable heatsinks include Thermalloy 2240A
(33
C/W), Wakefield 215CB (30§C/W) and
§
IERC-UP-TO-848CB (15
C/W).
§
General Application Suggestions
Video DAC Buffer
Many of the available video D to A converters
are unable to directly drive 50X or 75X cables.
The EL2004’s excellent phase linearity at video
frequencies make it an ideal solution. In critical
applications or where line termination is not controlled, a matching pad should be used as shown.
The capacitor should be adjusted for optimum
pulse response. If properly layed out this circuit
will not overshoot.
Video DAC Buffer
2004– 14
Impedance Matching
The EL2004 provides power gain and isolation
between source and load when used as an active
tap or impedance matching device as illustrated
here. In this example, there is no output matching pad between the 2004 and the 75X line. Such
matching is not needed when the distant end of
the cable is properly terminated as there is no
reflected signal to worry about and the 2004 isolates the source. This technique allows the full
output voltage of the EL2004 to be applied to the
load.
Impedance Converter
The case is isolated from the circuit and may be
connected to system chassis. Sockets are not recommended as they add substantial inductance
and capacitance which impair the performance of
the device. However, for test purposes they are
unavoidable and precautions such as shielding input from output are suggested.
2004– 15
9
Page 10
EL2004/EL2004C
350 MHz FET Buffer
General Application Suggestions
Inverting Amplifier for 20 MHz Flash Converter
Boosting the Output
Unlike most integrated cicuits, two or more
EL2004’s can be paralleled for increased output
drive. This capability results from the finite output resistance and low output mismatch of the
50X Cable Driver with Short Circuit Protection
Ð Contd.
2004– 16
EL2004. For example, a 50X cable driver with
g
10V capability can be made by using two
EL2004’s. A short-circuit protected version is
shown below.
NPNe2N6551
PNPe2N6554
or equivalent
2W devices
(
2004– 17
10
Page 11
Burn-In Circuit
EL2004/EL2004C
350 MHz FET Buffer
Pin numbers are for TO-8 package.
LCC uses the same schematic.
2004– 18
11
Page 12
EL2004/EL2004C
350 MHz FET Buffer
EL2004 Macromodel
* Connections: input
*
*
*
*
*
*
.subckt M2004 5 12 1 10 9 11
* Models
.model qn npn (is
a
cjee5pF cjce5pF mjee.42 mjce.23 tfe.3nS tre200nS bre5 vtfe0)
.model qp pnp (is
a
cjee5.7pF cjce4pF tfe.3nS mjee.32 mjce.43 tre170nS bre5 vtfe0)
.model qf njf (vto
* Resistors
r1 20 21 58.33
r2 27 10 58.33
r3 22 11 2
r4 11 23 2
* Transistors
j112520qf
j4 24 10 26 qf
q2 21 21 25 qn
q3 24 24 25 qp
q512122qn
q692423qp
q7 26 26 27 qn
.ends
a
V
l
ll
lll
llll
lllll
Vc
a
b
V
Vc
b
output
llllll
e5eb
14 bfe150 vafe100 rce1rbe5ree1 ikfe200mA
e5eb
14 bfe150 vafe100 rce2rbe3ree1 ikfe100mA
eb
3V betae4.0eb3 cgde4pF cgse10pF lambdae671.0eb6)
TABWIDE
TDis 3.8in
12
Page 13
EL2004/EL2004C
350 MHz FET Buffer
EL2004 Macromodel
Ð Contd.
2004– 19
13
Page 14
BLANK
14
Page 15
BLANK
15
Page 16
EL2004/EL2004C
350 MHz FET Buffer
EL2004/EL2004CNovember 1993 Rev G
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes
in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any
circuits described herein and makes no representations that they are free from patent infringement.
WARNING Ð Life Support Policy
Elantec, Inc. products are not authorized for and should not be
used within Life Support Systems without the specific written
consent of Elantec, Inc. Life Support systems are equipment in-
Elantec, Inc.
1996 Tarob Court
Milpitas, CA 95035
Telephone: (408) 945-1323
(800) 333-6314
Fax: (408) 945-9305
European Office: 44-71-482-4596
tended to support or sustain life and whose failure to perform
when properly used in accordance with instructions provided can
be reasonably expected to result in significant personal injury or
death. Users contemplating application of Elantec, Inc. products
in Life Support Systems are requested to contact Elantec, Inc.
factory headquarters to establish suitable terms & conditions for
these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages.
Printed in U.S.A.16
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