Datasheet dsPIC33FJ12GP201, dsPIC33FJ12GP202 Datasheet

dsPIC33FJ12GP201/202

Data Sheet

High-Performance, 16-bit Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

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• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K

EELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PRO MA TE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programmin g , IC SP, ICEPIC, Mindi, MiW i , MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC

logo, PowerCal, PowerInfo, PowerMate, PowerT ool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

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All other trademarks mentioned herein are property of their respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

MCUs and dsPIC® DSCs, KEELOQ

code hopping

dsPIC33FJ12GP201/202

High-Performance, 16-Bit Digital Signal Controllers

Operating Range:

• Up to 40 MIPS operation (at 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)

- Extended temperature range (-40°C to +125°C)

High-Performance DSC CPU:

• Modified Harvard architecture

• C compiler optimized inst ruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M instruction words

• Linear data memory addressing up to 64 Kbytes

• 83 base instructions, mostly one word/one cycle

• Sixteen 16-bit general purpose registers

• Two 40-bit accumulators with rounding and saturation options

• Flexible and powerful addressing modes:

-Indirect

- Modulo

- Bit-Reversed

• Software stack

• 16 x 16 fractional/integer multiply operations

• 32/16 and 16/16 divide operations

• Single-cycle multiply and accumulate:

- Accumulator write back for DSP operations

- Dual data fetch

• Up to ±16-bit shifts for up to 40-bit data

Interrupt Controller:

• 5-cycle latency

• 118 interrupt vectors

• Up to 21 available interrupt sources

• Up to three external interrupts

• Seven programmable priority levels

• Four processor exceptions

On-Chip Flash and SRAM:

• Flash program memory (12 Kbytes)

• Data SRAM (1024 bytes)

• Boot and General Security for Program Flash

Digital I/O:

• Peripheral Pin Select Functionality

• Up to 21 programmable digital I/O pi ns

• Wake-up/interrupt-on-change for up to 21 pins

• Output pins can drive from 3.0V to 3.6V

• Up to 5V output with open drain configuration

• All digital input pins are 5V tolerant

• 4 mA sink on all I/O pins

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated Phase-Locked Loop (PLL)

- Extremely low jitter P LL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monito r

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare:

• Timer/Counters, up to three 16-bit timers:

- Can pair up to make one 32-bit timer

- One timer runs as Real-Time Clock with external 32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to four channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to two channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM Mode

dsPIC33FJ12GP201/202

Communication Modules:

• 4-wire SPI:

- Framing supports I/O interface to simple codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and sampling modes

•I

C™:

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

•UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4 character TX and RX FIFO buffers

- LIN bus support

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

encoding and decoding in hardware

Analog-to-Digit al Converters (ADCs):

• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:

- Two and four simultaneous samples (10-bit ADC)

- Up to 10 input channels with auto-scanning

- Conversion start can be manual or synchronized with one of four trigger sources

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

CMOS Flash T echnology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial and extended temperature

• Low power consumption

Packaging:

• 18-pin SDIP/SOIC

• 28-pin SDIP/SOIC/SSOP/QFN Note: See Table 1 for the exact peripheral

features per device.

dsPIC33FJ12GP201/202

dsPIC33FJ12GP201/202 Product Families

The device names, pin counts, memory sizes, and peripheral availability of each family are listed below, followed by their pinout diagrams.

TABLE 1: dsPIC33FJ12GP201/202 CONTROLLER FAMILIES

Remappable Peripherals

(2)

Device

dsPIC33FJ12GP201 18 12 1 8 3

dsPIC33FJ12GP202 28 12 1

Note 1: Only two out of three timers are remappable.

2: Only two out of three interrupts are remappable.

Pins

Program Flash Memory

(Kbyte)

RAM

(Kbyte)

Remappable

Pins

(1)

UART

16-bit Timer

Input Capture

421311 ADC,

Std. PWM

Output Compare

External Interrupts

SPI

6 ch

10 ch

C™

10-Bit/12-Bit ADC

113SDIP

121SDIP

Packages

I/O Pins (Max)

SOIC

SSOP

QFN

dsPIC33FJ12GP201/202

18-PIN SDIP, SOIC

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/V

REF-/CN3/RA1

INT0/RP7

(1)

/CN23/RB7

PGD3/EMUD3/SOSCI/RP4

(1)

/CN1/RB4

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

OSCO/CLKO/CN29/RA3

OSCI/CLKI/CN30/RA2

PGC1/EMUC1/AN3/RP1

(1)

/CN5/RB1

PGD1/EMUD1/AN2/RP0

(1)

/CN4/RB0

AN6/RP15

(1)

/CN11/RB15

AN7/RP14

(1)

/CN12/RB14

SDA1/RP9

(1)

/CN21/RB9

SCL1/RP8

(1)

/CN22/RB8

1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11 10

VSS

VDD

VDDCORE

MCLR

dsPIC33FJ12GP201

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

28-PIN SDIP, SOIC, SSOP

INT0/RP7

(1)

/CN23/RB7

MCLR

AV ss

AN7/RP14

(1)

/CN12/RB14

DDCORE

ASCL1/RP6

(1)

/CN24/RB6

TDO/SDA1/RP9

(1)

/CN21/RB9

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

AN4/RP2

(1)

/CN6/RB2

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

OSCO/CLKO/CN29/RA3

AN5/RP3

(1)

/CN7/RB3

PGD3/EMUD3/SOSC/RP4

(1)

/CN1/RB4

AN8/RP13

(1)

/CN13/RB13

AN6/RP15

(1)

/CN11/RB15

AN9/RP12

(1)

/CN14/RB12

ASDA1/RP5

(1)

/CN27/RB5

Vss

OSCI/CLKI/CN30/RA2

TMS/RP11

(1)

/CN15/RB11

TDI/RP10

(1)

/CN16/RB10

Vss

TCK/SCL1/RP8

(1)

/CN22/RB8

PGD2/EMUD2/AN0/V

REF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

PGC1/EMUC1/AN3/RP1

(1)

/CN5/RB1

PGD1/EMUD1/AN2/RP0

(1)

/CN4/RB0

dsPIC33FJ12GP202

Pin Diagrams

28-Pin QFN

1 2 3 4 5 6 7

21 20 19 18 17 16 15

28 27 26 25 24 23 22

8 9 10 11 12 13 14

PGD1/EMUD1/AN2/RP0

(1)

/CN4/RB0

PGC1/EMUC1/AN3/RP1

(1)

/CN5/RB1

AN4/RP2

(1)

/CN6/RB2

AN5/RP3

(1)

/CN7/RB3

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/RA3

DDCORE

TDI/RP10

(1)

/CN16/RB10

TMS/RP11

(1)

/CN15/RB11

AN9/RP12

(1)

/CN14/RB12

TDO/SDA1/RP9

(1)

/CN21/RB9

AN8/RP13

(1)

/CN13/RB13

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

PGD3/EMUD3/SOSCI/RP4/CN1/RB4

ASDA1/RP5

(1)

/CN27/RB5

ASCL1/RP6

(1)

/CN24/RB6

INT0/RP7

(1)

/CN23/RB7

TCK/SCL1/RP8

(1)

/CN22/RB8

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

MCLR

AN6/RP15

(1)

/CN11/RB15

AN7/RP14

(1)

/CN12/RB14

dsPIC33FJ12GP202

AVSS

Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available

peripherals.

dsPIC33FJ12GP201/202

Pin Diagrams (Continued)

dsPIC33FJ12GP201/202

Table of Contents

1.0 Device Overview ..........................................................................................................................................................................7

2.0 CPU............................................................................................................................................................................................ 11

3.0 Memory Organization. ................................................................................................................................................................ 23

4.0 Flash Program Memory...................................... ........................................................................................................................ 47

5.0 Resets ....................................................................................................................................................................................... 53

6.0 Interrupt Controller ......................................... ............................................................................................................................ 61

7.0 Oscillator Configuration..............................................................................................................................................................89

8.0 Power-Saving Features...................... ........................................................................................................................................ 97

9.0 I/O Ports ................................................................................................................................................................................... 101

10.0 Timer1......................................................................................................................................................................................121

11.0 Timer2/3 Feature................. .............................................................................. .......................................................................123

12.0 Input Capture.............................................................................................................. ..............................................................129

13.0 Output Compare...................................................................... .................................................................................................131

14.0 Serial Peripheral Interface (SPI)...............................................................................................................................................135

15.0 Inter-Integrated Circuit™ (I

16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 147

17.0 10-bit/12-bit Analog-to-Digital Converter (ADC)............................................................ ...........................................................153

18.0 Special Features......................................................................................................................................................................167

19.0 Instruction Set Summary..........................................................................................................................................................173

20.0 Development Support. .............................................................................................................................................................. 181

21.0 Electrical Characteristics.......................................................................................................................................................... 185

22.0 Packaging Information..... .................................................... .....................................................................................................219

Appendix A: Revision History............................................................................................................................................................. 227

Index ...................................................................................................................................................................................... ........... 233

The Microchip Web Site.................. ................................................................................................................................................... 237

Customer Change Notification Service .............................................................................................................................................. 237

Customer Support..............................................................................................................................................................................237

Reader Response..............................................................................................................................................................................238

Product Identification System............................................................................................................................................................. 239

C™).............................................................................................................................................. 139

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Most Current Data Sheet

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http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP20 1/202 devices . It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F Family Reference Manual sections.

This document co nta i ns dev ic e spec if i c in for m at ion fo r the dsPIC33FJ12GP201/202 Digital Signal Controller (DSC) devices. The dsPIC33F devices contain extensive Digital Signal Processor (DSP) functionality with a high-performance, 16-bit microcontroller (MCU) architecture.

Figure 1-1 shows a general block diagram of the core and peripheral modules in the dsPIC33FJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.

dsPIC33FJ12GP201/202

OSC1/CLKI

OSC2/CLKO

DD, VSS

Timing

Generation

MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

Precision

Reference

Band Gap

FRC/LPRC

Oscillators

Regulator

Voltage

VDDCORE/VCAP

IC1,2,7,8

I2C1

PORTA

Instruction

Decode and

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

PSV & Table Data Access

Control Block

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Address Latch

Program Memory

Data Latch

Address Bus

Literal Data

Data Latch

Address

Latch

X RAM

Y RAM

Y Data Bus

X Data Bus

DSP Engine

Divide Support

Control Signals to Various Blocks

ADC1

Timers

PORTB

Address Generator Units

1-3

CNx

UART1

OC/

PWM1-2

Remappable

Pins

Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features

on each device.

dsPIC33FJ12GP201/202

FIGURE 1-1: dsPIC33FJ12GP201/202 BLOCK DIAGRAM

dsPIC33FJ12GP201/202

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin Type

AN0-AN9 I Analog Analog input channels. CLKI

CLKO

OSC1 OSC2

SOSCI SOSCO

CN0-CN7 CN11-CN15 CN21-CN24 CN27 CN29-CN30

IC1-IC2 IC7-IC8

OCFA OC1-OC2

INT0 INT1 INT2

RA0-RA4 I/O ST PORTA is a bidirectional I/O port. RB0-RB15 I/O ST PORTB is a bidirectional I/O port. T1CK

T2CK T3CK

U1CTS U1RTS

U1RX U1TX

SCK1 SDI1 SDO1

SS1 SCL1

SDA1 ASCL1 ASDA1

TMS TCK TDI TDO

PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3

Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

I/O

I ST Change notification inputs.

I ST Capture inputs 1/2

I I I

I/O

I/O I/O

I/O I/O I/O

I I I

I/O

Buffer

Type

ST/CMOS—External clock source input. Always associated with OSC1 pin function.

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS

ST/CMOS—32.768 kHz low-power oscillator crystal input; CMOS otherwise.

ST—Compare Fault A input (for Compare Channels 1 and 2).

ST ST ST

ST ST

ST ST ST

ST ST ST ST ST ST

Oscillator cryst al outp ut. Conne cts to crys tal or reso nator in Cryst al Oscil lator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin func tion .

otherwise. Oscillator cryst al outp ut. Conne cts to crys tal or reso nator in Cryst al Oscil lator mode. Optionally functions as CLKO in RC and EC modes.

32.768 kHz low-power oscillator crystal output.

Can be software programmed for internal weak pull-ups on all inputs.

Capture inputs 7/8

Compare outputs 1 through 2. External interrupt 0.

External interrupt 1. External interrupt 2.

Timer1 external cl ock input. Timer2 external cl ock input. Timer3 external cl ock input.

UART1 clear to send.

—

UART1 ready to send. UART1 receive.

—

UART1 transmit. Synchronous serial clock input/output for SPI1.

SPI1 data in.

—

SPI1 data out. SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1.

JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin.

—

JTAG test data output pin. Data I/O pin for programming/debugging communication channel 1.

Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3.

Description

dsPIC33FJ12GP201/202

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Type

VDDCORE P — CPU lo gic filter capacitor connection. VSS P — Ground reference for logic and I/O pins. VREF+ I Analog Analog voltage reference (high) input.

REF- I Analog Analog voltage reference (low) input.

V AVDD P P Positive supply for analog modules. This pin must be connected at all times. MCLR AVSS P P Ground reference for analog modules.

DD P — Positive supply for peripheral logic and I/O pins.

V Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power

ST = Schmitt Trigger input with CMOS levels O = Output I = Input

I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device.

Buffer

Type

Description

dsPIC33FJ12GP201/202

2.0 CPU

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family Reference Manual, “Section 2. CPU” (DS70204), which is available from the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M by 24 bits of user program memory space. The actual amount of program memory implemen ted vari es by devic e. A single-cycle instruction prefetch mechanism is used to help maintain throu ghput and provides predic table execution. All inst ructions execute in a sin gle cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.

The dsPIC33FJ12GP201/202 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or ad dress offset register. The 16th wo rking register (W15) operates as a software Stack Pointer (SP) for interrupts and calls.

The dsPIC33FJ12GP201/202 instruction set has two classes of instructions: MCU and DSP. These two instruction classes are seamlessly integrated into a single CPU. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, dsPIC33FJ12GP201/202 devices are capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.

A block diagram of the CP U is shown in Figu re 2-1. The programmer’s model for the dsPIC33FJ12GP201/202 is shown in Figure2-2.

2.1 Data Addressing Overview

The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions

operate through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific.

Overhead-free circular buffers (Modulo Addressing mode) are supported in both X and Y address spaces. The Modulo Addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also support s Bit-Rev ers ed Add r essin g to greatly simplify input or output data reordering for radix-2 FFT algorithms.

The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space.

2.2 DSP Engine Overview

The DSP engine features a high-spee d 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is c apable of shif ting a 40-bit value up to 16 bits right or left, in a single cycle. The DSP instructions operate seamles sly with all other in st ruction s and have been desi gned for o ptimal re al-time p erformanc e. The MAC instruction and other associated instructions can concurrently fetch two dat a operands from mem ory while multiplyin g two W registe rs and accumu lating and optionally saturating the result in the same cycle. This instruction functionality requires that the RAM data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.

2.3 Special MCU Features

The dsPIC33FJ12GP201/202 features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP engine. T he mul tiplie r can pe rform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17 -bi t mult ip lier for 16-bi t by 16- bit mu lti pli cation not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations, such as (-1.0) x (-1.0).

The dsPIC33FJ12GP201/202 supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions.

Instruction

Decode &

Control

PCH PCL

Program Counter

16-bit ALU

Instruction Reg

PCU

16 x 16

W Register Array

ROM Latch

EA MUX

Interrupt

Controller

Stack

Control

Logic

Loop

Control

Logic

Data Latch

Address

Latch

Control Signals

to Various Blocks

Address Bus

Literal Data

To Peripheral Modules

Data Latch

Address

Latch

X RAM

Y RAM

Address Generator Units

Y Data Bus

X Data Bus

DSP Engine

Divide Support

PSV & Table Data Access

Control Block

Program Memory

Data Latch

Address Latch

dsPIC33FJ12GP201/202

FIGURE 2-1: dsPIC33FJ12GP201/202 CPU CORE BLOCK DIAGRAM

dsPIC33FJ12GP201/202

PC22

PC0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP Operand Registers

W1 W2 W3 W4 W5

W6 W7

W8 W9 W10 W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP Address Registers

AD39 AD0AD31

DSP Accumulators

ACCA ACCB

Program Space Visibility Page Address

OA OB SA SB

RCOUNT

REPEAT Loop Counter

DCOUNT

DO Loop Counter

DOSTART

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Point er Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

Core Configuration Register

Legend

CORCON

DA DC

RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End Address

DOEND

FIGURE 2-2: dsPIC33FJ12GP201/202 PROGRAMMER’S MODEL

dsPIC33FJ12GP201/202

2.4 CPU Control Registers

CPU control registers include:

• SR: CPU Status Register

• CORCON: CORE Control Register

REGISTER 2-1: SR: CPU STATUS REGISTER

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0

OA OB SA

(1)

bit 15 bit 8

(1)

OAB SAB DA DC

R/W-0

(2)

IPL<2:0>

R/W-0

(3)

(2)

R/W-0

(3)

R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Set only bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘ 0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit

1 = Accumul ator A overflowed 0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit

1 = Accumul ator B overflowed 0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator A is saturated or has been saturated at some time 0 = Accumulator A is not satura ted

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit

(1)

1 = Accumulator B is saturated or has been saturated at some time 0 = Accumulator B is not satura ted

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit

1 = Accumulators A or B have overflowed 0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

1 = Accumulators A or B are saturated or have been saturated at some time in the past 0 = Neither Accumulator A or B are saturated

This bit can be read or cleared (not set). Clearing this bit will clear SA and SB.

bit 9 DA: DO Loop Active bit

1 = DO loop in progress 0 = DO loop not in progress

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are con caten ated with the IPL<3 > bi t (CO RCON<3>) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

dsPIC33FJ12GP201/202

bit 8 DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte -sized data) o r 8th low-order bit (for w ord-sized data )

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress 0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative 0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred

bit

(2)

Note 1: This bit can be read or cleared (not set).

2: The IPL<2:0> bits are con caten ated with the IPL<3 > bi t (CO RCON<3>) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when IPL<3> = 1.

3: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

dsPIC33FJ12GP201/202

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0

— — —USEDT

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0

SATA SATB SATDW ACCSAT IPL3

bit 7 bit 0

Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Read as ‘0’ bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit

1 = Terminate executing DO loop at end of current loop iteration 0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits

111 = 7 DO loops active

•

001 = 1 DO loop active 000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit

1 = Accumulator A saturation enabled 0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit

1 = Accumulator B saturation enabled 0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit

1 = Data space write saturation enabled 0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit

1 = 9.31 saturation (super saturation) 0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space 0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit

1 = Biased (conventional) rounding enabled 0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit

1 = Integer mode enabled f or DSP multiply operations 0 = Fractio nal mode enab led for DSP multiply opera tions

(1)

(2)

(1)

(2)

DL<2:0>

PSV RND IF

Note 1: This bit will always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

dsPIC33FJ12GP201/202

2.5 Arithmetic Logic Unit (ALU)

The dsPIC33FJ12GP201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC S tatus bits op erate as Borrow bits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU ca n be written to the W re gister array or a data memory location.

The dsPIC3 3FJ 12GP2 01/ 202 CPU inco rp orat es h ardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division.

Refer to the dsPIC30F/33F Programmer’s Reference Manual (DS70157) for information on the SR bits affected by each instruction.

2.5.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier of the DSP engine, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes:

• 16-bit x 16-bit signed

• 16-bit x 16-bit unsigned

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

2.5.2 DIVIDER

The divide block support s 32-bit/16-bit and 16-b it/16-bit signed and unsigned integer divide op erat ion s w i th th e following data sizes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0

and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.

and Digit Borrow

2.6 DSP Engine

The DSP engine consists of a high-speed 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round and saturation logic).

The dsPIC33FJ12GP201/202 is a single-cycle instruction flow architecture; therefore, concurrent operation of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine resources can be used concurrently by th e sa m e instruction (e.g., ED, EDAC).

The DSP engine can also perform accumulator-to-accumulator operatio ns that require no add itional data. These instructions are ADD, SUB and NEG.

The DSP engine has options selected through bits in the CPU Core Control register (CORCON), as listed below:

• Fractional or integer DSP multiply (IF)

• Signed or unsigned DSP multiply (US)

• Conventional or convergent rounding (RND)

• Automatic saturation on/off for ACCA (SATA), ACCB (SATB) and writes to data memory (SATDW)

• Accumulator Saturation mode selection (ACCSAT)

A block diagram of the DSP engine is shown in Figure 2-3.

TABLE 2-1: DSP INSTRUCTIONS

SUMMARY

Instruction

CLR ED A = (x – y) EDAC A = A + (x – y) MAC A = A + (x * y) Yes MAC A = A + x MOVSAC No change in A Yes MPY A = x * y No MPY A = x MPY.N A = – x * y No MSC A = A – x * y Yes

Algebraic

Operation

A = 0

ACC Write

Back

Yes

No No

dsPIC33FJ12GP201/202

Zero Backfill

Sign-Extend

Barrel Shifter

40-bit Accumulator A 40-bit Accumulator B

Round

Logic

X Data Bus

To/From W Array

Adder

Saturate

Negate

Y Data Bus

Carry/Borrow Out

Carry/Borrow In

Multiplier/Scaler

17-bit

FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM

dsPIC33FJ12GP201/202

2.6.1 MULTIPLIER

The 17-bit x 17-bit multiplier is capable of signed or unsigned operati on and can mul tiplex i ts ou tput u sing a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value. The output of the 17-bit x 17-bit multiplier/ scale r is a 33-bit valu e that i s sign -ext ended to 40 bits. Integer data is inherently represented as a signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit.

• The range of an N-bit 2’s complement integer is

N-1

to 2

-2

• For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including ‘0’.

• For a 32-bit integer, the data range is

-2,147,483,648 (0x80000000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractional multiplication, the data is represented as a 2’s complement fraction, where the MSb is defined as a sign bit and the radix po int is impli ed to lie just af ter the sign bit (QX format). The range of an N-bit 2’s complement fract ion with this im plie d radix point i s -1.0 to (1 – 2 is -1.0 (0x8000) to 0. 999 969 482 (0x 7FF F) including ‘0’ and has a precision of 3.01518x10-5. In Fractional mode, the 16 x 16 multiply operation generates a 1.31 product that has a precision of 4.65661 x 10

The same multiplier is used to support the MCU multiply instructions, which include integer 16-bit signed, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte or word-sized operands. Byt e operan ds will direct a 16-bit result, and word operands will direct a 32-bit result to the specified register(s) in the W array.

– 1.

1-N

). For a 16-bit fraction, the Q15 data range

-10

2.6.2 DATA ACCUMULATORS AND

ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/subtracter wi th au tom ati c si gn ex ten si on lo gic . It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For t he ADD and LAC instructions, the da t a to be accumulated or loaded can be optionally scaled using the barrel shifter prior to accumulation.

2.6.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optional zero input into one si de, and either true or comp leme nt data into the other input.

• In the case of addition, the Carry/Borrow

active-high and the other input is true data (not complemented).

• In the case of subtraction, the Carry/Borrow

is active-low and the ot her inpu t is comple mente d.

The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register:

• Overflow from bit 39: this is a catastrophic

overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits 32 through 39: this is a

recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the Overflow Status bits described previously, and the SAT<A:B> (CORCON<7:6>) and ACCSAT (CORCON<4>) mode control bits to determine when, and to what value to saturate.

Six STATUS register bits have been provided to support saturation and overflow:

• OA: ACCA overflowed into guard bits

• OB: ACCB overflowed into guard bits

• SA: ACCA saturated (bit 31 overflow and

saturation)

ACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and

saturation)

ACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB

• SAB: Logical OR of SA and SB

The OA and OB bits are modified each time data passes through the adder/subtracter. When set, they indicate that the most recent operation has overflowed into the accumulator guard bits (bits 32 through 39). The OA and OB bits can also optionally generate an arithmetic warning trap when set and the corresponding Overfl ow Tra p Flag Enable bit s (OV A TE, OVBTE) in the INTCON1 register are set (refer to Section 6.0 “Interrupt Controller”). This allows the user application to t ake imme diate ac tion, for ex ampl e, to correct system gain.

input is

input

dsPIC33FJ12GP201/202

The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the u ser applic ation. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow, and therefore, in dic ate that a catastrophic overflow has occurred. If the COVTE bit i n the INTCON1 register is set, the SA and SB bits will generate an arithmetic warning trap when saturation is disabled.

The Overfl ow and Saturation Status bits c an optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programs can che ck one bi t in the ST A TUS register to determine if eith er accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which ty pically uses both accum ulators.

The device supports three Saturation and Overflow modes:

• Bit 39 Overflow and Saturation: When bit 39 overflow and saturation occurs, the saturation logic loads the maximally positive 9.31 (0x7FFFFFFFFF) or maximally negative 9.31 value (0x8000000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. This condition is referred to as ‘super saturation’ and provides protection against erroneous data or unexpected algorithm problems (such as gain calculations).

• Bit 31 Overflow and Saturation: When bit 31 overflow and saturation occurs, the saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target accumulator. The SA or SB bit is set and remains set until cleared by the user application. When this Saturation mode is in effect , the guard bit s are not used, so the OA, OB or OAB bits are never set.

• Bit 39 Catastrophic Overflow: The bit 39 Overflow Status bit from the adder is used to set the SA or SB bit, which remains set until cleared by the user applic ation. No sa turation operation is performed and the accumulator is allowed to overflow, destroying its sign. If the COVTE bit in the INTCON1 register is set, a catastrophic ov erfl ow ca n i nitiate a trap excep tio n.

2.6.2.2 Accumulator ‘Write Back’

The MAC class of instructions (with the exception of MPY, MPY.N, ED and EDAC) can optionally write a rounded ver sion of the hi gh word (bits 31 t hroug h 16) of the accumulator tha t is not targeted by the instructio n

into data spac e memory. The write is performed across the X bus into combined X and Y address space. The following addressing modes are supported:

• W13, Register Direct: The rounded contents of the non-target accumulator are written into W13 as a

1.15 fraction.

• [W13] + = 2, Register Indirect with Post-Increment: The rounded contents of the non-target accumulator are written into the address pointed to by W13 as a 1.15 fraction. W13 is then incremented by 2 (for a word write).

2.6.2.3 Round Logic

The round logic is a combinational block that performs a conventional (biased) or convergent (unbiased) round function durin g an ac cumulat or write (store). Th e Round mode is determined by the state of the RND bit in the CORCON register. It generates a 16-bit, 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, a truncated 1.15 dat a val ue is store d and the least significant word (lsw) is simply discarded.

Conventional rounding will zero-extend bit 15 of the accumulator and will add it to the ACCxH word (bits 16 through 31 of the accumulator).

• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x 8000 included), ACCxH is incremented.

• If ACCxL is between 0x0 000 and 0x 7FFF, ACCxH is left unchanged.

A consequence of this algorithm is that over a succession of random rou nding operations, th e value tends to be biased slightly positive.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except when ACCxL equals 0x8000. In this case, the Least Significant bit (bit 16 of the accumulator) of ACCxH is examined.

• If it is ‘1’, ACCxH is incremented.

• If it is ‘0’, ACCxH is not modified. Assuming that bit 16 is effectively random in nature, this scheme removes any rounding bias that may accumulate.

The SAC and SAC.R instructions store either a truncated (SAC), or rounded (SAC.R) version of the contents of the target accumulator to data memory via the X bus, subject to data saturation (see Section 2.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instruc tions, the data is always subject to rounding.

dsPIC33FJ12GP201/202

2.6.2.4 Data Sp ace Write Saturation

In addition to adder/subtrac ter saturation, writes to dat a space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 1 6-bit round adde r . These in puts are combined and used to select the appropriate 1.15 fractional value as output to write to data space memory.

If the SATDW bit in the CORCON register is set, data (after rounding or truncat ion ) is tested for overflow and adjusted accordingly:

• For input data greater than 0x007FFF, data written to memory is forced to the maximum positive

1.15 value, 0x7FFF.

• For input dat a les s tha n 0x FF8000, dat a w ritten to memory is forced to the maximum negative 1.15 value, 0x8000.

The Most Significant bit of the sourc e (bit 39) is used to determine the sign of the operand being tested.

If the SA TDW bi t in the CORCON regis ter is not set , the input data is always passed through unmodified under all conditions.

2.6.3 BARREL SHIFTER

The barrel shifter ca n perform up to 1 6-bit arithme tic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either of the two DSP accumulators or the X bus (to su pport multi-bit shif t s of register or memory data).

The shifter requires a signed binary value to determine both the magnitude (num ber of bits) and direction of the shift operation. A positive value shif ts the operand right. A negative v alue shi fts the opera nd left. A va lue of ‘ 0’ does not modify the operand.

The barrel shifter is 40 bits wide, thereby obtaining a 40-bit result fo r DSP shif t o peratio ns a nd a 16-bit re sult for MCU shift operations. Data from the X bus is presented to the barrel shifter between bit positions 16 and 31 for right shifts, and between bit positions 0 and 16 for left shifts.

dsPIC33FJ12GP201/202

NOTES:

dsPIC33FJ12GP201/202

Reset Address

0x000000

0x0000FE

0x000002

0x000100

Device Configuration

User Program Flash Memory

0x002000

0x001FFE

(4K instructions)

0x800000

0xF80000

Registers

0xF80017 0xF80018

DEVID (2)

0xFEFFFE 0xFF0000

0xFFFFFE

0xF7FFFE

Unimplemented

(Read ‘0’s)

GOTO

Instruction

0x000004

Reserved

0x7FFFFE

Reserved

0x000200

0x0001FE

0x000104

Alternate Vector Table

Reserved

Interrupt Vector Table

dsPIC33FJ12GP201/202

Configuration Memory Space

User Memory Space

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the dsPIC33FJ12GP201/202 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F Family

Reference Manual, “Section 4. Program Memory” (DS70202), which is available

from the Microchip website (www.microchip.com).

The dsPIC33FJ12GP201/202 architecture features separate program and data memory spaces and buses. This ar chitecture also allows th e direct ac cess of program memory from the data space during code execution.

3.1 Program Address Space

The program address memory space of the dsPIC33FJ12GP201/202 devices is 4M instructions. The space is addressable by a 24-bit value derived either fro m the 23- bit P C during program execution, or from table operation or data space remapping as described in Section 3.6 “Interfacing Program and Data Memory Spaces”.

User application acces s to the progr am mem ory sp ace is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space.

The memory map for the dsPIC33FJ12GP201/202 family of devices is shown in Figure3-1.

FIGURE 3-1: PROGRAM MEMORY FOR dsPIC33FJ1 2GP2 01/202 DEVICES

dsPIC33FJ12GP201/202

0816

PC Address

0x000000 0x000002 0x000004 0x000006

00000000 00000000

00000000

Program Memor y

‘Phantom’ Byte

(read as ‘0’)

least significant word (lsw)

most significant word (msw)

Instruction Width

0x000001 0x000003 0x000005 0x000007

msw

Address (lsw Address)

3.1.1 PROGRAM MEMORY ORGANIZATION

The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2).

Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible.

3.1.2 INTERRUPT AND TRAP VECTORS

All dsPIC33FJ12GP201/202 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on de vice Re set to th e actual start of code . A GOTO in st ruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.

dsPIC33FJ12GP201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the ma ny dev ic e interrupt sources to be handle d by separate In terrupt Serv ice Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt

Vector Table”.

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

dsPIC33FJ12GP201/202

3.2 Data Address S pace

The dsPIC33FJ12GP201/202 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory map is shown in Figure 3-3.

All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data mem ory space (that is, when EA<15> =

0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility area (see Section3.6.3 “Read-

ing Data From Program Memory Using Program Space Visibility”).

dsPIC33FJ12GP201/202 devices implement up to 30 Kbytes o f data memory. Should an EA poi nt to a location outside of this area, an all-zero word or byte will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte addressable, 16-bit-wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even ad dresses, whil e the Most Significant Bytes (MSBs) have odd addresses.

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

To maintain backward compatibility with PIC devices and improve data space memory usage efficiency, the dsPIC33FJ12GP201/202 instruction set supports both word and byte operations. As a consequence of byte a ccessibility, all effective address ca lculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations.

Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. D at a by te writ es only wri te to t he co rresponding side of the array or register that matches the byte address.

MCU

All word accesses m ust be al igned to an even a ddress. Misaligned word data fetches are not supported, so care must be ta ken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the instruction occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault.

All byte loads into any W register are loaded into the Least Significan t B yte . T he Most Significant By te is n ot modified.

A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.

3.2.3 SFR SPACE

The first 2 Kbytes of the near data space, from 0x000 0 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the dsPIC33FJ12GP201/202 c ore and p erip he ral m odu le s for controlling the operation of the device.

SFRs are distributed among the modules that they control, and are generall y grouped together by mod ule. Much of the SFR space contains unused addresses; these are read as ‘0’. A co mplete listing o f implemented SFRs, including their addresses, is shown in Table 3-1 through Table 3-21.

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.

3.2.4 NEAR DATA SPACE

The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the who le data s pace is ad dressable us ing MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer.

dsPIC33FJ12GP201/202

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSbMSb

MSB

Address

0x0001

0x07FF

0xFFFF

Optionally Mapped into Program Memory

0x0801

0x0800

0x0C00

2 Kbyte SFR Space

1 Kbyte SRAM Space

0x8001

0x8000

SFR Space

X Data RAM (X)

X Data

Unimplemented (X)

Y Data RAM (Y)

0x09FE 0x0A00

0x09FF 0x0A01

0x0BFF 0x0C01

0x1FFF

0x1FFFF

0x2001

0x2000

8 Kbyte Near Data Space

FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ12GP201/202 DEVICES WITH 1 KB RAM

dsPIC33FJ12GP201/202

3.2.5 X AND Y DATA SPACES

The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths. This feature allows certain instructions to concu rrently fe tch two w ords from RAM , thereby enabling efficient execution of DSP algorithms such as Finite Impulse Response (FIR) filtering and Fast Fourier Transform (FFT).

The X data space is used by all instructions and supports all addressing modes. X data space has separate read and write data buses. The X read data bus is the read data path for all instructions that view data space as combined X and Y address space. It is also the X dat a prefe tch p ath for the dual operand DSP instructions (MAC class).

The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide two concurrent data read paths.

Both the X and Y data spaces support Modulo Addressing mode for all instructions, subject to addressing mode restrictions. Bit-Reversed Addressing mode is only supported for writes to X data space.

All data memory writes, including in DSP instructions, view data space as combined X and Y address space. The boundary between the X and Y data spaces is device-dependent and is not user-programmable.

All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device.

TABLE 3-1: CPU CORE REGISTERS MAP

SFR Name

WREG0 0000 Working Re gister 0 WREG1 0002 Working Re gister 1 WREG2 0004 Working Re gister 2 WREG3 0006 Working Re gister 3 WREG4 0008 Working Re gister 4 WREG5 000A Working Re gis ter 5 WREG6 000C Wo rk ing R egi ster 6 WREG7 000E Working Re gis ter 7 WREG8 0010 Working Re gister 8 WREG9 0012 Working Re gister 9 WREG10 0014 Working Register 10 WREG11 0016 Working Register 11 WREG12 0018 Working Register 12 WREG13 001A Working Register 13 WREG14 001C Working Register 14 WREG15 001E Working Register 15 SPLIM 0020 Stack Pointer Limit Register ACCAL 0022 Accumulator A Low Word Register ACCAH 0024 Accumulator A Hi gh Word Re gister ACCAU 0026 Accumulato r A Upp er W ord Re giste r ACCBL 0028 Accumulator B Low Word Register ACCBH 002A Accumul ator B Hi gh Word Regi ster ACCBU 002C Accu mula tor B U pper W o rd Reg ister PCL 002E Program Counter Low Word Register PCH 0030 — — — — — — — — Program Co unte r Hi gh B yte Re gist er TBLP A G 0032 — — — — — — — — T able Page Address Pointer Register PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register RCOUNT 0036 Repeat Loop Counter Register DCOUNT 0038 DCOUNT<15:0> xxxx DOSTARTL 003A DOSTARTL<15:1> 0xxxx DOSTARTH 003C DOENDL 003E DOENDL<15:1> 0xxxx DOENDH 0040 SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C CORCON 0044 — — — US EDT DL<2:0> MODCON 0046 XMODEN YMODEN

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — — — — — — — —

— —

All

Resets

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx

DOSTARTH<5:0> 00xx

DOENDH 00xx

0000

SATA SATB SATDW ACCSA T IPL3 PSV RND IF

BWM<3:0> YWM<3:0> XWM<3:0> 0000

0020

dsPIC33FJ12GP201/202

+ 212 hidden pages

Datasheet dsPIC33FJ12GP201, dsPIC33FJ12GP202 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 DEVICE OVERVIEW

FIGURE 1-1: dsPIC33FJ12GP201/202 BLOCK DIAGRAM

TABLE 1-1: PINOUT I/O DESCRIPTIONS

2.0 CPU

2.1 Data Addressing Overview

2.2 DSP Engine Overview

2.3 Special MCU Features

FIGURE 2-1: dsPIC33FJ12GP201/202 CPU CORE BLOCK DIAGRAM

FIGURE 2-2: dsPIC33FJ12GP201/202 PROGRAMMER’S MODEL

2.4 CPU Control Registers

REGISTER 2-1: SR: CPU STATUS REGISTER

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

2.5 Arithmetic Logic Unit (ALU)

2.5.1 MULTIPLIER

2.5.2 DIVIDER

2.6 DSP Engine

FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM

2.6.1 MULTIPLIER

2.6.3 BARREL SHIFTER

3.0 MEMORY ORGANIZATION

3.1 Program Address Space

FIGURE 3-1: PROGRAM MEMORY FOR dsPIC33FJ1 2GP2 01/202 DEVICES

3.1.1 PROGRAM MEMORY ORGANIZATION

3.1.2 INTERRUPT AND TRAP VECTORS

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

3.2 Data Address S pace

3.2.1 DATA SPACE WIDTH

3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT

3.2.3 SFR SPACE

3.2.4 NEAR DATA SPACE

FIGURE 3-3: DATA MEMORY MAP FOR dsPIC33FJ12GP201/202 DEVICES WITH 1 KB RAM

3.2.5 X AND Y DATA SPACES

TABLE 3-1: CPU CORE REGISTERS MAP