Datasheet DM74164N, DM74164CW Datasheet (Fairchild Semiconductor)

© 2000 Fairchild Semiconductor Corporation DS006552 www.fairchildsemi.com

September 1986
Revised February 2000

DM74164 8-Bit Serial In/Parallel Out Shift Registers

DM74164
8-Bit Serial In/Parallel Out Shift Registers

General Description

These 8-bit shift registe rs feature gated serial inpu ts and
an asynchronous clear. A LOW logic level at either serial
input inhibits entry o f th e n ew d ata , an d r ese ts th e first flip­flop to the LOW level at the next clock pulse, thus providing
complete control over incoming data. A HIGH logic level on
either input enables the other input, which will then dete r­mine the state of the first flip-flo p. Data at the serial inputs
may be changed while th e cloc k is HIG H or LOW, but only
information meeting th e setup and ho ld time require ments
will be entered. Clocking occurs on the LOW-to-HIGH level
transition of the clock input. All inputs are diode-clamped to
minimize transmission-line effects.

Features

■ Gated (enable/disable) serial inputs

■ Fully buffered clock and serial inputs

■ Asynchronous clear

■ Typical clock frequency 36 MHz

■ Typical power dissipation 185 mW

Ordering Code:

Connection Diagram Function Table

H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don’t Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
Q

A0

, QB0, QH0 = The level of QA, QB, or QH, respectively, before the

indicated steady-state input conditions were established.

Q

An

, QGn = The level of QA or QG before the most recent ↑ transition of the

clock; indicates a one-bit shift.

Order Number Package Number Package Description

DM74164 N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs Outputs

Clear Clock A B

Q

AQB

…

Q

H

LXXXLL…L
HLXXQ

A0QB0

…Q

H0

H ↑ HHHQAn…Q

Gn

H ↑ LX L QAn…Q

Gn

H ↑ XL L QAn…Q

Gn

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DM74164

Logic Diagram

Timing Diagram

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DM74164

Absolute Maximum Ratings(Note 1)

Note 1: The “Absolute M aximu m R atin gs” are t hose valu es b eyo nd w hich

the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommend ed O peratin g Cond itions” t able w ill defin e the condition s
for actual device operation.

Recommended Operating Conditions

Note 2: TA = 25°C and VCC = 5V.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 3: All typicals are at VCC = 5V, TA = 25°C.
Note 4: Not more than one output should be shorted at a time.
Note 5: I

CC

is measured wi th all outpu ts OPEN, SERIAL in puts gro unded, the CLOCK inp ut at 2.4V, and a mo mentary g round, th en 4.5V, applied to the

CLEAR input.

Switching Characteristics

at VCC = 5V and TA = 25°C

Supply Voltage 7V
Input Voltage 5.5V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

V

CC

Supply Voltage 4.75 5 5.25 V

V

IH

HIGH Level Input Voltage 2 V

V

IL

LOW Level Input Voltage 0.8 V

I

OH

HIGH Level Output Current −0.4 mA

I

OL

LOW Level Output Current 8 mA

f

CLK

Clock Frequency (Note 2) 0 25 MHz

t

W

Pulse Width Clock 20

ns

(Note 2) Clear 20

t

SU

Data Setup Time (Note 2) 15 ns

t

H

Data Hold Time (Note 2) 5 ns

T

A

Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min

Typ

Max Units

(Note 3)

V

I

Input Clamp Voltage VCC = Min, II = −14 mA −1.5 V

V

OH

HIGH Level VCC = Min, IOH = Max

2.4 3.2 V

Output Voltage VIL = Max, VIH = Min

V

OL

LOW Level VCC = Min, IOL = Max

0.2 0.4 V

Output Voltage VIH = Min, VIL = Max

I

I

Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 mA

I

IH

HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA

I

IL

LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA

I

OS

Short Circuit Output Current VCC = Max (Note 4) −9 −27.5 mA

I

CC

Supply Current VCC = Max (Note 5) 37 54 mA

RL = 800Ω

Symbol Parameter From (Input)

CL = 15 pF CL = 50 pF

Units

To (Output) Min Max Min Max

f

MAX

Maximum Clock Frequency 25 MHz

t

PLH

Propagation Delay Time

Clock to Output 27 30 ns

LOW-to-HIGH Level Output

t

PHL

Propagation Delay Time

Clock to Output 32 37 ns

HIGH-to-LOW Level Output

t

PHL

Propagation Delay Time

Clear to Output 36 42 ns

HIGH-to-LOW Level Output

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DM74164 8-Bit Serial In/Parallel Out Shift Registers

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or syste ms are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical compon ent in any com ponen t of a life su pport
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

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