Datasheet CXP740096, CXP740056, CXP740010 Datasheet (Sony)

CMOS 8-bit Single Chip Microcomputer

Description

The CXP740056/740096/740010 is a CMOS 8-bit
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, capture timer/counter, remote control receive
circuit, PWM output, and the like besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O
port.

The CXP740056/740096/740010 also provides the
sleep/stop functions that enables lower power
consumption.

Features

• A wide instruction set (211 instructions) which covers various types of data.

— 16-bit arithmetic/multiplication and division/Boolean bit operation instructions

• Minimum instruction cycle 167ns at 24MHz operation (4.5 to 5.5V)

333ns at 12MHz operation (2.7 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)

• Incorporated ROM capacity 56K bytes (CXP740056)

96K bytes (CXP740096)
120K bytes (CXP740010)

• Incorporated RAM capacity 4096 bytes

• Peripheral functions

— A/D converter 8 bits, 8 channels, successive approximation method

(Conversion time 10.3µs at 24MHz)

— Serial interface Srart-stop synchronization (UART), 1 channel

Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels
8-bit clock syncronization (MSB/LSB first selectable), 1 channel

— Timer 8-bit timer 2 channels, 8-bit timer/counter 2 channels,

19-bit time-base timer, 16-bit capture timer/counter
32kHz timer/counter

— Remote control receive circuit Noise elimination circuit

8-bit pulse measuring counter, 6-stage FIFO

— PWM output 12 bits, 2 channels

• Interruption 22 factors, 15 vectors, multi-interruption possible

• Standby mode Sleep/stop

• Package 100-pin plastic QFP/LQFP

• Piggy/evaluation chip CXP740000

– 1 –

E98406-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP740056/740096/740010

100 pin QFP (Plastic) 100 pin LQFP (Plastic)

Structure

Silicon gate CMOS IC

– 2 –

CXP740056/740096/740010

PF0 to PF7

8

RAM

4096

BYTES

SPC 700αII

CPU CORE

INTERRUPT CONTROLLER

A/D CONVERTER

INT3

INT1
INT0

INT2

AN0 to AN11

12

RST

XTAL

V

DD

V

SS

EXTAL

AV

REF

AV

SS

RxD

TxD

ROM

56K/96K/120K

BYTES

2

CLOCK

GENERATOR/

SYSTEM CONTROL

PORT A

2

6

PA0 to PA7

PB0 to PB7

PC0 to PC7

PD0 to PD7

PE0 to PE1

PE2 to PE7

PG0 to PG7

PI1 to PI7

PORT B

PORT C

PORT D

PORT E

PORT F

PORT G

PORT I

PH0 to PH7

PORT H

UART RECEIVER

UART TRANSMITTER

UART BAUD RATE

GENERATOR

8

8

8

8

8

8

7

INT4

NMI

2

PWM0

12-BIT PWM GENERATOR 0

12-BIT PWM GENERATOR 1

PWM1

REMOCON IN

BUFFER

RAM

CS0

SI0

SO0

SCK0

SERIAL

INTERFACE

UNIT (CH1)

16-BIT CAPTURE

TIMER/COUNTER 4

TO2

8-BIT TIMER/COUNTER 0

8-BIT TIMER 1

EC0

CINT

EC2

SERIAL INTERFACE UNIT

(CH2)

SI2

SO2

SCK2

PJ0 to PJ7

PORT J

8

AV

DD

RMC

CS1

SI1

SO1

SCK1

PRESCALER/

TIME-BASE TIMER

BUFFER

RAM

TX

TEX

32kHz

TIMER-COUNTER

2
5

PORT K

PK3 to PK7

PK1 to PK2

FIFO

SERIAL

INTERFACE

UNIT (CH0)

TO0

8-BIT TIMER/COUNTER 2

8-BIT TIMER 3

EC1

TO1

2

ADJ

Block Diagram

– 3 –

CXP740056/740096/740010

Pin Assignment (Top View) 100-pin QFP package

2
3

4
5
6
7
8

9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70
69

68
67

63

64

65

66

61

62

71

72

73

74

81

82

83

84

75

76

77

78

88

87

86

85

79

89

90

100

99

98

97

96

95

94

91

92

93

1

80

PI6/SO1
PI7/SI1
PE0/INT0
PE1/INT2
PE2/PWM0
PE3/PWM1
PE4
PE5
PE6
PE7
PG0/TxD
PG1/RxD
PG2/EC0
PG3/EC1
PG4/EC2
PG5/INT3
PG6/INT4
PG7/CINT
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6
PF3/AN7
AV

DD

AVREF
AVSS
PF4/AN8

PC5
PC4
PC3
PC2

PC1
PC0

PB7/SI2

PB6/SO2

PB5/SCK2

PB4/TO2

PB3
PB2

PB1
PB0

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2

PJ1

PJ0

PD7
PD6
PD5
PD4
PD3
PD2
PD1

PD0

PC6

PC7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

NC

V

DD

V

SS

PK1/TX

PK2/TEX

PI1/RMC

PI2/NMI

PI3/TO0/ADJ

PI4/INT1/CS1

PI5/SCK1

PH7

PH6

PH5

PH4

PH3

PH2

PH1

PH0

PK7/TO1

RST

V

SS

XTAL

EXTAL

PK6/CS0

PK5/SI0

PK4/SO0

PK3/SCK0

PF7/AN11

PF6/AN10

PF5/AN9

Note) 1. NC (Pin 90) is left open.

2. VSS (Pins 41 and 88) are both connected to GND.

– 4 –

CXP740056/740096/740010

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22

23

24

25

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68
67

63

64

65

66

61

62

71

72

73

74

81

82

83

84

75

76

77

78

88

87

86

85

79

89

90

100

99

98

97

96

95

94

91

92

93

1

80

PI6/SO1

PI7/SI1

PE0/INT0

PE1/INT2
PE2/PWM0
PE3/PWM1
PE4
PE5
PE6
PE7
PG0/TxD
PG1/RxD
PG2/EC0
PG3/EC1
PG4/EC2
PG5/INT3
PG6/INT4
PG7/CINT
AN0
AN1
AN2
AN3
PF0/AN4
PF1/AN5
PF2/AN6

PC3
PC2
PC1
PC0

PB7/SI2

PB6/SO2

PB5/SCK2

PB4/TO2

PB3
PB2
PB1
PB0

PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1

PJ0
PD7
PD6
PD5

PC6

PC7

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

NC

V

DD

V

SS

PK1/TX

PK2/TEX

PI1/RMC

PI2/NMI

PI3/TO0/ADJ

PI4/INT1/CS1

PI5/SCK1

PH2

PH1

PH0

PK7/TO1

RST

V

SS

XTAL

EXTAL

PK6/CS0

PK5/SI0

PK4/SO0

PK3/SCK0

PF7/AN11

PF6/AN10

PF5/AN9

PH7

PH6

PH5

PH4

PH3

26

27

28

29

30

PD4
PD3

PD2

PD1

PD0

PF4/AN8

AV

SS

PF3/AN7
AV

DD

AVREF

PC4

PC5

Pin Assignment (Top View) 100-pin LQFP package

Note) 1. NC (Pin 88) is left open.

2. VSS (Pins 39 and 86) are both connected to GND.

– 5 –

CXP740056/740096/740010

(Port A)
8-bit I/O port. I/O can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the program in a unit of
single bits.
(8 pins)

(Port C)
8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up
resistor can be set through the program in a unit of single bits.
(8 pins)

(Port D)
8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sink
current. Incorporation of pull-up resistor can be set through the program in a
unit of single bits.
(8 pins)

(Port E)
8-bit port. Lower 2 bits are
for input; upper 6 bits are for
output.
(8 pins)

(Port F)
8-bit I/O port. PF4 to PF7
can be set in a unit of single
bits as standby release
inputs. I/O can be set in a
unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)

Analog inputs to A/D converter.
(8 pins)

Pin Description

Symbol

PA0 to PA7

PC0 to PC7

PD0 to PD7

PE0/INT0
PE1/INT1
PE2/PWM0
PE3/PWM1
PE4 to PE7

PF0/AN4

to

PF7/AN11

I/O

I/O

I/O

Input/Input
Input/Input
Output/Output
Output/Output
Output

I/O

I/O

Description

(Port B)
8-bit I/O port. I/O can be set
in a unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)

External interrupt inputs.
(2 pins)

12-bit PWM outputs.
(2 pins)

16-bit timer/counter rectangular wave output.
Serial clock I/O (CH2).
Serial data output (CH2).
Serial data input (CH2).

I/O
I/O/Output
I/O/I/O
I/O/Output
I/O/Input

PB0 to PB3
PB4/TO2
PB5/SCK2
PB6/SO2
PB7/SI2

– 6 –

CXP740056/740096/740010

(Port H)
8-bit I/O port. Operated as N-ch open drain output for medium voltage drive
(12V) and large current (12mA).
(8 pins)

(Port I)
7-bit I/O port. I/O can be set
in a unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(7 pins)

(Port J)
8-bit I/O port. I/O can be set in a unit of single bits.
Standby release input can be set in a unit of single bits.
Incorporation of pull-up resistor can be set through the program in a unit of
single bits.
(8 pins)

(Port K)
7-bit port. lower 2 bits are for
input; upper 5 bits are for I/O.
I/O can be set in a unit of
single bits.
For PK3 to PK7, incorporation
of pull-up resistor can be set
through the program in a unit
of single bits.
(7 pins)

UART transmission data output.
UART reception data input.
External event input for 8-bit timer/counter 0.
External event input for 8-bit timer/counter 2.
External event input for 16-bit timer/counter.

External capture input to 16-bit timer/counter.

Remote control receiver circuit input.
Non-maskable interrupt input.
Output for the 8-bit timer/counter 1

rectanguler waves and 32-kHz oscillation
frequency demultiplication.

Serial clock I/O (CH1).
Serial data output (CH1).
Serial data input (CH1).

Crystal connectors for 32-kHz timer/counter
clock oscillation circuit.
For usage as event count, connect clock
oscillation source to TEX, and leave TX
open.

Serial clock I/O (CH0).
Serial data output (CH0).
Serial data input (CH0).
Chip select input for serial inteface (CH0).
8-bit timer/counter 3 rectangular wave output.

Symbol
PG0/TxD
PG1/RxD
PG2/EC0
PG3/EC1
PG4/EC2
PG5/INT3
PG6/INT4
PG7/CINT

PH0 to PH7

PI1/RMC
PI2/NMI

PI3/TO0/
ADJ

PI4/INT1/
CS1

PI5/SCK1
PI6/SO1
PI7/SI1

PJ0 to PJ7

PK3/SCK0
PK4/SO0
PK5/SI0
PK6/CS0
PK7/TO1

I/O/Output
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input
I/O/Input

Output

I/O/Input
I/O/Input

I/O/Output/
Output

I/O/Input/
Input

I/O/I/O
I/O/Output
I/O/Input

I/O

I/O/I/O
I/O/Output
I/O/Input
I/O/Input
I/O/Output

I/O

Description

Chip select input for serial
interface (CH1).

External
interrupt input.

(Port G)
8-bit I/O port. I/O can be set
in a unit of single bits.
Incorporation of pull-up
resistor can be set through
the program in a unit of
single bits.
(8 pins)

PK1/TX

PK2/TEX

Input

Input/Input

External interrupt inputs.
(2 pins)

– 7 –

CXP740056/740096/740010

Analog inputs to A/D converter.
(4 pins)

Connects a crystal for system clock oscillation. When a clock is supplied
externally, input it to EXTAL pin and input a reversed phase clock to XTAL
pin.

System reset; active at Low level.
Not connected.

Leave this pin open for normal operation.
Positive power supply of A/D converter.
Reference voltage input of A/D converter.
GND of A/D converter.
Positive power supply.
GND. Connect both VSS pins to GND.

Symbol

I/O

Description

EXTAL
XTAL

Input

AN0 to AN3

RST
NC
AVDD

AVREF
AVSS
VDD
VSS

Input

Input

Input

– 8 –

CXP740056/740096/740010

18 pins

Hi-Z

Hi-Z

After a reset

PA0 to PA7

PB0

PB2

PC0 to PC7

PB4/TO2
PI3/TO0/ADJ
PK7/TO1

3 pins

Internal data bus

RD (Ports A, B, C)

IP

A

Ports A, B, C data

“0” after a reset

∗

Ports A, B, C direction

Pull-up resistor

“0” after a reset

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

I/O Circuit Format for Pins

Pin

Circuit format

2 pins

Hi-Z

PB1
PB3

Internal data bus

RD (Port B)

IP

A

Port B data

“0” after a reset

∗

Port B direction

Pull-up resistor

“0” after a reset

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Schmitt input

Internal
data bus

RD (Ports B, I, K)

IP

Ports I, K function

select

“0” after a reset

∗

“0” after a reset

Pull-up resistor

TO0/ADJ, TO1

“0” after a reset

∗

Pull-up transistors

approx. 100kΩ (V

DD = 4.5 to 5.5V)

approx. 150kΩ (VDD = 2.7 to 3.3V)

Ports I, K data

Ports I, K direction

Port A
Port B
Port C

Port B

Port I
Port K

– 9 –

CXP740056/740096/740010

3 pins

Hi-Z

Hi-Z

After a reset

PB5/SCK2
PI5/SCK1
PK3/SCK0

PB6/SO2
PG0/TxD
PI6/SO1
PK4/SO0

4 pins

Internal
data bus

RD (Ports B, I, K)

IP

Ports B, I, K direction

“0” after a reset

∗

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Ports B, I, K data

“0” after a reset

Ports B, I, K function
select

SCK2, SCK1, SCK0

Output enable

Output buffer
capability

“0” after a reset

Pull-up resistor

“0” after a reset

Schmitt input

SCK2, SCK1, SCK0

Pin

Circuit format

A

Internal
data bus

RD (Ports B, G, I, K)

IP

Ports B, G, I, K
direction

“0” after a reset

∗

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Ports B, G, I, K data

“0” after a reset

Ports B, G, I, K
function select

TO2, SO2, TxD, SO1, SO0

Output enable

Output buffer
capability

“0” after a reset

Pull-up resistor
“0” after a reset

Port B
Port I
Port K

Port B
Port G
Port I
Port K

AA

– 10 –

CXP740056/740096/740010

14 pins

Hi-Z

Hi-Z

After a reset

PB7/SI2

PG1/RxD

PG2/EC0

PG3/EC1

PG4/EC2

PG5/INT3

PG6/INT4

PG7/CINT

PI1/RMC

PI2/NMI

PI4/INT1/CS1

PI7/SI1

PK5/SI0

PK6/CS0

PE0/INT0
PE1/INT2

2 pins

Internal data bus

RD (Ports B, G, I, K)

Ports B, G, I, K direction

IP

Ports B, G, I, K data

Pull-up resistor
“0” after a reset

“0” after a reset

∗

Schmitt input

SI2, RxD, EC0, EC1, EC2, INT3, INT4, CINT,
RMC, MNI, INT1/CS1, SI1, SI0, CS0

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Pin

Circuit format

8 pins

Hi-Z

PD0 to PD7

Internal data bus

RD (Port D)

Port D direction

Port D data

Pull-up resistor

“0” after a reset

∗

2

∗

1

∗

1

Large current

12mA (VDD = 4.5 to 5.5V)

4.5mA (VDD = 2.7 to 3.3V)

∗

2

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

IP

IP

Schmitt input

RD (Port E)

Internal data bus

INT0, INT2

Port B
Port G
Port I
Port K

Port D

Port E

– 11 –

CXP740056/740096/740010

2 pins

Hi-Z

After a reset

PE2/PWM0

PE3/PWM1

Port E function select

“0” after a reset

PWM0, PWM1

Port E data

Internal data bus

RD (Port E)

Hi-Z by writing to Port E data register or Port E
function select register → Output active

2 pins

Hi-Z

PE4
PE5

Hi-Z by writing to Port E data
register → Output active

Internal data bus

RD (Port E)

Port E data

1 pin

High level

PE6

Internal data bus

RD (Port E)

Port E data

“1” after a reset

1 pin

PE7

Internal data bus

RD (Port E)

∗

∗

Pull-up transistors

approx. 150kΩ (VDD = 4.5 to 5.5V)
approx. 200kΩ (VDD = 2.7 to 3.3V)

Internal reset signal

Port E data

“1” after a reset

4 pins

Hi-Z

AN0 to AN3

IP

A/D converter

Input multiplexer

Pin

Circuit format

"H" level
"H"level at
ON
resistance
of pull-up
transistor
during a
reset.

)

Port E

Port E

Port E

Port E

)

– 12 –

CXP740056/740096/740010

4 pins

Hi-Z

Hi-Z

After a reset

PF0/AN4

to

PF3/AN7

PF4/AN8

to

PF7/AN11

4 pins

Internal data bus

RD (Port F)

Port F direction

IP

Port F data

Pull-up resistor

Port F
function select

“0” after a reset

“0” after a reset

“0” after a reset

Input multiplexer

A/D converter

∗

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Pin

Circuit format

Internal data bus

RD (Port F)

Port F direction

IP

Port F data

Pull-up resistor

Port F
function select

“0” after a reset

“0” after a reset

“0” after a reset

Input multiplexer

A/D converter

∗

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Polarity select

“0” after a reset

A

Edge detection

Standby release

Port F

Port F

– 13 –

CXP740056/740096/740010

8 pins

Hi-Z

Hi-Z

After a reset

PH0 to PH7

PJ0 to PJ7

8 pins

Internal data bus

RD (Port H)

Port H data

“1” after a reset

∗

∗

High tension proof 12V
Large current

12mA (VDD = 4.5 to 5.5V)

4.5mA (VDD = 2.7 to 3.3V)

Pin

Circuit format

Internal data bus

RD (PortJ)

Port J direction

IP

Port J data

Pull-up resistor

“0” after a reset

“0” after a reset

∗

∗

Pull-up transistors

approx. 100kΩ (VDD = 4.5 to 5.5V)
approx. 150kΩ (VDD = 2.7 to 3.3V)

Polarity select

“0” after a reset

Edge detection

Standby release

Oscillation
stop port
input

PK1/TX
PK2/TEX

2 pins

IP

IP

TEX oscillation circuit control

RD (Port K)

Schmitt input

Clock input

Internal
data bus

Internal
data bus

“1” after a reset

PK2/TEX

PK1/TX

RD (Port K)

Port H

Port J

Port K

– 14 –

CXP740056/740096/740010

2 pins

Oscillation

After a reset

EXTAL
XTAL

IP

EXTAL

XTAL

• Diagram shows circuit configuration
during oscillation.

• When program stops the oscillation,
the feedback registor disconnects,
and XTAL is driven at "H" level.

IP

1 pin

"L" level
(during a
reset)

RST

Schmitt input

Pull-up resistor

Mask option

OP

IP

Pin

Circuit format

– 15 –

CXP740056/740096/740010

Supply voltage

Input voltagte
Output voltage
High level output current
High level total output current

Low level output current

Low level total output current
Operating temperature
Storage temperature

Allowable power dissipation

∗1

AVDD and VDD must be set to the same voltage.

∗2

VIN and VOUT must not exceed VDD + 0.3V.

∗3

The large current output pins are Port D and H (PD, PH).

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended operating conditions. Exceeding these conditions may adversely
affect the reliability of the LSI.

VDD
AVDD
AVSS
AVREF
VIN
VOUT
IOH
∑IOH

IOL
IOLC

∑IOL
Topr
Tstg

PD

–0.3 to +7.0

AVSS to +7.0

∗1

–0.3 to +0.3

AVSS to +7.0

–0.3 to +7.0

∗2

–0.3 to +7.0

∗2

–5

–50

15
20

100

–20 to +75

–55 to +150

600
380

V
V
V
V
V

V
mA
mA

mA
mA

mA

°C
°C

mW

Output (value per pin)
Total for all output pins
All pins excluding large current

outputs (value per pin)
Large current outputs (value per pin)

∗3

Total for all output pins

QFP package
LQFP package

Item Symbol Rating Unit Remarks

Absolute Maximum Ratings (Vss = 0V reference)

– 16 –

CXP740056/740096/740010

High level input
voltage

Low level input
voltage

Operating temperature

Supply voltage

Analog voltage

5.5

5.5

5.5
VDD
VDD
VDD

VDD + 0.3
VDD + 0.2

0.3VDD

0.2VDD

0.2VDD

0.4

0.2
+75

V
V
V
V
V
V
V
V
V
V

°C

V
V

V
V
V

Item Symbol Min.

4.5

2.7

5.5

5.5

Max. Unit Remarks

fc = 24MHz or less

Guaranteed operation
range for 1/2 and 1/4
frequency dividing clock.

fc = 12MHz or less

V

2.7

5.5
Guaranteed operation range for TEX

2.7

2.5

2.7

0.7VDD

0.8VDD

0.8VDD
VDD – 0.4
VDD – 0.2

0
0

0
–0.3
–0.3

–20

VIH

VIHS

VIHEX

VIL

VILS

VILEX

Topr

Guaranteed operation range for 1/16
frequency dividing clock or sleep mode

Guaranteed data hold operation range
during stop mode

∗1
∗2, ∗6
∗2, ∗7

Hysteresis input

∗3

EXTAL pin

∗4, ∗6

, TEX pin

∗5, ∗6

EXTAL pin

∗4, ∗7

, TEX pin

∗5, ∗7
∗2, ∗6
∗2, ∗7

Hysteresis input

∗

3

EXTAL pin

∗4, ∗6

, TEX pin

∗5, ∗6
EXTAL pin

∗4, ∗7

, TEX pin

∗5, ∗7

VDD

AVDD

∗1

AVDD and VDD must be set to the same voltage.

∗2

Normal input port (PA, PB0, PB2, PB4, PB6, PC, PD, PF, PG0, PI3, PI6, PJ, PK1, PK2, PK4, PK7)

∗3

RST, PB1, PB3, PB5/SCK2, PB7/SI2, PE0/INT0, PE1/INT2, PG1/RxD, PG2/EC0, PG3/EC1, PG4/EC2,
PG5/INT3, PG6/INT4, PG7/CINT, PI1/RMC, PI2/NMI, PI4/INT1/CS1, PI5/SCK1, PI7/SI1, PK3/SCK0,
PK5/SI0, PK6/CS0

∗4

Specifies only when the external clock is input.

∗5

Specifies only when the external event count is input.

∗6

This case applies to the range of 4.5 to 5.5V supply voltage (VDD).

∗7

This case applies to the range of 2.7 to 5.5V supply voltage (VDD).

Recommended Operating Conditions (Vss = 0V reference)

– 17 –

CXP740056/740096/740010

VDD = 4.5V, IOL = 12.0mA
VDD = 5.5V, VIH = 5.5V
VDD = 5.5V, VIL = 0.4V
VDD = 5.5V, VIL = 5.5V
VDD = 5.5V, VIL = 0.4V

VDD = 5.5V, VIL = 0.4V

VDD = 4.5V, VIL = 4.0V

VDD = 5.5V
VI = 0, 5.5V

VDD = 5.5V
VOH = 12V

High level
output voltage

Low level
output voltage

Input current

I/O leakage
current

0.5

–0.5

0.1
–0.1
–1.5

–2.78

V

V

V

V

V
µA
µA
µA
µA
µA
µA
µA

µA

µA

PD, PH

PA to PD,
PE2 to PE7,
PF to PG,
PI to PJ,
PK3 to PK7

PB5, PB6∗1,
PG0∗1,
PI5, PI6∗1,
PK3, PK4

∗1

PA to PD,
PE2 to PE7,
PF to PG,
PI to PJ,
PK3 to PK7

EXTAL

TEX

RST

∗2

PA to PD∗3,
PF to PG∗3,
PI to PK

∗3

Item Symbol Pins Conditions Min.

PA to PD∗3,
PF to PG∗3,
PI to PK∗3,
PE,
AN0 to AN3
RST

∗2

PH

Typ.

1.5
40

–40

10

–10

–400

–45

±10

50

Max. Unit

DC Characteristics (VDD = 4.5 to 5.5V)

Electrical Characteristics

(Ta = –20 to +75°C, VSS = 0V reference)

VOH

VOL

IIHE
IILE
IIHT
IILT
IILR

IIL

IIZ

Open drain
output leakage
current
(N-ch Tr off
state)

LLOH

VDD = 4.5V, IOH = –1.0mA

VDD = 4.5V, IOH = –1.2mA

VDD = 4.5V, IOH = –0.5mA

4.0

3.5

4.0

3.5

0.4

0.6

V

VVDD = 4.5V, IOH = –2.4mA

VDD = 4.5V, IOL = 1.8mA

VDD = 4.5V, IOL = 3.6mA

– 18 –

CXP740056/740096/740010

Supply
current

∗4

Item Symbol Pins Conditions Min.

27

47

mA

mA

µA

µA

30

1.0

5.0

75

µA

12

40

10

PA to PD,
PE0 to PE1,
PF to PG,
PI to PK,
AN0 to AN3,
EXTAL,
RST

Clock 1MHz
0V for all pins excluding measured
pins

VDD = 5V ± 0.5V
Sleep mode

VDD = 5V ± 0.5V

24MHz crystal oscillation
(C1 = C2 = 15pF)

VDD

IDD1

IDDS1

IDD2

IDDS2

IDDS3

CIN

Typ. Max. Unit

∗1

This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and
Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0= "1, 1, 1, 1, 1") are ON.

∗2

RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current
when no resistor is selected.

∗3

PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and
specify the leakage current when no resistor is selected.

∗4

When all pins are open.

VDD = 3V ± 0.3V
Sleep mode

VDD = 3V ± 0.3V

32kHz crystal oscillation
(C1 = C2 = 47pF)

Stop mode
(Termination of EXTAL and TEX pins
crystal oscillation)

VDD = 5V ± 0.5V

Input
capacity

pF2010

– 19 –

CXP740056/740096/740010

DC Characteristics (VDD = 2.7 to 3.3V)

Electrical Characteristics

(Ta = –20 to +75°C, VSS = 0V reference)

VDD = 2.7V, IOL = 4.5mA
VDD = 3.3V, VIH = 3.3V
VDD = 3.3V, VIL = 0.3V
VDD = 3.3V, VIL = 3.3V
VDD = 3.3V, VIL = 0.4V

VDD = 3.3V, VIL = 0.3V

VDD = 3.3V, VIL = 2.7V

VDD = 3.3V
VI = 0, 3.3V

VDD = 3.3V
VOH = 12V

High level
output voltage

Low level
output voltage

Input current

I/O leakage
current

0.3

–0.3

0.1
–0.1
–0.9

–1.0

V

V

V

V

V
µA
µA
µA
µA
µA
µA
µA

µA

µA

PD, PH

PA to PD,
PE2 to PE7,
PF to PG,
PI to PJ,
PK3 to PK7

PB5, PB6∗1,
PG0∗1,
PI5, PI6∗1,
PK3, PK4

∗1

PA to PD,
PE2 to PE7,
PF to PG,
PI to PJ,
PK3 to PK7

EXTAL

TEX

RST

∗2

PA to PD∗3,
PF to PG∗3,
PI to PK

∗3

Item Symbol Pins Conditions Min.

PA to PD∗3,
PF to PG∗3,
PI to PK∗3,
PE,
AN0 to AN3
RST

∗2

PH

Typ.

0.9
20

–20

10

–10

–200

–20

±10

50

Max. Unit

VOH

VOL

IIHE
IILE
IIHT
IILT
IILR

IIL

IIZ

Open drain
output leakage
current
(N-ch Tr off
state)

LLOH

VDD = 2.7V, IOH = –0.24mA

VDD = 2.7V, IOH = –0.45mA

VDD = 2.7V, IOH = –0.12mA 2.5

2.1

2.5

2.1

0.25

0.4

V

VVDD = 2.7V, IOH = –0.9mA

VDD = 2.7V, IOL = 1.0mA

VDD = 2.7V, IOL = 1.4mA

– 20 –

CXP740056/740096/740010

Supply
current

∗4

Item Symbol Pins Conditions Min.

8

20

mA

mA

µA

0.3

1.5

10

PA to PD,
PE0 to PE1,
PF to PG,
PI to PK,
AN0 to AN3,
EXTAL,
RST

Clock 1MHz
0V for all pins excluding measured
pins

VDD = 3.0V ± 0.3V

∗3

Sleep mode

VDD = 3.0V ± 0.3V

12MHz crystal oscillation
(C1 = C2 = 15pF)

VDD

IDDS1

IDD1

IDDS3

CIN

Typ. Max. Unit

Stop mode
(Termination of EXTAL and TEX pins
crystal oscillation)

VDD = 3.0V ± 0.3V

Input
capacity

pF2010

∗1

This case applies that Port B buffer capability switching register (BUFB: 010F4h, bits 6 and 5 = "1, 1") and
Ports G/I/K buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4, 3 and 0 = "1, 1, 1, 1, 1") are ON.

∗2

RST pin specifies the input current when the pull-up resistor is selected, and specifies the leakage current
when no resistor is selected.

∗3

PA to PD, PF to PG and PI to PK pins specify the input current when the pull-up resistor is selected, and
specify the leakage current when no resistor is selected.

∗4

When all pins are open.

CXP740056/740096/740010

– 21 –

∗1

tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock

control register (CLC: 000FEh).

tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”)

EXTAL

t

XH tXLtCF tCR

0.4V (VDD = 4.5 to 5.5V)

V

DD – 0.4V (VDD = 4.5 to 5.5V)

1/fc

V

DD – 0.3V

0.3V

Crystal oscillation
Ceramic oscillation

EXTAL

XTAL

External clock

EXTAL

XTAL

74HC04

C

1 C2

32kHz clock applied condetions
crystal oscillation

TEX

TX

C

1 C2

TEX
EC0
EC1
EC2

t

EH tELtEF tER

0.2VDD

0.8VDD

tTH tTLtTF tTR

AC Characteristics
(1) Clock timing

System clock frequency

System clock input pulse
width

System clock input
rise time, fall time

Event count input clock
pulse width

Event count input clock
rise time, fall time

System clock frequency

Event count input clock
pulse width

Event count input clock
rise time, fall time

fC

tXL,
tXH

tCR,
tCF

tEH,
tEL

tER,
tEF

fC

tTL,
tTH

tTR,
tTF

XTAL
EXTAL

EXTAL

EXTAL

EC

EC

TEX
TX

TEX

TEX

MHz

ns

ns

ns

ms

kHz

µs

ms

Item Symbol Pin Conditions Min. Unit

Fig. 1, Fig. 2

Fig. 1, Fig. 2
External clock drive

Fig. 1, Fig. 2
External clock drive

Fig. 3

Fig. 3
VDD = 2.7 to 5.5V

Fig. 2 (32kHz clock applied
condition)

Fig. 3

Fig. 3

1
1

28

37.5

tsys + 50

∗1

10

Typ.

32.768

Max.

24
12

200

20

20

(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)

Fig. 2. Clock applied conditions

Fig. 1. Clock timing

Fig. 3. Event count clock timing

VDD = 4.5 to 5.5V

VDD = 4.5 to 5.5V

– 22 –

CXP740056/740096/740010

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)

Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1

and SO1 for CH1, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
Note 4) This case applies that Port I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5, 4

and 3 = "0, 0, 0, 0") is OFF.

(2) Serial transfer (CH0, CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

CS↓ → SCK
delay time

CS↑ → SCK
floating delay time

CS↓ → SO delay time
CS↑ → SO floating

delay time
CS High level width

tsys + 200

2tsys + 200

8000/fc

tsys + 100

4000/fc – 50

–tsys + 100

200

2tsys + 200

100

1.5tsys + 200

1.5tsys + 200

1.5tsys + 200

1.5tsys + 200

2tsys + 200

100

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Item Symbol Pin

Conditions

Min. Max. Unit

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

SCK cycle time

SCK High and Low
level width

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

SCK↓ → SO
delay time

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0
SCK1

SCK0
SCK1

SO0
SO1

SO0
SO1

CS0
CS1

SCK0
SCK1

SCK0
SCK1

SI0
SI1

SI0
SI1

SO0
SO1

– 23 –

CXP740056/740096/740010

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh)

upper 2 bits (CPU clock selection).

tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)

Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1

and SO1 for CH1, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF.
Note 4) This case applies that Port G/I/K output buffer capability switching register (BUFG: 010F5h, bits 6, 5,

4 and 3 = "1, 1, 1, 1") is ON.

Serial transfer (CH0, CH1) (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)

CS↓ → SCK
delay time

CS↑ → SCK
floating delay time

CS↓ → SO delay time
CS↑ → SO floating

delay time
CS High level width

tsys + 200

2tsys + 200

8000/fc

tsys + 100

4000/fc – 100

–tsys + 100

200

2tsys + 200

100

1.5tsys + 250

1.5tsys + 250

1.5tsys + 250

1.5tsys + 250

2tsys + 250

125

ns

ns

ns

ns

ns
ns

ns
ns
ns
ns
ns
ns
ns
ns
ns

Item Symbol Pin Conditions Min. Max. Unit

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode
(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode
Input mode

Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

SCK cycle time

SCK High and Low
level widths

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

SCK↓ → SO
delay time

tDCSK

tDCSKF

tDCSO

tDCSOF

tWHCS

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK0
SCK1

SCK0
SCK1

SO0
SO1

SO0
SO1

CS0
CS1

SCK0
SCK1

SCK0
SCK1

SI0
SI1

SI0
SI1

SO0
SO1

– 24 –

CXP740056/740096/740010

CS0
CS1

SCK0
SCK1

0.2V

DD

0.8VDD

tWHCS

tDCSK tDCSKF

0.8VDD

0.2VDD

0.8VDD

tKCY

tKL tKH

0.8VDD

0.2VDD

SI0
SI1

t

SIK

tKSI

Input data

t

DCSO tKSO tDCSOF

Output data

0.8V

DD

0.2VDD

SO0
SO1

Fig. 4. Serial transfer CH0, CH1 timing

– 25 –

CXP740056/740096/740010

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Min. Max. UnitConditions

SCK cycle time

SCK High and Low
level widths

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

SCK↓ → SO delay time

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK2

SCK2

SI2

SI2

SO2

Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

1000

8000/fc

400

4000/fc – 50

100
200
200
100

200
100

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)

Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF+1TTL.
Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 =

“0, 0”) is OFF.

Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V reference)

Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 000FEh) upper

2 bits (CPU clock selection).

tsys [ns] = 2000/fc (upper 2 bits = “00”), 4000/fc (upper 2 bits = “01”), 16000/fc (upper 2 bits = “11”)

Note 2) SCK, SI and SO represent SCK2, SI2 and SO2 for CH2, respectively.
Note 3) The load of SCK2 output mode and SO2 output delay time is 50pF.
Note 4) This case applies that Port B output buffer capability switching register (BUFB: 010F4h, bits 6 and 5 =

“1, 1”) is ON.

Item Symbol Pin Min. Max. UnitConditions

SCK cycle time

SCK High and Low
level widths

SI input setup time
(for SCK↑)

SI input hold time
(for SCK↑)

SCK↓ → SO delay time

tKCY

tKH
tKL

tSIK

tKSI

tKSO

SCK2

SCK2

SI2

SI2

SO2

Input mode
Output mode
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode

1000

8000/fc

400

4000/fc – 100

100
200
200
100

250
125

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

– 26 –

CXP740056/740096/740010

Fig. 5. Serial transfer CH2 timing

tKCY

tKL tKH

0.2VDD

0.8VDD

tSIK tKSI

tKSO

Input data

Output data

0.2V

DD

0.8VDD

0.2VDD

0.8VDD

SCK2

SI2

SO2

– 27 –

CXP740056/740096/740010

Analog input

Linearity error

V

FTVZT

00h

01h

FEh

FFh

Digital conversion value

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference)

Fig. 6. Definition of A/D converter terms

∗1

VZT:Value at which the digital conversion value changes

from 00h to 01h and vice versa.

∗2

VFT:Value at which the digital conversion value changes

from FEh to FFh and vice versa.

∗3

fADC indicates the below values due to the contents of bit
6 (CKS) of the A/D control register (ADC: 000F9h).

PS3 selected fADC = fc/4
PS4 selected fADC = fc/8

However, when PS3 is selected, fc is 12MHz or less.

∗4

Sub clock operated tCONV = 34/fTEX

tSAMP = 10/fTEX

Resolution
Linearity errror
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

AVREF current

tCONV
tSAMP

VREF
VIAN
IREF

IREFS

AVREF
AN0 to AN11

AVREF

VDD = AVDD = 4.5 to 5.5V

Operation mode
Sleep mode

Stop mode
32kHz operation mode

Item Symbol Pin Conditions Min. Typ. Max. Unit

Bits
LSB
LSB

µs
µs

V
V

mA

µA

8
±2
±3

1.0

10

0.6

31/fADC

∗3, ∗4

10/fADC

∗3, ∗4

AVDD – 0.5

0

Ta = 25°C
VDD = AVDD = AVREF = 5.0V
VSS = AVSS = 0V

Resolution
Linearity errror
Absolute error
Conversion time
Sampling time
Reference input voltage
Analog input voltage

AVREF current

tCONV
tSAMP

VREF
VIAN
IREF

IREFS

AVREF
AN0 to AN11

AVREF

VDD = AVDD = 2.7 to 3.3V

Operation mode
Sleep mode

Stop mode
32kHz operation mode

Item Symbol Pin Conditions Min. Typ. Max. Unit

Bits
LSB
LSB

µs
µs

V
V

mA

µA

(Ta = –20 to +75°C, VDD = AVDD = 2.7 to 3.3V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference)

8
±2
±3

0.7

10

0.4

31/fADC

∗3, ∗4

10/fADC

∗3, ∗4

AVDD – 0.3

0

Ta = 25°C
VDD = AVDD = AVREF = 3.0V
VSS = AVSS = 0V

– 28 –

CXP740056/740096/740010

0.2VDD

0.8VDD

tIH tIL

tIL tIH

INT0
INT1
INT2
INT3
INT4
NMI
(NMI is specified only for
the falling edge)

tRSL

0.2VDD

RST

External interruption
High and Low level widths

Reset input Low level width

INT0
INT1
INT2
INT3
INT4
NMI

RST

1

32/fc

µs

µs

Item Symbol Pin Conditions Min. Max. Unit

tIH
tIL

tRSL

(4) Interruption, reset input

Fig. 7. Interruption input timing

Fig. 8. RST input timing

(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V reference)

– 29 –

CXP740056/740096/740010

Appendix

Fig. 9. Recommended oscillation circuit

C2

Rd

EXTAL

XTAL

C

1

(i) Main clock

TEX

TX

C

1 C2

Rd

(iii) Sub clock

Rd

EXTAL

XTAL

C

1

C2

(ii) Main clock

Manufacturer

RIVER
ELETEC
CO., LTD.

MURATA MFG
CO., LTD.

CSA10.0MTZ
CSA12.0MTZ
CSA16.00MXZ040
CST10.0MTW

∗

CST12.0MTW

∗

CST16.00MXW0C1

∗

KINSEKI LTD.

Seiko
Instruments Inc.

Model

HC-49/U03

HC-49/U (-S)

P3
VTC-200

SP-T

fc (MHz)

10.0

12.0

16.0

10.0

12.0

16.0

8.0

12.0

16.0

8.0

12.0

16.0

30

5

30

5
18
12
10
10

5

Open

30
18

30

5

30

5
18
12
10
10

5

Open

33
18

0

∗1

330

∗1

0

∗1

120k

32.768kHz

32.768kHz

(iii)

330k

(iii)

C1 (pF) C2 (pF) Rd (Ω)

Circuit
example

(i)

∗Indicates types with on-chip grounding capacitor (C1, C2).
∗1

XTAL series resistor (Rd = 500Ω or less) is hard to affect noise by ESD.

(i)

(ii)

CL = 12.5pF

Remarks

– 30 –

CXP740056/740096/740010

Characteristics Curve

20

(100µA)

3

4 5

6

0.1

5.0

1.0

V

DD – Supply voltage [V]

I

DD

– Supply current [mA]

IDD vs. VDD

(fc = 24MHz, Ta = 25°C, Typical)

2

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

1/16 dividing mode

1/4 dividing mode

Sleep mode

32kHz operation
mode

0

20

10

fc – System clock [MHz]

I

DD

– Supply current [mA]

IDD vs. fc

(VDD = 5.0V, Ta = 25°C, Typical)

10

30

1/2 dividing mode

(100µA)

3

4 5

6

0.1

5.0

1.0

V

DD – Supply voltage [V]

I

DD

– Supply current [mA]

IDD vs. VDD

(fc = 12MHz, Ta = 25°C, Typical)

2

0.05

(50µA)

0.01

(10µA)

0.5

10.0

20.0

1/16 dividing mode

1/4 dividing mode

Sleep mode

1/2 dividing mode

32kHz sleep mode

24

1/2 dividing mode

1/16 dividing mode

Sleep mode

1/4 dividing mode

20

0

20

fc – System clock [MHz]

I

DD

– Supply current [mA]

IDD vs. fc

10

30

24

1/2 dividing mode

1/16 dividing mode
Sleep mode

1/4 dividing mode

10

0

0

(VDD = 3.0V, Ta = 25°C, Typical)

– 31 –

CXP740056/740096/740010

Package Outline Unit: mm

SONY CODE
EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL
LEAD TREATMENT

LEAD MATERIAL
PACKAGE MASS

EPOXY RESIN

SOLDER PLATING

42/COPPER ALLOY

PACKAGE STRUCTURE

23.9 ± 0.4

QFP-100P-L01

100PIN QFP (PLASTIC)

20.0 – 0.1

+ 0.4

0.15 – 0.05

+ 0.1

15.8 ± 0.4

17.9 ± 0.4

14.0 – 0.1

+ 0.4

2.75 – 0.15

+ 0.35

A

0.65
M

0.13

QFP100-P-1420

1.7g

1

100

81

80 51

50

31

30

0.3 – 0.1

+ 0.15

DETAIL A

0° to 10°

0.8 ± 0.2

(16.3)

0.15

0.1 – 0.05

+ 0.2

SONY CODE
EIAJ CODE
JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

PACKAGE MASS

EPOXY RESIN
SOLDER PLATING
42 ALLOY

PACKAGE STRUCTURE

DETAIL A

LQFP-100P-L01

LQFP100-P-1414

100PIN LQFP (PLASTIC)

16.0 ± 0.2

∗ 14.0 ± 0.1

75

51

50

26

25

1

76

0.5

0.18 – 0.03

+ 0.08

(0.22)

A

1.5 – 0.1

+ 0.2

0.127 – 0.02

+ 0.05

0.5 ± 0.2

(15.0)

0° to 10°

0.1 ± 0.1

0.5 ± 0.2

100

0.1

NOTE: Dimension “∗” does not include mold protrusion.

0.8g

0.13

M