Datasheet CXP402 Datasheet (Sony)

CMOS 4-bit Single Chip Microcomputer

Description

The CXP402 is a CMOS 4-bit single chip micro­computer which consists of 4-bit CPU, ROM, RAM,
8-bit timer, 8-bit timer/counter, 18-bit time-base timer,
LCD controller/driver, digital signal processor circuit
for CD player, 1-bit DAC and the like.

Features

• Instruction cycle 1.89µs for 16.93MHz oscillation

• ROM capacity 6144 × 8 bits

• RAM capacity 400 × 4 bits

(Including stack and display area)

• LCD controller/driver (Enables to direct drive)

• 8-bit timer, 8-bit timer/event counter and 18-bit

time-base timer are incorporated; they are

independently controllable.

• Arithmetic and logical operations between the entire

RAM area, I/O area and the accumulator by means

of the memory mapped I/O.

• Entire ROM area can be referred by the table look-

up instruction.

Digital Signal Processor (DSP) Block

• Playback mode supporting CAV (Constant Angular

Velocity)

• Frame jitter free

• Allows relative rotational velocity readout

• Supports spindle external control

• Wide capture range playback mode

• Spindle rotational velocity following method

• 16K RAM

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• SEC strategy-based error correction

• Subcode demodulation and Sub Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry correction circuit

• Servo auto sequencer

• Digital audio interface output

• Digital peak meter

Digital Filter, DAC and Analog Low-Pass Filter Blocks

• DBB (digital bass boost) function

• Digital de-emphasis

• Digital attenuation

• Zero detection function

• 8Fs oversampling digital filter

• S/N: 100dB or more

(master clock: 384Fs, typ.)

Logical value: 109dB

• THD + N: 0.007% or less
(master clock: 384Fs, typ.)

• Rejection band attenuation: –60dB or more

• 112-pin plastic LQFP

• Piggyback package (CXP401Z) available

Structure

Silicon gate CMOS IC

– 1 –

E98924-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXP402

112 pin LQFP (Plastic)

For the availability of this product, please contact the sales office.

– 2 –

CXP402

58

59

60

63

64

61

62

70

65

XRST

RMC

PC3
PC2
PC1
PC0
PB3
PB2
PB1
PB0

29

SEIN

CNIN

DATO

XLTO

CLKO

MON

MDS

MDP

LOCK

VPCO2
VPCO1

VCKI

V16M

VCTL

PCO

FILI

FILO

AV

SS

CLTV

AV

DD

RF
BIAS

ASYI

ASYO

C4M

SBSO

EXCK

8

9
10

11

12
13

14 15

16

17

18

19

20

21

22

23
24

25

26

2

3

4

5

1

49

54

55

V

LC1

V

LC2

V

LC3

COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3

88
87
86
85

89

90

95

94

91

92

93

LRCK

PCMD

PCMDI

BCK

BCKI

AV

SS

AV

DD

AOUT2

AIN2

LOUT2

AV

SS

XV

SS

XTAO

XTAI

XV

DD

AV

SS

LOUT1

AIN1

AOUT1

AV

DD

AV

SS

LRCKI

37

36

35

34

32
33

100

99

98

97

96

101
102

103
104

105
106
107
108
109
110
111

69

68

67

66

PA3

PA2

PA1

PA0

73

74

81

82

83

84

75

76

77

78

79

80

SEG15

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

27

28

TEST1

TEST0

GTOP

XPCK

RFCK

C2PO

XROF

MNT3

MNT1

MNT0

DOUT

WFCK

39

38

41

42

45

46

47

48

50

52

6

7

57

71

72

V

SS

VDD

VDD

VSS

43

44

56

CTEST

DTEST

V

SS

VDD

XRSTO

FOK

GFS

EMPH
SCOR

30

31

51
53

40

LCD Controller/Driver

SPC500

CPU Core

ROM

6K Byte

RAM

400 × 4bit

T/C RMC

Port RST

SCOR

EMPHI

Servo Auto

Sequencer

Digital

CLV

Digital

PLL

Asymmetry

Collector

D/A

I/F

EFM

Demodulator

EPROM

Collector

1-bit DAC

Digital Filter

Test

Circuit

Analog

Out

16K

RAM

ACDT

RMUT

LMUT

DATA

XLAT

CLOK

XRST

SYSM

PWMI

XTSL

ASYE

SENS

FOK

GFS

SQCK

SQSO

INT

PY0

PY2

PX0

PX3

PF0

PF1

PF2

PF3

PE0

PE1

PE2

PE3

PD0

PD1

PD2

PY1

SIO I/F

OSC

PORT I/F CPU I/F

PY3

Block Diagram

– 3 –

CXP402

Pin Configuration (Top View)

2
3
4
5
6
7
8

9
10
11

12
13
14
15
16
17
18
19
20

21
22

23

24
25
26
27
28

1

57

58

59

60

63

64

61

62

70
69
68
67

65

66

71

72

73

74

81

82

83

84

75

76

77

78

79

80

SEIN
CNIN

DATO

XLTO

CLKO

V

SS

VDD

MON

MDP
MDS

LOCK
VPCO2
VPCO1

VCKI
V16M
VCTL

PCO

FILI

FILO

AV

SS

CLTV

AV

DD

RF
BIAS
ASYI

ASYO
TEST1
TEST0

XRST

XRSTO

FOK

LRCK

PCMD

PCMDI

BCK

BCKI

GTOP

XPCK

GFS

RFCK

C2PO

V

SS

V

DD

XROF

MNT3

MNT1

MNT0

C4M

DOUT

EMPH

WFCK

SCOR

SBSO

EXCK

DTEST

NC

AV

SS

AV

DD

AOUT2

AIN2

LOUT2

AV

SS

XV

SS

XTAO

XTAI

XV

DD

AV

SS

LOUT1

AIN1

AOUT1

AV

DD

AV

SS

V

LC1

V

LC2

V

LC3

COM0

COM1

COM2

COM3

SEG0

SEG1

SEG2

SEG3

SEG15
V

DD

VSS
RMC

PC3
PC2
PC1
PC0
CTEST

PB3
PB2
PB1
PB0

PA3
PA2
PA1
PA0

SEG14

SEG13

SEG12

SEG11

SEG10

SEG9

SEG8

SEG7

SEG6

SEG5

SEG4

LRCKI

88

87

86

85

89

90

100

99

98

97

96

95

94

91

92

93

101

102

103

104

105

106

107

108

109

110

111

112

29

30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

– 4 –

CXP402

Pin Description

Symbol

I/O

Description

(Port A)
4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is
attached for input. (4 pins)

(Port B)
4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is
attached for input. (4 pins)

(Port C)
4-bit I/O port. I/O can be set in a unit of single bits. Pull-up resistor is
attached for input. (4 pins)

LCD segment signal output. (16 pins)
LCD common signal output.
LCD bias power supply. Bias voltage is generated, which is 1/3 the

supply voltage due to the internal resistor. (3 pins)
SENS input from SSP.
Track jump count signal input.
Serial data output to SSP.
Serial data latch output to SSP.
Serial clock output to SSP.
Spindle motor ON/OFF control output.

Spindle motor servo control. (2 pins)

Lock signal output. GFS is sampled at 460Hz and; when GFS is high,
this pin outputs a high signal. If GFS is low eight convective samples,
this pin outputs low.

Wide-band EFM PLL charge pump output. (2 pins)
Wide-band EFM PLL VCO2 oscillation input.

Wide-band EFM PLL VCO2 oscillation output.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL charge pump output.
Master PLL filter input.
Master PLL filter output.
Master VCO control voltage input.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM output. (full swing)
System reset input. Active at low.

I/O

I/O

I/O

Output
Output

Input
Input
Output
Output
Output
Output

Output
(tri-state)

Output

Output
(tri-state)

Input
Output
Input
Output (tri-state)
Input
Output (Analog)
Input
Input
Input
Input
Output
Input

PA0 to PA3

PB0 to PB3

PC0 to PC3

SEG0 to SEG15
COM0 to COM3

VLC1 to VLC3
SEIN

CNIN
DATO
XLTO
CLKO
MON
MDP
MDS

LOCK

VPCO1
VPCO2

VCKI
V16M
VCTL
PCO
FILI
FILO
CLTV
RF
BIAS
ASYI
ASYO
XRST

CXP402

Symbol

I/O

Description
Reset signal output. Active at low.
Focus OK input.

Used for SENS output and servo auto sequencer.
D/A interface LR clock output. (f = Fs)
LR clock input.
D/A interface serial data output.
D/A interface serial data input.
D/A interface bit clock output.
D/A interface bit clock input.
GTOP output.
XPLCK output.
GFS output.
RFCK output.
C2PO output.
XRAOF output.
MNT3 output.
MNT1 output.
MNT0 output.
1/4 frequency division output of the oscillation input. (4.2336MHz for

16.3944MHz)
Digital Out output.
De-emphasis ON/OFF output. High is output for ON; low is output for OFF.
WFCK output.
Subcode sync detection output. Outputs a high signal when either

subcode sync S0 or S1 is detected.
Sub P to W serial data output.
SBSO serial clock input.
Lch analog output.
Lch operational amplifier input.
Lch LINE output.
Rch analog output.
Rch operational amplifier
Rch LINE output.
Remote control receiver circuit input.

Connect a crystal for system clock oscillation. When the clock is supplied
externally, input it to the XTAI pin and leave the XTAO pin open.

No connected.

Output
Input
Output

Input
Output
Input
Output
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output

Output
Output

Output
Output

Output
Output

Input
Output (Analog)
Input (Analog)
Output
Output (Analog)
Input (Analog)
Output
Input
Input

XRSTO
FOK
LRCK

LRCKI
PCMD
PCMDI
BCK
BCKI
GTOP
XPCK
GFS
RFCK
C2PO
XROF
MNT3
MNT1
MNT0

C4M
DOUT

EMPH
WFCK

SCOR
SBSO

EXCK
AOUT1
AIN1
LOUT1
AOUT2
AIN2
LOUT2
RMC
XTAI
XTAO
NC

– 5 –

– 6 –

CXP402

Symbol

I/O

Description
Positive power supply.
GND.
Positive power supply for analog circuit.
GND for analog circuit.
Positive power supply for oscillation circuit.
GND for oscillation circuit.

Test for LSI.
Connect to GND for normal operation.

Input
Input
Input
Input

VDD
VSS
AVDD
AVSS
XVDD
XVSS
TEST1
TEST0
DTEST
CTEST

Notes

• Power supply pins AVDD, AVss, XVDD, XVss, VDD and Vss should process all the pins.

• PCMD is the MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync

protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal
transition point coincide.

• The GFS signal goes high when the frame sync and the insertion timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs (at normal speed).

• C2PO represents the data error status.

• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

– 7 –

CXP402

Port C

8 pins

Hi-Z

Hi-Z

When reset

PA0 to PA3
PB0 to PB3

4 pins

PC0 to PC3

RMC
XRST
SEIN
CNIN
VCKI
FOK
LRCKI
PCMDI
BCKI
EXCK

10 pins

Hi-Z

Ports A, B data

Ports A, B I/O direction

RD (Ports A, B)

Data bus

∗

Pull-up transistor approx. 50kΩ

∗

Input protection
circuit

IP

Input/Output Circuit Formats for Pins

Port A
Port B

Pin

Circuit format

Port C data

Port C I/O direction

∗

Data bus

RD (Port C)

IP

Schmitt input

∗

Pull-up transistor approx. 50kΩ

Internal circuit

∗

EMPHI is not Schmitt input.

IP

– 8 –

CXP402

4 pins

16 pins

VDD level

VLC1 = 3/4VDD
VLC2 = 2/4VDD
VLC3 = 1/4VDD
(when pins
left open)

When reset

COM0
COM1
COM2
COM3

3 pins

VLC1
VLC2
VLC3

XVDD
XTAI
XTAO
XVSS

4 pins

Oscillation

VLC1

VLC2

VDD

VLC3

Pin

Circuit format

VCH

VCL

SEG0 to SEG15

VDD level

XVDD

XTAI

SS

XV

XTAO

∗

IP

∗

∗

Internal resistor approx. 20kΩ

– 9 –

CXP402

PCO
MDP
VPCO1
VPCO2

4 pins

1 pin

—

MDS

Output enable

MDS

—

IP

6 pins

—

—

When reset

VCTL
FILI
CLTV
RF
BIAS
ASYI

2 pins

AIN1
AIN2

AOUT1
AOUT2
LOUT1
LOUT2

4 pins

—

IP

Poly resistor

Pin

Circuit format

– 10 –

CXP402

When reset

DATO
XLTO
CLKO
LOCK
MON
V16M
FILO
ASYO
XRSTO
LRCK
PCMD
BCK
GTOP
XPCK
GFS
RFCK
C2PO
XROF
MNT3
MNT1
MNT0
C4M
DOUT
EMPH
WFCK
SCOR
SBSO

—

Pin

Circuit format

27 pins

– 11 –

CXP402

Absolute Maximum Ratings

Item
Supply voltage
LCD bias voltage
Input voltage
Output voltage
High level output current
High level total output current
Low level output current
Low level total output current
Operating temperature
Storage temperature
Allowable power dissipation

VDD
VLC1, VLC2, VLC3
VIN
VOUT
IOH
∑IOH
IOL
∑IOL
Topr
Tstg
PD

–0.3 to +7.0

∗1

–0.3 to +7.0

∗2

–0.3 to +7.0

∗2

–0.3 to +7.0

∗2

–5

–70

15

100

–20 to +75

–40 to +125

600

V
V
V

V
mA
mA
mA
mA

°C
°C

mW

Output pin (value per pin)
Total of output pins
Output pin (value per pin)
Total of output pins

Symbol

Ratings Unit Remarks

∗1

The potential difference between analog power supplies AVDD, AVss, the oscillation power supplies XVDD,
XVss and VDD, Vss should be within ±0.3V.

∗2

VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V.

Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should

be conducted under the recommended conditions. Exceeding those conditions may adversely affect the
reliability of the LSI.

Recommended Operation Conditions

Item

Supply voltage VDD

VLC1,
VLC2,
VLC3

VIH
VIHS
VIL
VILS
VIA
Topr

LCD bias voltage

High level input voltage

Low level input voltage

Analog input voltage
Operating temperature

Symbol Min.

3.4

VSS

0.7VDD

0.8VDD
0
0
0

–20

5.25

VDD

VDD
VDD

0.3VDD

0.2VDD
VDD
+75

V

V

V
V
V
V
V

°C

Operation guaranteed range
Liquid crystal power supply

range

∗1

Hysteresis input

∗2

Hysteresis input

∗2

∗3

Max. Unit

Remarks

∗1

The optimal value depends on the characteristics of the used LCD element. Also, the LCD bias voltage is
biased to 1/3 the supply voltage by the resistor of approximately 20kΩ in the LSI.

∗2

RME, XRST, EXCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, PCMDI pins

∗3

CLTV, FILI, RF, VCTL, AIN1, AIN2, BAIS, ASYI pins

(Vss = 0V reference)

(Vss = 0V reference)

– 12 –

CXP402

Electrical Characteristics

DC characteristics (Topr = –20 to +75°C, VSS = AVSS = XVSS = 0V reference)

Item

High level output
voltage

VOH

PA, PB
BCKI, C2PO, SBSO,

DATO, XLTO, CLKO,
PA (VOL only),
PB (VOL only),
PC, MON, MDS,
LOCK, LRCK, PCMD,
BCK, GTOP, GFS,
RFCK, XROF, MNT3,
MNT1, MNT0, DOUT,
WFCK, SCOR, MDP,
VPCO2, VPCO1, PCO,
V16M, EMPH, XPCK,
ASYO, C4M, XRSTO,
LRCK, PCMD

VDD = 4.75V, IOH = –0.1mA
VDD = 4.75V, IOH = –2.0mA

VDD= 4.75V, IOH

= –

0.28mA

VDD= 4.75V, IOL = 0.36mA

VDD = 4.75V, IOL = 6.0mA

VDD = 4.75V, IOL = 9.0mA
VDD = 5.25V, VIH = 5.25V

VDD = 5.25V, VIL = 0.4V

4.25

4.25

4.25

0.2

–0.2

–0.06

10

0.4

0.4

0.6
30

–30

–0.2

±5

20

V
V

V

V

V

V

µA
µA

mA

µA

pF

VDD = 5.25V
VI = 0, 5.25V

VDD = 5.0V
VLC1 = 3.75V
VLC2 = 2.5V
VLC3 = 1.25V

VDD = 5.25V

16.93MHz self-excited
oscillation operation
All output pins left open

Clock 1MHz
0V for no-measured pins

XTAI

PA to PC
PCMDI, RME,

XRST, EXCK, FOK,
SEIN, CNIN, VCKI,
LRCKI, BCKI,
CLTV, FILI, RF,
VCTL, AIN1, AIN2,
MDP, MDS,
VPCO1, VPCO2

COM0 to COM3

SEG0 to SEG15

VDD, AVDD

Pins other than
VLC1 to VLC3,
COM0 to COM3,
SEG0 to SEG15,
PA to PC,
VDD, VSS, AVDD,
AVSS, XVDD, XVSS

VOL

IIH
IILE
IIL

IIZ

Low level output
voltage

Input current

High-impedance
I/O leak current

Common output
impedance

7

3

5

37

30

5

15

80

kΩ

kΩ

kΩ

mA

VDD = 5V, VLC1, VLC2, VLC3
pins left open

VLC1, VLC2, VLC3

RB

RCOM

RSEG

IDD

CIN

LCD bias voltage
resistance

Segment output
impedance

Supply current

Input capacity

Symbol Pins Conditions Min. Typ. Max. Unit

FILO

– 13 –

CXP402

AC Characteristics

1. XTAI pin

(1) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(2) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(3) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Oscillation
frequency

fMAX 15 16.93 20 MHz

Item

Symbol

Min. Typ. Max. Unit

High level pulse
width

tWHX

13 500

ns

Low level pulse
width

tWLX

13 500

ns

Pulse cycle

tCK

26

1,000

ns

Input high level

VIHX

VDD – 1.0

V

Input low level

VILX 0.8

V

Rise time,
fall time

tR, tF

10

ns

Item

Symbol Min. Typ. Max. Unit

Input amplitude VI 2.0 VDD + 0.3 Vp-p

Item Symbol Min. Typ. Max. Unit

tR tF

tWHX

tWLX

tCK

VILX

VIHX × 0.1

VIHX × 0.9

V

IHX

XTAI

V

DD/2

– 14 –

CXP402

2. CNIN, EXCK pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

3. BCKI, LRCKI, PCMDI pins

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK frequency
EXCK pulse width

fCK

tWCK
tSU
tH
tD
tWL

fT
fWT

750
300
300
300
750

750

0.65

0.65

MHz

ns
ns
ns
ns
ns

MHz

ns

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tHtSU

tWLtD

1/fT

tWT tWT

tH

tSU

CLK

DATA

XLT

EXCK

CNIN

SUBQ

BCK pulse width
DATAL, R setup time
DATAL, R hold time
LRCK setup time

tW
tSU
tH
tSU

ns
ns
ns
ns

Item Symbol

Conditions

Typ.
94
18
18
18

Min.

Max. Unit

VDD/2 VDD/2

tW (BCKI) tW (BCKI)

tSU

(PCMDI)

t

H

(PCMDI)

tSU

(LRCKI)

BCKI

PCMDI

LRCKI

– 15 –

CXP402

1-bit DAC, LPF Blocks Analog Characteristics

Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)

Fs = 44.1kHz.
The total harmonic distortion and signal-to-noise ratio are measured by the circuits shown below.

LPF external circuit diagram

Block diagram of analog characteristics measurement

Item

Total
harmonic
distortion

Signal-to­noise ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data (A-filter)

384Fs
768Fs
384Fs
768Fs

96
96

0.0050

0.0045
100
100

0.0070

0.0065

Min.

Typ.

Max.

Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

680p

12k

12k

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXP402

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Output voltage
Load resistance

VOUT
RL

∗1
∗1

Vrms

kΩ

Item Symbol

8

Min.

Max.

1.23

∗

Typ.

Applicable pinsUnit

∗

When a sine wave of 1kHz, 0dB is output.

Applicable pins

∗1

LOUT1, LOUT2

– 16 –

CXP402

SONY CODE

EIAJ CODE

JEDEC CODE

PACKAGE MATERIAL

LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT

EPOXY RESIN
SOLDER PLATING
COPPER ALLOY

PACKAGE STRUCTURE

0.65

0.32 ± 0.05

1

28

29

56

57

84

85

112

20.0 ± 0.1

22.0 ± 0.2 1.7MAX

1.4 ± 0.1

M

DETAIL A

DETAIL B

0.32 ± 0.05
(0.3)

(0.125)

0.145 ± 0.03

(21.0)(0.5)

0° — 10°

0.13

A

B

0.1

112PIN LQFP(PLASTIC)

LQFP-112P-L01

LQFP112-P-2020

1.3g

S

S

S

0.1 ± 0.05

0.6 ± 0.15

0.25

Package Outline Unit: mm