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CMOS-CCD 1H Delay Line for PAL
CXL5514M/P
Description
The CXL5514M/P are CMOS-CCD delay line ICs
designed for processing video signals. This ICs
provide a 1H delay time for PAL signals including
the external lowpass filter.
Features
• Single 5V power supply
• Low power consumption
• Built-in peripheral circuit
• Built-in tripling PLL circuit
• Sync tip clamp mode
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD +6 V
• Operating temperature Topr –10 to +60 °C
• Storage temperature Tstg –55 to +150 °C
• Allowable power dissipation
PD
CXL5514M 350 mW
CXL5514P 480 mW
Recommended Operating Range (Ta = 25°C)
VDD 5V ± 5%
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.
• Clock frequency fCLK 4.433619MHz
• Input clock waveform Sine wave
CXL5514M CXL5514P
8 pin SOP (Plastic) 8 pin DIP (Plastic)
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 575mVp-p (Max.)
(at internal clamp condition)
Functions
• 848-bit CCD register
• Clock driver
• Auto-bias circuit
• Sync tip clamp circuit
• Sample and hold circuit
• Tripling PLL circuit
• Inverted output
Structure
CMOS-CCD
)
Block Diagram and Pin Configuration (Top View)
V
DD VCO OUT VCO IN CLK
8
Auto-bias circuit
Clamp circuit
1
IN AB OUT V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
7
CCD
(848 bit)
Output circuit
(S/H 1 bit)
2
6
3
5
PLL
Timing circuit
Clock driver
Bias circuit A
Bias circuit B
4
SS
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E94903-ST
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Pin Description
Pin No. Symbol I/O Description Impedance
CXL5514M/P
1
2
3
4
5
6
7
8
IN
AB
OUT
VSS
CLK
VCO IN
VCO OUT
VDD
Electrical Characteristics
Item
Symbol
Supply current
IDD
I
O
O
—
O
—
Signal input
Auto-bias DC output
Signal output
GND
I
Clock input (fsc)
I
VCO input
VCO output (3fsc)
5V power supply
>10KΩ
40 to 500Ω
>10KΩ
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p, sine wave)
See “Electrical Characteristics Test Circuit”.
SW conditions
Conditions
Min.
Typ.
Max. Unit
NOTE
12
—
a — 10 15 20 mA 1
Low frequency gain
Frequency response
Differential gain
Differential phase
S/H pulse coupling
S/N ratio
GL
fR
DG
DP
CP
SN
200kHz
500mVp-p
Sine wave
200kz ←→ 4.434MHz
150mVp-p Sine wave
5-staircase wave
(See Note 4.)
5-staircase wave
(See Note 4.)
No signal input
50% white video signal
(See Note 6.)
a b –2 0 2 dB 2
b ←→ c
b –2.7 –1.7 –0.7 dB 3
dc035%4
d c 0 3 5 degree 4
f a — — 350 mVp-p 5
e d 52 56 — dB 6
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NOTE
1. This is the IC supply current value during clock and signal input.
2. GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
CXL5514M/P
GL = 20 log
OUT pin output voltage [mVp-p]
[dB]
500 [mVp-p]
3. Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at OUT pin when a
150mVp-p, 200kHz sine wave is fed to IN pin, and from the output voltage at OUT pin when a 150mVp-p,
4.434MHz sine wave is fed to the same, calculation is made according to the following formula.
fR = 20 log
OUT pin output voltage (4.434MHz) [mVp-p]
[dB]
OUT pin output voltage (200kHz) [mVp-p]
4. In Fig. below, the differential gain (DG) and the differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
150mV
350mV
500mV
150mV
1H 64µs
5. Leakage of internal clock components and related high frequency component to the output signal, during
no signal input, is tested.
Test value
[mVp-p]
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CXL5514M/P
6. S/N ratio during a 50% white video signal input shown in Fig. below is tested at the video noise meter, in
BPF 100kHz to 5MHz, Sub Carrier Trap mode.
175mV
325mV
150mV
1H 64µs
CLOCK
fSC (4.433619MHz) Sine wave
400mVp-p (Typ.)
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CXL5514M/P
400mVp-p
Sine wave
fsc (4.433619MHz)
6.8µ2200p
0.1µ 0.1µ
× 3
Note 2)
d
Noise meter
BPF
Note1) Note 2)
BPF frequency response
0
[dB]
LPF frequency response
[dB]
–3
0
–3
–50
–50
6M 13.3M
Frequency [Hz]
50 200
6M 13.3M
Frequency [Hz]
Oscilloscope
Spectrum analyzer
+15V
SS
IN AB OUT V
b
2.2k
4
3
0.1µ
2
1
a
5
6
7
8
CXL5514M/P
VDD VCO OUT VCO IN CLK
× 3
Note1)
SW2
Vector scope
LPF
c
5V
200kHz
500mVp-p
Sine wavea200kHz
150mVp-p
Sine waveb4.434MHz
Electrical Characteristics Test Circuit
1µ
SW1
c
150mVp-p
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1M
Sine wave
d
5-staircase wave
e
50% white
video signal
f
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CXL5514M/P
400mVp-p
Sine wave
fsc (4.433619MHz)
0.1µ 0.1µ
LPF
Output
56k 1k
2.2k
Transistor used
NPN: 2SC403
Transistor used
NPN: 2SA403
5V
470
33k
5
6
SS
4
1µ
3
6.8µ2200p
5V
0.1µ
7
8
CXL5514M/P
VDD VCO OUT VCO IN CLK
2
1
IN AB OUT V
1M
1µ
Input
5V
1.8k
When VCO OUT (7Pin) in use
3fsc OUT
2SC403
7
2.2k
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Application Circuit
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Example of Representative Characteristics
CXL5514M/P
Supply current vs. Supply voltage
20
15
Supply current [mA]
10
4.75
5 5.25
Supply voltage [V]
Frequency response vs. Supply voltage
0
Low frequency Gain vs. Supply voltage
1
0
–1
Low frequency Gain [dB]
–2
4.75
Supply voltage [V]
5 5.25
Differential gain vs. Supply voltage
10
8
–1
–2
Frequency response [dB]
–3
4.75
5 5.25
Supply voltage [V]
Supply current vs. Ambient temperature
20
18
16
14
Supply current [mA]
12
6
4
Differential gain [%]
2
0
4.75
Supply voltage [V]
5 5.25
Low frequency Gain vs. Ambient temperature
1
0
–1
Low frequency Gain [dB]
10
–20
06020
Ambient temperature [°C]
40 80
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–2
–20
40 8006020
Ambient temperature [°C]
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CXL5514M/P
Frequency response vs. Ambient temperature
0
–1
–2
Frequency response [dB]
–3
–20
Ambient temperature [°C]
2
40 8006020
Differential gain vs. Ambient temperature
10
8
6
4
Differential gain [%]
2
0
–20
Frequency response
40 8006020
Ambient temperature [°C]
0
–2
–4
Gain [dB]
–6
–8
–10
10k
10M100k 1M
Frequency [Hz]
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Package Outline Unit : mm
CXL5514M
CXL5514M/P
8PIN SOP (PLASTIC)
CXL5514P
+ 0.1
0.4 – 0.05
SONY CODE
EIAJ CODE
JEDEC CODE
+ 0.4
5.0 – 0.1
85
1
4
1.27
± 0.12
SOP-8P-L03
∗SOP008-P-0225-A
+ 0.3
4.4 – 0.1
M
PACKAGE STRUCTURE
A
+ 0.1
0.15 – 0.05
0° to 10°
A
DETAIL
MOLDING COMPOUND
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
1.25 – 0.15
+ 0.15
0.1 – 0.1
0.5 ± 0.2
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
0.1g
+ 0.4
0.10
6.4 ± 0.4
SONY CODE
EIAJ CODE
JEDEC CODE
8
1
2.54
0.5 ± 0.1
1.2 ± 0.15
+ 0.4
9.4 – 0.1
DIP-8P-01
∗DIP008-P-0300-A
8PIN DIP (PLASTIC) 300mil
5
7.62
4
+ 0.4
3.7 – 0.1
0.5 MIN
3.0 MIN
PACKAGE STRUCTURE
+ 0.3
6.4 – 0.1
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
+ 0.1
0.25 – 0.05
0° to 15°
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
0.5g
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