Datasheet CA3240EZ Specification

CA3240, CA3240A

Data Sheet August 2001 File Number 1050.5

Dual, 4.5MHz, BiMO S Operational Amplifie r
with MOSFET Input/Bipolar Output

The CA3240Aand CA3240 are dual versions of the popular
CA3140 seriesintegratedcircuit operationalamplifiers. They
combine the advantagesof MOS and bipolar transistors on
the same monolithic chip. The gate-protected MOSFET
(PMOS) input transistorsprovide high input impedance and
a wide common-mode input voltage range (typically to 0.5V
below the negative supply rail). The bipolar output
transistorsallow a wide output voltage swing and provide a
high output current capability.

TheCA3240AandCA3240arecompatiblewiththeindustry
standard 1458 operationalamplifi e rsinsimilarpa ckages.The
offsetnullfeatureis availableonly when thesetypes are supplied
inthe14leadPDIPpackage(E1suffix).

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE

CA3240AE -40 to 85 8 Ld PDIP E8.3
CA3240AE1 -40to85 14LdPDIP E14.3
CA3240E -40 to 85 8Ld PDIP E8.3

PKG.

NO.

Features

• Dual Version of CA3140

• Internally Compensated

• MOSFET Input Stage

- Very High Input Impedance (Z

- Very Low Input Current (I

- Wide Common-Mode Input Voltage R ange (V

)1.5TΩ (Typ)

IN

) 10pA (Typ) at ±15V

I

ICR

): Can

Be Swung 0.5V Below Negative Supply Voltage Rail

• Directly Replaces Industry Type 741 in Most Applications

Applications

• Ground Referenced Single Amplifiers in Automobile and
Portable Instrumentation

• Sample and Hold Amplifiers

• Long Duration Timers/Multivibrators ( Microseconds­Minutes-Hours)

• PhotocurrentInstrumentation

• Intrusion Alarm System • ActiveFilters

• Comparators • Function Generators

• Instrumentation Amplifiers • Power Supplies

Functional Diagram

2mA 4mA

BIAS CIRCUIT

CURRENT SOURCES

AND REGULATOR

+

IN-

PUT

A ≈ 10

-

OFFSET NULL

NOTE: Only available with 14 lead DIP (E1 Suffix).

A ≈ 10,000

12pF

A ≈ 1

C

1

Pinouts

CA3240, CA3240A (PDIP)

V+

OUTPUT (A)

INV.

INPUT (A)

NON-INV.

2mA1.6mA 2µA200µA200µA

OUT-

PUT

V-

INPUT (A)

INV.

INPUT (A)

NON-INV.

INPUT (A)

OFFSET

NULL (A)

OFFSET

NULL (B)

NON - INV.

INPUT (B)

INV.

INPUT (B)

† Pins 9 and 13 internally connected through approximately 3Ω.

TOP VIEW

1
2
3
4

V-

CA3240A (PDIP)

TOP VIEW

1
2
3
4

V-

5
6
7

8

V+
OUTPUT

7

INV.

6

INPUT (B)
NON-INV.

5

INPUT (B)

OFFSET

14

NULL ( A)
V+†

13

OUTPUT (A)

12

NC

11

OUTPUT (B)

10

V+

9

OFFSET

8

NULL ( B)

†

1

1-888-INTERSIL or 321-724-7143

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

| Intersil and Design is a trademarkof Intersil AmericasInc. | Copyright © Intersil Americas Inc. 2001

CA3240, CA3240A

Absolute Maximum Rati ng s Thermal Information

SupplyVoltage(BetweenV+andV-)..................... 36V

DifferentialInputVoltage............................... 8V

InputVoltage.........................(V++8V)to(V--0.5V)

InputCurrent.......................................1mA

OutputShortCircuitDuration(Note1)................ Indefinite

Operating Conditions

TemperatureRange..........................-40oCto85oC

VoltageRange.....................4Vto36Vor±2V to ±18V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within max­imum rating.

is measuredwith the component mountedon an evaluation PC board in free air.

2. θ

JA

Thermal Resistance (Typical, Note 2)

θ

JA

(oC/W)

8LeadPDIPPackage....................... 100

14LeadPDIPPackage...................... 100

MaximumJunction Temperature (PlasticPackage) . . . . . . . 150

MaximumStorageTemperatureRange..........-65

o

Cto150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300

o

C

o

C

Electrical Specifications ForEquipment Design, V

PARAMETER SYMBOL

Input Offset Voltage V
Input Offset Current I
Input Current I
Large-SignalVoltage Gain

(See Figures 13, 28) (Note 3)
CommonModeRejection

Ratio(SeeFigure18)
Common Mode Input VoltageRange

(See Figure 25)
Power Supply Rejection Ratio

(See Figure 20)

(∆V

Maximum Output Voltage (Note 4)
(See Figures 24, 25)

Maximum Output Voltage (Note 5) V
Total SupplyCurrent

(See Figure 16) For Both Amps
Total Device Dissipation P

NOTES:

3. At V

4. At R

=26V

O

=2kΩ.

L

5. At V+ = 5V, V- = GND, I

, +12V, -14V and RL=2kΩ.

P-P

=200µA.

SINK

IO

IO

I

A

OL

CMRR - 32 320 - 32 320 µV/V

V

ICR

PSRR

/∆V±)

IO

+ 12 13 - 12 13 - V

V

OM

- -14 -14.4 - -14 -14.4 - V

V

OM
OM-

I+ - 8 12 - 8 12 mA

D

-515- 2 5mV

- 0.5 30 - 0.5 20 pA

- 10 50 - 10 40 pA
20 100 - 20 100 - kV/V
86 100 - 86 100 - dB

70 90 - 70 90 - dB

-15 -15.5 to

- 100 150 - 100 150 µV/V
76 80 - 76 80 - dB

0.4 0.13 - 0.4 0.13 - V

- 240 360 - 240 360 mW

SUPPLY

= ±15V,TA=25oC, Unless Otherwise Specified

CA3240 CA3240A

11 -15 -15.5 to

+12.5

UNITSMIN TYP MAX MIN TYP MAX

12 V

+12.5

Electrical Specifications For EquipmentDesign, V

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Resistor (E1
PackageOnly)

Input Resistance R
Input Capacitance C
Output Resistance R
Equivalent WidebandInput NoiseVoltage

(See Figure 2)

2

I
I

O

e

N

= ±15V, TA=25oC, Unless Otherwise Specified

SUPPLY

TYPICAL VALUES

UNITSCA3240A CA3240

TypicalValueof Resistor Between Terminals4and 3(5)
or Between 4 and 14(8) to Adjust Maximum V

IO

18 4.7 kΩ

1.5 1.5 TΩ
44pF

60 60 Ω

BW = 140kHz, RS=1MΩ 48 48 µV

CA3240, CA3240A

Electrical Specifications For EquipmentDesign, V

= ±15V, TA=25oC, Unless Otherwise Specified (Continued)

SUPPLY

TYPICAL VALUES

PARAMETER SYMBOL TEST CONDITIONS

Equivalent Input Noise V oltage
(See Figure 19)

e

f=1kHz,RS=100Ω 40 40 nV/√Hz

N

f=10kHz,RS=100Ω 12 12 nV/√Hz

UNITSCA3240A CA3240

Short-CircuitCurrent to Opposite Supply IOM+Source 40 40 mA

-Sink 11 11 mA

I

OM

Gain BandwidthProduct (See Figures 14, 28) f

T

4.5 4.5 MHz

Slew Rate (See Figure 15) SR 9 9 V/µs
Transient Response (See Figure 1) t

Settling Timeat 10V

(See Figure 26) t

P-P

OS R

RL=2kΩ,CL= 100pF Rise Time 0.08 0.08 µs

r

=2kΩ,CL= 100pF Overshoot 10 10 %

L

AV=+1,RL=2kΩ,CL= 100pF,

S

Voltage Follower

To 1mV 4.5 4.5 µs
To 10mV 1.4 1.4 µs

Crosstalk (See Figure 23) f = 1kHz 120 120 dB

Electrical Specifications For Equipment Design, at V

= ±15V ,TA= -40 to 85oC, Unles sOtherwise Specified

SUPPLY

TYPICAL VALUES

PARAMETER SYMBOL

Input Offset Voltage |V
Input Offset Current (Note 8) |I
Input Current (Note 8) I
Large Signal Voltage Gain (See Figures 13, 28), (Note 6) A

|3 10mV

IO

|32 32pA

IO

I

OL

640 640 pA

63 63 kV/V

UNITSCA3240A CA3240

96 96 dB

Common Mode Rejection Ratio (See Figure 18) CMRR 32 32 µV/V

90 90 dB

Common Mode Input VoltageRange (See Figure 25) V

ICR

Power Supply Rejection Ratio (See Figure 20) PSRR

/∆V±)

(∆V

IO

Maximum Output Voltage (Note 7) (See Figures 24, 25) V

OM

V

OM

+12.4 12.4 V

- -14.2 -14.2 V

-15to+12.3 -15to+12.3 V
150 150 µV/V

76 76 dB

SupplyCurrent (SeeFigure 16) Total For Both Amps I+ 8.4 8.4 mA
Total Device Dissipation P
Temperature Coefficient of Input Offset Voltage ∆V

D

/∆T15 15µV/oC

IO

252 252 mW

NOTES:

6. At V

7. At R

8. At T

=26V

O

=2kΩ.

L

=85oC.

A

, +12V, -14V and RL=2kΩ.

P-P

Electrical Specifications For EquipmentDesign, at V+ = 5V, V- = 0V, T

PARAMETER SYMBOL

Input Offset Voltage |V
Input Offset Current |I
Input Current I
Input Resistance R
Large Signal Voltage Gain (See Figures 13, 28) A

3

=25oC, Unless Otherwise Specified

A

TYPICAL VALUES

UNITSCA3240A CA3240

|2 5mV

IO

|0.1 0.1pA

IO

I

IN

OL

22pA

11TΩ
100 100 kV/V
100 100 dB

CA3240, CA3240A

Electrical Specifications For EquipmentDesign, at V+ = 5V, V- = 0V, T

=25oC, Unless Otherwise Specified (Continued)

A

TYPICAL VALUES

PARAMETER SYMBOL

UNITSCA3240A CA3240

Common-Mode Rejection Ratio CMRR 32 32 µV/V

90 90 dB

Common-Mode InputVoltage Range (See Figure 25) V

ICR

-0.5 -0.5 V

2.6 2.6 V

Power Supply Rejection Ratio PSRR 31.6 31.6 µV/V

90 90 dB

Maximum Output Voltage (See Figures 24, 25) V

MaximumOutput Current Source I

Sink I

+3 3 V

OM

-0.3 0.3V

V

OM

+20 20mA

OM

-1 1mA

OM

Slew Rate (See Figure 15) SR 7 7 V/µs
Gain Bandwidth Product (See Figure 14) f

T

4.5 4.5 MHz
SupplyCurrent (SeeFigure 16) I+ 4 4 mA
Device Dissipation P

D

20 20 mW

Test Circuits and Waveforms

50mV/Div .,200ns/Div.

Top Trace:Input, Bottom Trace: Output

Top Trace:Input, Bottom Trace: Output

5V/Div., 1µs/Div.

FIGURE 1A. SMALL SIGNAL RESPONSE FIGURE 1B. LARGE SIGNAL RESPONSE

+15V

10kΩ

+
CA3240

-

-15V

2kΩ

0.05µF

0.1µF

0.1µF

BW (-3dB) = 4.5MHz
SR = 9V/µs

SIMULATED

100pF

LOAD

2kΩ

FIGURE 1C. TEST CIRCUIT

FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS

4

CA3240, CA3240A

Test Circuits and Waveforms (Continued)

R

S

1MΩ

+15V

+

CA3240

-

0.01µF

30.1kΩ

NOISE
VOLT AGE
OUTPUT

BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48µV(TYP)

FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT

Schematic Diagram (One Amplifier of Two)

BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE D YNAMIC CURRENT SINK

D

1

Q

2

Q

5

D

3

D

4

R
8K

Q

1

Q

6

Q

7

1

Q

8

D

2

-15V

0.01µF

1kΩ

V+

D

7

R

Q

3

Q

4

Q

17

R
1K

9

50Ω

R

10

Q

19

1K

R

11

20Ω

8

Q

18

R
12K

R

13

15K

Q

20

D

8

R

12

Q

14

20K

21

OUTPUT

INVERTING

NON-INVERTING

INPUT

INPUT

-

Q

+

R

2

500Ω

Q

11

R

4

500Ω

OFFSET NULL (NOTE 9)

NOTES:

9. Onlyavailablewith14LeadDIP(E1Suffix).

10. All r esistance valuesare in ohms.

5

D

5

Q

10

9

R

3

500Ω

Q

12

R

5

500Ω

C

12pF

1

Q

Q

13

14

R

6

50Ω

Q

Q

16

15

D

R

7

30Ω

6

V-

Application Information

CA3240, CA3240A

Circuit Description

The schematic diagram details one amplifier section of the
CA3240. It consists of a differentialamplifierstage using PMOS
transistors (Q
static discharge damage provided by zener diodes D

. Constant current bias is applied to the differential amplifier

D

5

from transistors Q
source. This assures a high common-mode rejection ratio. The
output of the differential amplifier is coupled to the base of gain
stage transistor Q
supplies the required differential-to-single-ended conversion.
Provision for offset null for types in the 14 lead plasticpackage
(E1 suffix) isprovided through the use of this current mirror.

The gain stage transistor Q
load (Q
collector of Q
emitter-follower output stage. Pulldown for the output stage is
provided by two independent circuits: (1) constant-current­connected transistors Q
sink transistor Q

pulldown current is constant at about 1mA for Q
from 0 to 18mA for Q
voltage between the output terminal and V+. The dynamic

current sink becomesactive whenever the output terminal is
more negative than V+ by about 15V. When this condition
exists, transistors Q
sink current from the output terminalto V-. This current always
flows when the output is in the linear region, either from the
load resistor or from the emitter of Q
present. The purpose of this dynamic sink is to permit the
output to go within 0.2V (V
ground. When the load is returned to V+, it may be necessary

to supplementthe 1mA of currentfrom Q
the dynamic current sink (Q

placing a resistor (Approx. 2kΩ)between the outputand V-.

and Q10) with gate-to-source protection against

9

3,D4

and Q5connected as a constant current

2

by means of anNPN current mirror that

13

has a high impedanceactive

and Q4) to provide maximum open-loop gain. The

3

directly drives the base of the compound

13

and its associated circuitry. The level of

16

13

and Q15and (2) dynamiccurrent-

14

and varies

depending on the magnitude of the

16

and Q16are turned on causing Q16to

21

if no load resistor is

18

(sat)) of V-with a 2kΩ load to

CE

). Thismay be accomplished by

16

15

in orderto turn on

15

,and

Input Circuit Considerations

As indicated by the typical VICR, this device will accept
inputs as low as 0.5V below V-. However,a series current­limiting resistor is r ecommended to limit the maximum input
terminal current to less than 1mA to prevent damage to the
input protection circuitry.

Moreover, some current-limiting resistance should be
provided between the inverting input and the output when
the CA3240 is used as a unity-gain voltage follower. This
resistance prevents the possibility of extremely large input­signal transients from forcinga signal through the input­protection network and directly driving the internal constant­currentsource which could result in positivefeedback via the
output terminal. A 3.9kΩ resistor is sufficient.

The typical i nput current is on the order of 10pA when the
inputs are centered at nominal device dissipation.As the
outputsupplies load current, device dissipationwill increase,
rasing the chip temperature and resulting in i ncreased input
current. Figure 4 shows typical input-terminal current versus
ambient temperature for the CA3240.

+HV

LOAD

L

LOAD

MT

2

120V

AC

CA3240

V+

R

R

S

30V NO LOAD

Output Circuit Considerations

Figure 24 shows output current-sinking capabilities of the
CA3240 at various supply voltages.Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristorsdirectly without the need for
level-shifting circuitry usually associated with the 741 series
of operational amplifiers.

Figure 3 shows some typical configurations. Note that a series
resistor , RL, is used in both cases to limit the drive available to
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
thyristors, from damaging the integrated circuit.

6

CA3240

FIGURE 3. METHODSOF UTILIZING THE V

CURRENT CAPABILITY OF THE CA3240 SERIES

R

L

CE (SAT)

MT

1

SINKING

CA3240, CA3240A

10K

VS= ±15V

1K

100

INPUT CURRENT (pA)

10

-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (

FIGURE 4. INPUT CURRENT vs TEMPERATURE

o

C)

It is well known that MOSFET devices can exhibit slight
changes in characteristics (for example, small changes in
input offset voltage) due to t he application of large
differential input voltages that are sustained over long
periods at elevated temperatures.

Both applied voltage and temperature accelerate these
changes. The process is r eversible and offset voltage shifts
of the opposite polarity reverse t he offset. In typical linear
applications, where the differential voltageis small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage.

Offset-Voltage Nulling

The input offset voltage of the CA3240AE1 and CA3240E1
canbenulledbyconnectinga10kΩ potentiometer between
Terminals 3 and 14 or 5 and 8 and returning its wiper arm to
Terminal 4, see Figure 5A. This technique, however, gives
more adjustment range than required and therefore, a
considerable portion of the potentiometer rotation is not fully
utilized. Typical values of series resistors that may be placed
at either end of the potentiometer, see Figure 5B, to optimize
its utilization range are given in the table “Electrical
Specifications for Equipment Design” shown on third page of
this data sheetAn alternate system is shown in Figure 5C.
Thiscircuit uses only one additional resistor of approximately
thevalue shown in the table.For potentiometers,in whichthe
resistancedoes not drop to 0Ω at either end of rotation, a
value of resistance 10% lower than the values shown in the
table should be used.

Typical Applications

On/Off Touch Switch

The on/off touch switch shown in Figure 6 uses the
CA3240E to sense small currents flowing between two
contactpoints on a touch plate consisting of a PC board
metallization “grid”. When the “on” plate is touched, current
flows between t he two halves of the gr id causing a positive

shift in the output voltage (Terminal7) of the CA3240E.
These positive transitions are fed into the CA3059, which is
used as a latching circuit and zero-crossing TRIAC driver.
When a positive pulse occurs at Terminal7 of the CA3240E,
the TRIAC is t urned on and held on by the CA3059 and its
associatedpositive feedback circuitry (51kΩ resistor and
36kΩ/42kΩ voltage divider). When t he positive pulse occurs
at Terminal 1 (CA3240E), the TRIAC is turned off and held
off in a similar manner. Note that power for the CA3240E is
supplied by the CA3059 internal power supply.

The advantage of using the CA3240E in this circuit is that it
can sense the small currentsassociated with skin
conductionwhile allowing sufficiently high circuit impedance
to provide protection against electrical shock.

Dual Level Detector (Wi ndo w Comparator)

Figure 7 illustratesa simple dual liquid level detector using
the CA3240E as the sensing amplifier. This circuit operates
on the principle that most liquids contain enough ions i n
solution to sustain a small amount of current flow between
two electrodessubmersed in the liquid.The current, induced
by an 0.5V potential applied between t wo halves of a PC
board grid, is convertedto a voltage level by the CA3240E in
a circuit similar to t hat of the on/off touch switch shown in
Figure 6. The changes in voltage for both t he upper and
lowerlevel sensors are processed by the CA3140to activate
an LED whenever the liquid level is above the upper sensor
or below the lower sensor.

Constant-Voltage/Constant-Current Power Supply

The constant-voltage/constant-current power supply shown
in Figure 8 uses the CA3240E1 as a voltage-error and
current-sensing amplifier. The CA3240E1 is i deal for this
applicationbecause its input common-mode voltage range
includes ground, allowing the supply to adjust from 20mV to
25V without requiring a negative supply voltage. Also, the
ground reference capability of the CA3240E1allows it to
sense the voltageacross the 1Ω current-sensing resistor in
the negative output lead of the power supply. The CA3086
transistor array functions as a reference for both constant­voltageand constant-current limiting. The 2N6385 power
Darlingtonis used as the pass element and may be required
to dissipate as much as 40W. Figure 9 shows the transient
response of the supply during a 100mA to 1A load transition.

Precision Differential Amplifier

Figure 10 shows the CA3240E in the classical precision
differentialampl ifier circuit.The CA3240Eis ideallysuited for
biomedicalapplicationsbecause of its extremely high input
impedance. To insure patientsafety, an extremely high
electrode series resistance is required to limit any current
that might result in patient discomfort in the event of a fault
condition.In this case, 10MΩ resistors have been used to
limit the current to less than 2µA without affecting the
performanceof the circuit. Figure 11shows a typical
electrocardiogram waveform obtained with t his circuit.

7

CA3240, CA3240A

V+

3
(5)

13(9)

12(10)

4

V-

1(7)

CA3240

2(6)

14(8)

10kΩ

FIGURE 5A. BASIC FIGURE 5B. IMPROVE D RESOLUTION

FIGURE 5C. SIMPLER IMPROVED RESOLUTION

NOTE:

11. See Electrical Specification Table for value of R.

FIGURE 5. THREE OFFSET-VOLTAGE NULLING METHODS, (CA3240AE1 ONLY)

(NOTE 11)

CA3240

10kΩ

V+

CA3240

R(NOTE11) R

V+

V-

R

10kΩ

(NOTE 11)

V-

44M

“ON”

“OFF”

0.01µF

0.01µF

5.1M

1M

1M

6

+6V

5

3

2

1M

+6V

8

-

1/2

CA3240

+

+

1/2

CA3240

-

4

44M

NOTE:

12. At 220V operation,TRIAC should be T2300D, R

+6V

51K

7

1

=18K,5W.

S

36K

1N914

42K

1N914

+6V SOURCE

5

13

9

CA3059

10
11

7

2

+

100µF (16V)

-

FIGURE 6. ON/OFF TOUCH SWITCH

10K (2W)

R

(NOTE 12)

S

8

4

12K

MT

120V/220V
AC
60Hz/50Hz

40W
120V LIGHT

2

T2300B (NOTE 12)

G

MT

1

COMMON

8

HIGH

LEVEL

8.2K

LOW

LEVEL

100K

+15V

100K

240K

2

3

(0.5V)

5

6

CA3240, CA3240A

12M

+15V

0.1µF

8

-

1/2
CA3240
+

+

1/2
CA3240

-

4

12M

FIGURE 7. DUAL LEVEL DETECTER

1

33K

3

160K

100K

2

100K

7

+15V

7

+

CA3140

-

4

0.1µF

6

680Ω

LED ON WHEN
LIQUID OUTSIDE
OF LIMITS

LED

2N6385
DARLINGTON

V

= 30V

I

CA3086E
TRANSISTOR

ARRAY

+

2000µF

-

50V

2.7K

V

O

180K

82K

I

O

+

500

-

µF

V+

2

3

75Ω

3K

1

2.2K

10
11

9
8
7

6

2
1

3
5

4

100Ω

+

5µF
16V

-

12

1K

12

14

13

13

-

1/2

CA3240E1

+

4

100K

100K

100K

820Ω 680K

1

2

50K

0.056µF

7

6

10K

V+

9

-

1/2

CA3240E1

+

1N914

10

CHASSIS GROUND

VORANGE = 20mV TO 25V
LOAD REGULATION:

VOLTAGE <0.08%
CURRENT <0.05%

6.2K

1Ω
1W

OUTPUT HUM AND NOISE ≤ 150µV

SINE REGULATION ≤ 0.1%/V
IORANGE = 10mA - 1.3A

(10MHz BANDWIDTH)

O

100K

RMS

FIGURE 8. CONS TANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY

9

CA3240, CA3240A

Top Trace: Output Voltage;

500mV/Div ., 5µs/Div.

Bottom Trace: Collector Of Load Switching Transistor

Load = 100mA to 1A; 5V/Div.,5µs/Div.

FIGURE 9. TRANSIENT RESPONSE

TWO COND.
SHIELDED
CABLE

10M

GAIN
CONTROL

10M

+15V

2000pF

2000pF

0.1µF

1

7

0.1µF

100K 1%

2000pF

+15V

1%

5.1K

5.1K
1%

2

3

FREQUENCY RESPONSE (-3dB) DC TO 1MHz
SLEW RATE = 1.5V/µs
COMMON MODE REJ: 86dB
GAIN RANGE: 35dB TO 60dB

7

CA3140

4

-15V

3

2

100K

3.9K

6

5

8

+
1/2
CA3240

-

100K 1%

100K 1%

-

1/2
CA3240

+

4

-15V

FIGURE 10. PRECISION DIFFERENTIAL AMPLIFIER

0.1µF
OUTPUT

6

2K

0.1µF

10

CA3240, CA3240A

Vertical: 1.0mV/Div.

AmplifierGain = 100X
Scope Sensitivity = 0.1V/Div.

Horizontal:>0.2s/Div.(Uncal)

FIGURE 11. TYPICAL ELECTROCARIOGRAM WAVEFORM

0.015µF

100K

+15V

8

-

1/2
CA3240E

+

+
1/2
CA3240E

-

4

-15V
100K

0.015µF

C30809
PHOTO
DIODE

C30809
PHOTO
DIODE

+15V

5.1K

1.3
K

13K

2

3

5

6

FIGURE 12. DIFFERE NTIAL LIGHT DETECTOR

Differential Light Detector

In the circuit shown in Figure 12, the CA3240E converts the
current from two photo diodes to voltage,and applies 1V of
reverse bias to the diodes. The voltages from the CA3240E
outputsare subtractedin the second stage (CA3140) so that

+15V

1

2K

3

200K

2

2K

7

7

+

CA3140

-

4

-15V

200k

6

OUTPUT

only the difference is amplified. In this manner, the circuit
can be used over a wide range of ambient light conditions
without circuit component adjustment. Also, when used with
a light source, the circuit will not be sensitiveto changes in
light level as the source ages.

11

Typical Performance Curves

CA3240, CA3240A

RL=2kΩ

125

100

75

50

OPEN LOOP VOLTAGEGAIN (dB)

25

TA=-40oC

25oC

85oC

2520151050

SUPPLY VOLTAGE (V)

RL=2kΩ
C

=100pF

L

20
10

TA=-40oC

85oC

GAIN BANDWIDTH PRODUCT (MHz)

1

0 5 10 15 20 25

25oC

SUPPLYVOLTAGE (V)

FIGURE 13. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE FIGURE 14. GAINBANDWIDTHPRODUCTvs SUPPLYVOLTAGE

20

=2kΩ

R

L

= 100pF

C

L

15

25oC

10

SLEW RATE (V/µs)

5

TA=-40oC

85oC

10

RL= ∞

9

8

7

6

5

FORBOTHAMPS

4

TOTAL SUPPLY CURRENT (mA)

3

TA=-40oC

25oC

85oC

0

0

5101520

SUPPLYVOLTAGE (V)

25

2

0 5 10 15 20

SUPPLY VOLTAGE (V)

FIGURE 15. SLEW RATE vs SUPPLY VOLTAGE FIGURE16. QUIESCENTSUPPL YCURRENTvsSUPPLYVOLTAGE

SUPPLY VOLTAGE: VS= ±15V
T

=25oC

A

25

)

P-P

20

15

10

OUTPUT VOLTAGE (V

5

0
10K 100K

FREQUENCY (Hz)

1M 4M

FIGURE 17. MAXIMUMOUTPUTVOLTAGE SWING vs

FREQUENCY

120

SUPPLY VOLTAGE: VS= ±15V
T

=25oC

A

100

80

60

40

20

COMMON MODE REJECTION RATIO (dB)

0

10

1

2

10

3

10

10

FREQUENCY (Hz)

4

5

10

FIGURE 18. COMMON MODE REJECTION RATIO vs

FREQUENCY

25

6

10

7

10

12

Typical Performance Curves (Continued)

CA3240, CA3240A

1000

SUPPLY VOL TAGE: VS= ±15V
T

=25oC

A

100

10

1

EQUIVALENT INPUT NOISE VOLTAGE(nV/√Hz)

1

1

10

RS=100Ω

2

10

FREQUENCY (Hz)

10

3

4

10

FIGURE 19. EQUIVALENTINPUTNOISEVOLTAGE vs

FREQUENCY

TA=25oC

12

10

8

VS= ±15V
ONE AMPLIFIER OPERATING

SUPPLY VOLTAGE: VS= ±15V
T

=25oC

A

100

80

60

40

20

POWER SUPPLY REJECTION RATIO (dB)

5

10

10

1

-PSRR

2

10

10

POWER SUPPLY
REJECTION RATIO = ∆V

+PSRR

3

4

10

FREQUENCY (Hz)

/∆ V

IO

S

5

10

6

10

7

10

FIGURE 20. POWER SUPPLY REJECTION RATIO vs

FREQUENCY

TA=25oC

17.5
VS= ±15V

15

12.5

RL= ∞

6

PER AMP

4

OUTPUT SINK CURRENT (mA)

2

0

-15 -10 -5 0 5 10 15
OUTPUT VOLTAGE (V)

10

7.5

SUPPLY CURRENT (mA)

PER AMP (DOUBLE FOR BOTH)

5

2.5

-15 -10 -5 0 5 10 15
OUTPUT VOLTAGE (V)

FIGURE 21. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE FIGURE 22. SUPPLY CURRENT vs OUTPUT VOLTAGE

1000

TA=25oC

140

130

120

110

CROSSTALK (dB)

100

90

80

0.1 1 10

AMP A → AMP B
AMP B → AMP A
V

= ±15V

S

V

=5V

O

RMS

FREQUENCY (Hz)

)

16

Q

15,

1

2

10

3

10

OUTPUT STAGE TRANSISTOR (Q

V- = 0V

=25oC

T

A

100

10

SATURATION VOLTAGE (mV)

1.0

0.01 0.1

V+ = +5V

LOAD (SINKING) CURRENT (mA)

+15V

1.0 10

+30V

FIGURE 23. CROSSTALK vs FREQUENCY FIGURE24. VOLTAGE ACROSS OUTPUT TRANSISTORS Q

AND Q16vs LOAD CURRENT

13

15

Typical Performance Curves (Continued)

CA3240, CA3240A

RL= ∞

0

-0.5

-1

-1.5

-2

-2.5

INPUT AND OUTPUT VOLTAGE

-3

REFERENCED TOTERMINAL V+(V)

0 5 10 15 20 25

OUTPUT VOLTAGE (+VO)
COMMON MODE VOLTAGE (+V

TA=85oC

TA=25oC

TA=-40oC

SUPPLY VOLTAGE (V)

TA=-40oC

)

ICR

TA=25oC

TA=85oC

INPUT AND OUTPUT VOLTAGE

RL= ∞

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

REFERENCED TO TERMINAL V- (V)

OUTPUT VOLTAGE (-VO)
COMMON MODE VOLTAGE (-V

TA=-40oCTO85oC

TA=85oC

TA=-40oC

0510152025

SUPPLY VOLTAGE (V)

ICR

TA=25oC

FIGURE 25A. FIGURE 25B.

FIGURE 25. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE

SUPPLY VOLTAGE: VS= ±15V

=25oC, RL=2kΩ,CL= 100pF

T

A

10

8
6
4
2
0

-2

INPUT VOLTAGE (V)

-4

-6

-8

-10

0.1

10mV

10mV

2468

1.0 10

TIME (µs)

1mV

10mV

FOLLOWER
INVERTING

1mV

10mV

1mV

2468

1mV

10kΩ

+15V

+
CA3240

-

-15V

0.05µF

0.1µF

100pF

0.1µF

2kΩ

)

SIMULATED

LOAD

2kΩ

FIGURE 26A. SE TTLING TIME vs INPUT VOLTAGE FIGURE 26B. TEST CIRCUIT (FOLLOWER)

5kΩ

+15V

5kΩ

200Ω

4.99kΩ

D

1

1N914 1N914

-

CA3240

+

-15V

D

2

0.1µF

0.1µF

SETTLING POINT

100pF

5.11kΩ

SIMULATED

LOAD

2kΩ

FIGURE 26C. TEST CIRCUIT (INVERTING)

FIGURE 26. INPUT VOLTAGE vs SETTLING TIME

14

Typical Performance Curves (Continued)

CA3240, CA3240A

10K

VS= ±15V

1K

100

INPUT CURRENT (pA)

10

1

-60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE(

o

C)

VS= ±15V
T

=25oC

A

100

80

60

40

20

OPEN LOOP VOLTAGE GAIN (dB)

0

1

2

10

10

10310410510610710

FREQUENCY (Hz)

PHASE

RL=2kΩ,
C

GAIN

= 100pF

L

RL=2kΩ,
C

L

FIGURE 27. INPUT CURRENT vs TEMPERATURE FIGURE 28. OPENLOOPVOLTAGE GAINANDPHASEvs

FREQUENCY

=0pF

-75

-90

-105

-120

-135

-150

OPEN LOOP PHASE (DEGREES)

8

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