Datasheet CA3183A, CA3146A, CA3183 Datasheet (Intersil Corporation)

TM

CA3146, CA3146A, CA3183, CA3183A

[ /Title
(CA31
46,
CA314
6A,
CA318
3,
CA318
3A)
/Sub-
ject
(High-
Volt-
age
Tran-
sistor
Arrays
)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
five,
transis-
tor
array,
low
cost
NPN,
40V,
50ma
75ma,
mhz ft,
high
volt-

Data Sheet April 2000

High-Voltage Transistor Arrays

The CA3146A, CA3146, CA3183A, and CA3183 are general
purpose high voltage silicon NPN transistor arrays on a
common monolithic substrate.

TypesCA3146AandCA3146 consist of five transistors with two
of the transistors connected to form a differentially connected
pair.These types are recommended for low power applications
in the DC through VHF range.(CA3146A and CA3146 are high
voltage versions of the popularpredecessor type CA3046.)

Types CA3183A and CA3183 consist of five high current
transistors with independent connections for each transistor.
In addition two of these transistors (Q

and Q2) are matched

1

at low current (i.e., 1mA) for applications where offset
parameters are of special importance. A special substrate
terminal is also included for greater flexibility in circuit
design. (CA3183A and CA3183 are high voltage versions of
the popular predecessor type CA3083.)

The types with an “A” suffix are premium versions of their
non-“A” counterparts and feature tighter control of
breakdown voltages making them more suitable for higher
voltage applications.

For detailed application information, see companion
Application Note AN5296 “Application of the CA3018
Integrated Circuit Transistor Array.”

Ordering Information

PART
NUMBER
(BRAND)

CA3146AE -40 to 85 14 Ld PDIP E14.3
CA3146AM

(3146A)
CA3146E -40 to 85 14 Ld PDIP E14.3
CA3146M

(3146)
CA3146M96

(3146)
CA3183AE -40 to 85 16 Ld PDIP E16.3
CA3183AM96

(3183A)
CA3183E -40 to 85 16 Ld PDIP E16.3
CA3183M

(3183)
CA3183M96

(3183)

TEMP.

RANGE

(oC) PACKAGE

-40 to 85 14 Ld SOIC M14.15

-40 to 85 14 Ld SOIC M14.15

-40 to 85 14 Ld SOIC Tape and
Reel

-40 to 85 16 Ld SOIC Tape and
Reel

-40 to 85 16 Ld SOIC M16.15

-40 to 85 16 Ld SOIC Tape and
Reel

PKG.

NO.

M14.15

M16.15

M16.15

File Number 532.5

Features

• Matched General Purpose Transistors

-V

Match . . . . . . . . . . . . . . . . . . . . . . . . ±5mV (Max)

BE

• Operation from DC to 120MHz (CA3146, CA3146A)

• Low Noise Figure . . . . . . . . . . 3.2dB (CA3146, CA3146A)

• High I

. . . . . . . . . . . . 75mA (Max) (CA3183, CA3183A)

C

Applications

• General Use in Signal Processing Systems in DC through
VHF Range

• Custom Designed Differential Amplifiers

• Temperature Compensated Amplifiers

• Lamp and Relay Drivers (CA3183, CA3183A)

• Thyristor Firing (CA3183, CA3183A)

Pinouts

CA3146, CA3146A (PDIP, SOIC)

TOP VIEW

DIFF.

PAIR

CA3183, CA3183A (PDIP, SOIC)

SUBSTRATE

1

2

3

4

5

6

7

1

2

3

4

5

6

7

8

TOP VIEW

Q

Q

3

Q

1

Q

2

Q

3

Q

1

2

14

Q

5

SUBSTRATE

13

12

11

Q

4

10

9

8

16

15

14

Q

13

5

12

11

Q

10

4

9

1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

CA3146, CA3146A, CA3183, CA3183A

Absolute Maximum Ratings Thermal Information

Collector-to-Emitter Voltage (V

CA3146A, CA3183A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V

CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30V

Collector-to-Base Voltage (V

CA3146A, CA3183A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50V

CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V

Collector-to-Substrate Voltage(V

CA3146A, CA3183A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50V

CA3146, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V

Emitter to Base Voltage (V

EBO

Collector Current

CA3146A, CA3146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA

CA3183A, CA3183 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75mA

Base Current (IB) - CA3183A, CA3183 . . . . . . . . . . . . . . . . . . . 20mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The collector of each transistor is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more
negative than any collector voltage in order to maintain isolation between transistors, and to provide for normal transistor action. To avoid
undesired coupling between transistors, the substrate terminal should be maintained at either DC or signal (AC) ground. A suitable bypass
capacitor can be used to establish a signal ground.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal
resistances to calculate the junction temperature.

)

CEO

)

CBO

, Note 1)

CIO

) all types. . . . . . . . . . . . . . . . . . . . .5V

Thermal Resistance (Typical, Note 2) θJA (oC/W)

14 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 100

14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 200

16 Ld PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . 95

16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Power Dissipation (Any One Transistor, Note 3)

CA3146A, CA3146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mW

CA3183A, CA3183. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW

Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . . . 175oC

Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC

Maximum Storage Temperature Range (all types) . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications CA3146 Series

TEST CONDITIONS TYPICAL

PERF .

CURVE

PARAMETER SYMBOL

DC CHARACTERISTICS FOR EACH TRANSISTOR

Collector-to-Base

V

(BR)CBOIC

= 10µA, IE = 0 - 40 72 - 50 72 - V

Breakdown Voltage
Collector-to-Emitter

V

(BR)CEOIC

= 1mA, IB = 0 - 30 56 - 40 56 - V

Breakdown Voltage
Collector-to-Substrate

Breakdown Voltage
Emitter-to-Base Breakdown V oltage V
Collector-Cutoff Current I

Collector-Cutoff Current I
DC Forward-Current Transfer

Ratio

V

(BR)CIOICI

(BR)EBOIE

CEO

CBO

h

FE

= 10µA, IB = 0,

IE = 0

= 10µA, IC = 0 - 5 7 - 5 7 - V

VCE = 10V, IB = 0 1 - See

VCB = 10V, IE = 0 2 - 0.002 100 - 0.002 100 nA
VCE = 5V, IC = 10mA 3 - 85 - - 85 - ­VCE = 5V, IC = 1mA 3 30 100 - 30 100 - -

VCE = 5V, IC = 10µA3 -90--90-­Base-to-Emitter Voltage V
Collector-to-Emitter

V

CE SATIC

VCE = 3V, IC = 1mA 4 0.63 0.73 0.83 0.63 0.73 0.83 V

BE

= 10mA, IB = 1mA 5 - 0.33 - - 0.33 - V

Saturation Voltage

DC CHARACTERISTICS FOR TRANSISTORS Q1 AND Q2 (As A Differential Amplifier)

Magnitude of Input Offset
Voltage |V

BE1

- V

BE2

|

Magnitude of Base-to-Emitter
Temperature Coefficient

|VIO|VCE = 5V, IE = 1mA 6, 7 - 0.48 5 - 0.48 5 mV

∆V

----------------

∆T

VCE = 5V, IE = 1mA - - 1.9 - - 1.9 - mV/oC

BE

FIG. NO.

- 40 72 - 50 72 - V

CA3146 CA3146A

5 - See

Curve

Curve

UNITSTA = 25oC MN TYP MAX MIN TYP MAX

5 µA

2

CA3146, CA3146A, CA3183, CA3183A

Electrical Specifications CA3146 Series (Continued)

TEST CONDITIONS TYPICAL

PARAMETER SYMBOL

Magnitude of VIO(V
Temperature Coefficient

Magnitude of Input Offset Current
|I

- I

IO1

| (CA3146AE and

IO2

CA3146E Only)

DYNAMIC CHARACTERISTICS

Low Frequency Noise Figure NF f = 1kHz, V

Low-Frequency, Small-Signal
Equivalent-Circuit Characteristics:

Forward-Current Transfer
Ratio

Short-Circuit Input Impedance h

Open-Circuit Output Impedance h

Open-Circuit Reverse Voltage
Transfer Ratio

Admittance Characteristics:

Forward Transfer Admittance Y

Input Admittance Y

Output Admittance Y

Reverse Transfer

Admittance
Gain-Bandwidth Product f
Emitter-to-Base Capacitance C
Collector-to-Base Capacitance C
Collector-to-Substrate

Capacitance

BE1

- V

BE2

)

∆V

------------- -

∆T

I

IO

IO

VCE = 5V,
IC1 = IC2 = 1mA

VCE = 5V,
I

= IC2 = 1mA

C1

I

= 100µA, Source

C

CE

Resistance = 1kΩ

h

f = 1kHz, VCE = 5V,

FE

IC = 1mA
f = 1kHz, VCE = 5V,

IE

IC = 1mA
f = 1kHz, VCE = 5V,

OE

IC = 1mA

h

f = 1kHz, VCE = 5V,

RE

IC = 1mA

f = 1MHz, VCE = 5V,

FE

IC = 1 mA
f = 1MHz, VCE = 5V,

IE

IC = 1 mA
f = 1MHz, VCE = 5V,

OE

IC = 1 mA

Y

C

f = 1MHz, VCE = 5V,

RE

IC = 1 mA
VCE = 5V, IC = 3mA 17 300 500 - 300 500 - MHz

T

VEB = 5V, IE = 0 18 - 0.70 - - 0.70 - pF

EB

VCB = 5V, IC = 0 18 - 0.37 - - 0.37 - pF

CB

VCl = 5V, IC = 0 18 - 2.2 - - 2.2 - pF

Cl

= 5V,

CA3146 CA3146A

PERF .

CURVE

FIG. NO.

- - 1.1 - - 1.1 - µV/oC

8 - 0.3 2 - 0.3 2 µA

10 - 3.25 - - 3.25 - dB

12 - 100 - - 100 - -

12 - 3.5 - - 2.7 - kΩ

12 - 15.6 - - 15.6 - µS

12 - 1.8 x

10

13 - 31-

- - 1.8 x

-4

10

-4

- - 31-j1.5 - mS

--

j1.5

14 - 0.3 +

j0.04

15 - 0.001

+ j0.03

16 See

Curve

- - 0.35 +
j0.04

- - 0.001

+ j0.03

See

Curve

-mS

-mS

UNITSTA = 25oC MN TYP MAX MIN TYP MAX

mS

Electrical Specifications CA3183 Series

TEST CONDITIONS TYPICAL

PARAMETER SYMBOL

DC CHARACTERISTICS FOR EACH TRANSISTOR

Collector-to-Base
Breakdown Voltage

Collector-to-Emitter
Breakdown Voltage

Collector-to-Substrate
Breakdown Voltage

Emitter-to-Base
Breakdown Voltage

Collector-Cutoff Current I

V

(BR)CBOIC

V

(BR)CEOIC

V

(BR)ClOICI

V

(BR)EBOIE

CEO

3

= 100µA, IE = 0 - 40 - - 50 - - V

= 1mA, IB = 0 - 30 - - 40 - - V

= 100µA, IB = 0,

IE = 0

= 500µA, IC = 0 - 5 - - 5 - - V

VCE = 10V, IB = 0 19 - - 10 - - 10 µA

CA3183 CA3183A

PERF .

CURVE

FIG. NO.

UNITSTA = 25oC MIN TYP MAX MIN TYP MAX

-40--50--V

CA3146, CA3146A, CA3183, CA3183A

Electrical Specifications CA3183 Series (Continued)

TEST CONDITIONS TYPICAL

PERF .

CURVE

PARAMETER SYMBOL

Collector-Cutoff Current I
DC Forward-Current

Transfer Ratio
Base-to-Emitter Voltage V

Collector-to-Emitter
Saturation Voltage

V

(Note 3)

CBO

h

FE

BE

CE SAT

= 25oC MIN TYP MAX MIN TYP MAX

A

VCB = 10V, IE = 0 20 - - 1 - - 1 µA
VCE = 3V, IC = 10mA 21, 22 40 - - 40 - - ­VCE = 5V, IC = 50mA - 40 - - 40 - - ­VCE = 3V, IC = 10mA 23 0.65 0.75 0.85 0.65 0.75 0.85 V
IC = 50mA, IB = 5mA 24 - 1.7 3.0 - 1.7 3.0 V

FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER)

Absolute Input Offset

|VIO|VCE = 3V, IC = 1mA 25 - 0.47 5 - 0.47 5 mV

Voltage
Absolute Input Offset

|IIO|VCE = 3V, IC = 1mA 26 - 0.78 2.5 - 0.78 2.5 µA

Current

FIG. NO.

Typical Performance Curves DC Characteristics - CA3146 Series

CA3183 CA3183A

UNITST

3

10

IB = 0

2

10

10

1

-1

10

-2

10

COLLECTOR CUTOFF CURRENT (nA)

-3

10

0 25 50 75 100 125

FIGURE 1. I

160

140

120

100

80

60

40

DC FORWARD CURRENT TRANSFER RATIO

20

0.01 1 10

vs TEMPERATURE FOR ANY TRANSISTOR FIGURE 2. I

CEO

VCE = 5V

VCE = 10V

VCE = 5V

25oC

-55oC

o

C)

TEMPERATURE (

TA = 125oC

0.1

COLLECTOR CURRENT (mA)

2

10

IE = 0

10

1

-1

10

-2

10

-3

10

COLLECTOR CUTOFF CURRENT (nA)

-4

10

0 25 50 75 100 125

0.9

0.8

0.7

0.6

0.5

BASE TO EMITTER VOLTAGE (V)

0.4

-75

VCB = 10

VCB = 5

vs TEMPERATURE FOR ANY TRANSISTOR

CBO

VCE = 5V

-50 -25 0 25 50 75 100 125

VCB = 15

TEMPERATURE (

IE = 3mA

IE = 1mA

TEMPERATURE (

o

C)

o

C)

FIGURE 3. hFE vs IC FOR ANY TRANSISTOR FIGURE 4. VBE vs TEMPERATURE FOR ANY TRANSISTOR

4

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves DC Characteristics - CA3146 Series (Continued)

TA = 25oC

1.50

1.25

1.0
hFE = 10

0.75

0.50

COLLECTOR TO EMITTER

SATURATION VOLTAGE (V)

0.25

0102030

COLLECTOR CURRENT (mA)

FIGURE 5. V

0.8
VCE = 5V

= 25oC

T

A

0.7

0.6

vs IC FOR ANY TRANSISTOR FIGURE 6. VIO vs TEMPERATURE FOR Q1 AND Q

CE SAT

5

VCE= 5V

4

3

2

0.75

0.50

OFFSET VOLTAGE (mV)

0.25

0

40

-75 -50 -25 0 25 50 75 100 125
TEMPERATURE (

o

IE= 10mA

IE= 1mA

IE= 0.1mA

C)

2

10

VCE = 5V

= 25oC

1.0

T

A

3

2

(mV)

2

AND Q

1

0.1

0.5

- V

|V

BASE TO EMITTER VOLTAGE (V)

0.4

0.01 0.1 1.0 10

BE1

EMITTER CURRENT (mA)

BE2

|

FIGURE 7. VBE AND VIO vs IE FOR Q1 AND Q

1

INPUT OFFSET CURRENT (µA)

INPUT OFFSET VOLTAGE Q

0

2

0.01

0.01 0.1 1.0 10
COLLECTOR CURRENT (mA)

FIGURE 8. IIO vs IC FOR Q1 AND Q

Typical Performance Curves Dynamic Characteristics (For Any Transistor) - CA3146 Series

VCE = 5V
R

= 500Ω

S

T

= 25oC

A

20

15

10

NOISE FIGURE (dB)

5

0

0.01 0.1 1.0

f = 0.1kHz

f = 1kHz

f = 10kHz

COLLECTOR CURRENT (mA)

VCE = 5V

= 1000Ω

R

S

T

= 25oC

A

20

15

10

NOISE FIGURE (dB)

5

0

0.01 0.1 1.0

f = 0.1kHz

f = 1kHz

f = 10kHz

COLLECTOR CURRENT (mA)

2

FIGURE 9. NF vs I

AT RS = 500Ω FIGURE 10. NF vs IC AT RS = 1kΩ

C

5

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves Dynamic Characteristics (For Any Transistor) - CA3146 Series (Continued)

30

VCE = 5V
R

= 10000Ω

S

25

20

15

10

NOISE FIGURE (dB)

= 25oC

T

A

f = 0.1kHz

f = 1kHz

f = 10kHz

5

0

0.01 0.1 1.0
COLLECTOR CURRENT (mA)

FIGURE 11. NF vs IC AT RS = 10kΩ FIGURE 12. hFE, hIE, hOE, hRE vs I

)

FE

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25oC, VCE = 5V, IC = 1mA

40

) (mS)

30

FE

20

10

g

FE

100

VCE = 5V

10

f = 1kHz
T

= 25oC

A

hFE = 100

= 2.7kΩ

h

IE

h

= 1.88 x 10

RE

hOE = 15.6µS

AT

-4

1mA

1.0

h

NORMALIZED h PARAMETERS

RE

0.1

0.01 0.1 1.0 10
COLLECTOR CURRENT (mA)

C

6

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25oC, VCE = 5V, IC = 1mA

5

)

IE

) (mS)

IE

4

3

h

OE

h

FE

h

IE

b

IE

0

OR SUSCEPTANCE (b

-10

-20

FORWARD TRANSFER CONDUCTANCE (g

0.1 10 100

1.0

b

FE

FREQUENCY (MHz)

FIGURE 13. yFE vs FREQUENCY FIGURE 14. yIE vs FREQUENCY

COMMON EMITTER CIRCUIT, BASE INPUT

6

)

OUTPUT CONDUCTANCE (g

TA = 25oC, VCE = 3V, IC = 1mA

5

OE

) (mS)

OE

4

3

2

1

OR SUSCEPTANCE (b

0

0.1 10 1001.0
FREQUENCY (MHz)

2

INPUT CONDUCTANCE (g

OR SUSCEPTANCE (b

1

g

0

0.1 10 100

IE

1.0
FREQUENCY (MHz)

)

RE

b

OE

COMMON EMITTER CIRCUIT, BASE INPUT
TA = 25oC, VCE = 5V, IC = 1mA

) (mS)

RE

0

gREIS SMALL AT FREQUENCIES

-0.5

LESS THAN 500MHz

b

RE

-1.0

-1.5

g

OE

OR SUSCEPTANCE (b

-2.0

REVERSE TRANSFER CONDUCTANCE (g

1 10010

FREQUENCY (MHz)

FIGURE 15. FIGURE 15. yOE vs FREQUENCY FIGURE 16. FIGURE 16. yRE vs FREQUENCY

6

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves Dynamic Characteristics (For Any Transistor) - CA3146 Series (Continued)

VCE = 5V

= 25oC

T

1000

GAIN BANDWIDTH PRODUCT (MHz)

A

900
800
700
600
500
400
300
200
100

01234567891011121314

COLLECTOR CURRENT (mA)

FIGURE 17. fT vs I

C

CAPACITANCE (pF)

Typical Performance Curves DC Characteristics - CA3183 Series

VCE = 10V

1

-1

10

TA = 25oC

4

3

2

1

0

012345678910

C

EB

BIAS VOLTAGE (V)

FIGURE 18. CEB, CCB, CCI vs BIAS VOLTAGE

-1

10

VCB = 10V

-2

10

C

CI

C

CB

11 12 13 14

-2

10

-3

10

COLLECTOR CUTOFF CURRENT (nA)

-4

10

-50 -25 0 25 50 75 100
TEMPERATURE (oC)

FIGURE 19. I

125

)

FE

100

75

50

25

TRANSFER RATIO (h

DC FORWARD CURRENT

0

-50 -25 0 25 50 75 100

vs TEMPERATURE FOR ANY TRANSISTOR FIGURE 20. I

CEO

VCE = 3V

IC = 0.1mA

IC = 1mA

IC = 10mA

TEMPERATURE (

o

C)

-3

10

COLLECTOR CUTOFF CURRENT (nA)

-4

10

-50 -25 0 25 50 75 100
TEMPERATURE (

vs TEMPERATURE FOR ANY TRANSISTOR

CBO

TA = 25oC

100

90

)

FE

80

70

60

TRANSFER RATIO (h

DC FORWARD CURRENT

50

40

0.1 1.0 10
COLLECTOR CURRENT (mA)

o

C)

VCE = 10V

VCE = 3V

FIGURE 21. hFE vs TEMPERATURE FOR ANY TRANSISTOR FIGURE 22. hFE vs IC FOR ANY TRANSISTOR

7

CA3146, CA3146A, CA3183, CA3183A

Typical Performance Curves DC Characteristics - CA3183 Series (Continued)

TA = 25oC
h

= 10

0.9

0.8
TA = 70oC

0.7

0.6

0.5

0.4

BASE TO EMITTER VOLTAGE (V)

0.3

0.1 1.0 10

TA = 25oC

COLLECTOR CURRENT (mA)

TA = 0oC

COLLECTOR TO EMITTER

FE

1.0

SATURATION VOLTAGE (V)

0.1
10 100

COLLECTOR CURRENT (mA)

FIGURE 23. VBE vs IC FOR ANY TRANSISTOR FIGURE 24. V

V

= 3V

CE

1.0
TA = 70oC

0.1

ABSOLUTE INPUT - OFFSET VOLTAGE (mV)

0.1 1.0 10

TA = 25oC

COLLECTOR CURRENT (mA)

TA = 0oC

1.0

ABSOLUTE INPUT - OFFSET CURRENT (µA)

0.1

VCE = 3V

= 25oC

T

A

0.1 1.0 10

vs IC FOR ANY TRANSISTOR

CE SAT

COLLECTOR CURRENT (mA)

FIGURE 25. |VIO|vsICFOR DIFFERENTIAL AMPLIFIER (Q1AND Q2) FIGURE 26. |IIO| vs IC FOR DIFFERENTIAL AMPLIFIER (Q1 AND Q2)

8

CA3146, CA3146A, CA3183, CA3183A

Dual-In-Line Plastic Packages (PDIP)

N

D1

E1

-B-

-C-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

1 2 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols aredefined inthe “MOSeries SymbolList” inSection 2.2of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpen-

e

dicular to datum .

A

-C-

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1maximumdimensionsdonotincludedambarprotrusions.Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -

1.14mm).

E14.3 (JEDEC MS-001-AA ISSUE D)

14 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N14 149

NOTESMIN MAX MIN MAX

Rev. 0 12/93

9

CA3146, CA3146A, CA3183, CA3183A

Dual-In-Line Plastic Packages (PDIP)

N

D1

E1

-B-

-C-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

B1

1 2 3 N/2

-A­D

e

B

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH.Incase of conflict betweenEnglishand
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seatedin JE­DEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with theleads constrained to be perpendic-

e

A

ular to datum .

-C-

7. eBand eCare measured atthe leadtips withthe leadsunconstrained.
eC must be zero or greater.

8. B1 maximum dimensions do notinclude dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 ­D 0.735 0.775 18.66 19.68 5

D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC ­e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N16 169

NOTESMIN MAX MIN MAX

Rev. 0 12/93

10

CA3146, CA3146A, CA3183, CA3183A

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension“E”doesnotincludeinterleadflashorprotrusions.Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M14.15 (JEDEC MS-012-AB ISSUE C)

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6

N14 147

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

11

CA3146, CA3146A, CA3183, CA3183A

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” doesnotinclude interlead flashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”,asmeasured0.36mm (0.014 inch) orgreaterabove
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

A1

C

0.10(0.004)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by descriptiononly.Intersil Corporationreserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

12

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
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TEL: [phone]
FAX: [phone]

ASIA

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Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]