Datasheet CA3130T, CA3130M96, CA3130M, CA3130E, CA3130BT Datasheet (Harris Semiconductor)

SEMICONDUCTOR

3-64

November 1996

CA3130, CA3130A

15MHz, BiMOS Operational Amplifier

with MOSFET Input/CMOS Output

Features

• MOSFET Input Stage Provides:

- Very High Z

I

= 1.5 TΩ (1.5 x 1012Ω) (Typ)

- Very Low I

I

= 5pA (Typ) at 15V Operation

= 2pA (Typ) at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung

0.5V Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either
(or both) Supply Rails

Applications

• Ground-Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Amplifiers

• V oltage Followers (e.g. Follower f or Single-Supply D/A
Converter)

• V oltage Regulators (P ermits Contr ol of Output Voltage
Down to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectifiers

• Photo-Diode Sensor Amplifiers

Description

CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS transistors in the input stage
results in common-mode input-voltage capability down to

0.5V below the negative-supply terminal, an important
attribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the output volt­age to within 10mV of either supply-voltage terminal (at very
high values of load impedance), is employed as the output
circuit.

The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have ter­minals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.

The CA3130A offers superior input characteristics over
those of the CA3130.

Pinouts

CA3131, CA3130A

(PDIP, SOIC)

TOP VIEW

CA3130, CA3130A

(METAL CAN)

TOP VIEW

OFFSET

INV.

NON-INV.

V-

1
2
3
4

8
7
6
5

STROBE
V+
OUTPUT
OFFSET

-

+

NULL
INPUT
INPUT

NULL

TAB

OUTPUT

INV.

V- AND CASE

OFFSET

NON-INV.

V

+

OFFSET

2

4

6

1

3

7

5

8

-

+

STROBE

PHASE
COMPENSATION

NULL

INPUT

INPUT

NULL

Ordering Information

PART NO.

(BRAND)

TEMP.

RANGE

(oC) PACKAGE

PKG.

NO.

CA3130AE

-55 to 125 8 Ld PDIP

E8.3

CA3130AM

(3130A)

-55 to 125 8 Ld SOIC

M8.15

CA3130AM96

(3130A)

-55 to 125 8 Ld SOIC (Note)

M8.15

CA3130AT

-55 to 125 8 Pin Metal Can

T8.C

CA3130BT

-55 to 125 8 Pin Metal Can

T8.C

CA3130E

-55 to 125 8 Ld PDIP

E8.3

CA3130M

(3130)

-55 to 125 8 Ld SOIC

M8.15

CA3130M96

(3130)

-55 to 125 8 Ld SOIC (Note)

M8.15

CA3130T

-55 to 125 8 Pin Metal Can

T8.C

NOTE: Denotes Tape and Reel.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1996

File Number 817.3

3-65

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . 16V

Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA

Output Short-Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 160 N/A

Metal Can Package. . . . . . . . . . . . . . . 170 85

Maximum Junction Temperature (Metal Can Package). . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications T

A

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

PARAMETER SYMBOL

TEST

CONDITIONS

CA3130 CA3130A

UNITSMIN TYP MAX MIN TYP MAX

Input Offset Voltage |V

IO

|V

S

= ±7.5V - 8 15 - 2 5 mV

Input Offset Voltage
Temperature Drift

∆V

IO

/∆T - 10 - - 10 - µV/oC

Input Offset Current |I

IO

|V

S

= ±7.5V - 0.5 30 - 0.5 20 pA

Input Current I

I

VS = ±7.5V - 5 50 - 5 30 pA

Large-Signal Voltage Gain A

OL

VO = 10V

P-P

RL = 2kΩ

50 320 - 50 320 - kV/V
94 110 - 94 110 - dB

Common-Mode
Rejection Ratio

CMRR 70 90 - 80 90 - dB

Common-Mode Input
Voltage Range

V

ICR

0 -0.5 to

12

10 0 -0.5 to

12

10 V

Power-Supply
Rejection Ratio

∆V

IO

/∆VSVS = ±7.5V - 32 320 - 32 150 µV/V

Maximum Output Voltage V

OM

+R

L

= 2kΩ 12 13.3 - 12 13.3 - V

V

OM

-R

L

= 2kΩ - 0.002 0.01 - 0.002 0.01 V

V

OM

+R

L

= ∞ 14.99 15 - 14.99 15 - V

V

OM

-R

L

= ∞ - 0 0.01 - 0 0.01 V

Maximum Output Current I

OM

+ (Source) at VO = 0V 12 22 45 12 22 45 mA

I

OM

- (Sink) at VO = 15V 12 20 45 12 20 45 mA

Supply Current I+ V

O

= 7.5V,

RL = ∞

- 10 15 - 10 15 mA

I+ V

O

= 0V,

RL = ∞

-23-23mA

CA3130, CA3130A

3-66

Electrical Specifications Typical Values Intended Only for Design Guidance, V

SUPPLY

= ±7.5V, TA = 25oC

Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS

CA3130,

CA3130A UNITS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5

or 4 and 1

±22 mV

Input Resistance R

I

1.5 TΩ

Input Capacitance C

I

f = 1MHz 4.3 pF

Equivalent Input Noise Voltage e

N

BW = 0.2MHz, RS = 1MΩ
(Note 3)

23 µV

Open Loop Unity Gain Crossover Frequency
(For Unity Gain Stability ≥47pF Required.) f

T

CC = 0 15 MHz

CC = 47pF 4 MHz

Slew Rate: SR

CC = 0 30 V/µsOpen Loop

Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF,

CL = 25pF,
RL = 2kΩ
(Voltage Follower)

0.09 µsRise Time t

r

Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4V

P-P

)t

S

1.2 µs

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T

A

= 25oC

Unless Otherwise Specified (Note 4)

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage V

IO

82mV

Input Offset Current I

IO

0.1 0.1 pA

Input Current I

I

22pA

Common-Mode Rejection Ratio CMRR 80 90 dB

Large-Signal Voltage Gain A

OL

VO = 4V

P-P

, RL = 5kΩ 100 100 kV/V

100 100 dB

Common-Mode Input Voltage Range V

ICR

0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V

NOTE:

4. Operation at 5V is not recommended for temperatures below 25oC.

CA3130, CA3130A

3-67

Schematic Diagram

Application Information

Circuit Description

Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the out­put stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentially rises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high

(e.g.,when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).

Input Stage

The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q

6

, Q7) working into a mirror-pair of bipolar tran-

sistors (Q

9

, Q10) functioning as load resistors together with

resistors R

3

through R6. The mirror-pair transistors also func­tion as a differential-to-single-ended conv erter to provide base
drive to the second-stage bipolar transistor (Q

11

). Offset null­ing, when desired, can be effected by connecting a 100,000Ω
potentiometer across Terminals 1 and 5 and the potentiome­ter slider arm to Terminal 4. Cascade-connected PMOS
transistors Q

2

, Q4 are the constant-current source for the
input stage. The biasing circuit for the constant-current source
is subsequently described. The small diodes D

5

through D

8

provide gate-oxide protection against high-voltage transients,
including static electricity during handling for Q

6

and Q7.

3

2

1 8 4

6

7

Q

1

Q

2

Q

4

D

1

D

2

D

3

D

4

Q

3

Q

5

D5D

6

D7D

8

Q

9

Q

10

Q

6

Q

7

5

Z

1

8.3V

INPUT STAGE

R

3

1kΩ

R

4

1kΩ

R

6

1kΩ

R

5

1kΩ

NON-INV.

INPUT

INV.-INPUT

+

-

R

1

40kΩ

5kΩ

R

2

BIAS CIRCUIT

CURRENT SOURCE FOR

“CURRENT SOURCE

LOAD” FOR Q

11

Q6AND Q

7

V+

OUTPUT

OUTPUT
STAGE

Q

8

Q

12

V-

Q

11

SECOND
STAGE

OFFSET NULL

COMPENSATION STROBING

(NOTE 5)

NOTE:

5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.

CA3130, CA3130A

3-68

Second-Stage

Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q

11

and its cascade-connected load resistance provided by
PMOS transistors Q

3

and Q5. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, somewhat above 8.3V, resistor R

2

and zener diode Z1 serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R

1

, diodes

D

1

through D4, and PMOS transistor Q1. A tap at the junction

of resistor R

1

and diode D4 provides a gate-bias potential of

about 4.5V for PMOS transistors Q

4

and Q5 with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q

1

with respect to Terminal
7 to provide gate bias for PMOS transistors Q

2

and Q3. It

should be noted that Q

1

is “mirror-connected (see Note 8)” to

both Q

2

and Q3. Since transistors Q1, Q2, Q3 are designed to

be identical, the approximately 200µA current in Q

1

estab-

lishes a similar current in Q

2

and Q3 as constant current
sources for both the first and second amplifier stages, respec­tively.

At total supply voltages somewhat less than 8.3V, zener
diode Z

1

becomes nonconductive and the potential,

developed across series-connected R

1

, D1-D4, and Q1, var­ies directly with variations in supply voltage. Consequently,
the gate bias for Q

4

, Q5 and Q2, Q3 varies in accordance

with supply-voltage variations. This variation results in

deterioration of the power-supply-rejection ratio (PSRR) at
total supply voltages below 8.3V. Operation at total supply
voltages below about 4.5V results in seriously degraded
performance.

Output Stage

The output stage consists of a drain-loaded inverting ampli­fier using CMOS transistors operating in the Class A mode.
When operating into very high resistance loads, the output
can be swung within millivolts of either supply rail. Because
the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer charac­teristics of the output stage for a load returned to the nega­tive supply rail are shown in Figure 2. Typical op amp loads
are readily driven by the output stage. Because large-signal
excursions are non-linear , requiring feedback for good wa ve­form reproduction, transient delays may be encountered. As
a voltage follower, the amplifier can achieve 0.01% accuracy
levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transis­tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.

Input Current Variation with Common Mode Input
Voltage

As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T

A

= 25oC when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T

A

=25oC.
These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the com­mon-mode input voltage does not exceed 2V. As previously
noted, the input current is essentially the result of the leakage
current through the gate-protection diodes in the input circuit
and, therefore, a function of the applied voltage. Although the
finite resistance of the glass terminal-to-case insulator of the

3

2

7

4

815

6

BIAS CKT.

COMPENSATION

(WHEN REQUIRED)

AV≈ 5X

AV≈

A

V

≈

6000X

30X

INPUT

+

-

200µA 200µA

1.35mA

8mA
0mA

V+

OUTPUT

V-

STROBE

C

C

OFFSET

NULL

CA3130

(NOTE 7)

(NOTE 5)

NOTES:

6. Total supply voltage (for indicated voltage gains) = 15V with input
terminals biased so that Terminal 6 potential is +7.5V above Ter­minal 4.

7. Total supply voltage (for indicated voltage gains) = 15V with out­put terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

22.5

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

17.5 2012.5 15107.52.5 50

2.5

7.5

5

10

15

12.5

17.5

0

SUPPLY VOLTAGE: V+ = 15, V- = 0V
T

A

= 25oC

LOAD RESISTANCE = 5kΩ

500Ω

1kΩ

2kΩ

FIGURE 2. VOL T A GE TRANSFER CHARA CTERISTICS OF

CMOS OUTPUT STAGE

CA3130, CA3130A

3-69

metal can package also contributes an increment of leakage
current, there are useful compensating factors. Because the
gate-protection network functions as if it is connected to Ter­minal 4 potential, and the Metal Can case of the CA3130 is
also internally tied to Ter minal 4, input Terminal 3 is essen­tially “guarded” from spurious leakage currents.

Offset Nulling

Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
potentiometer’s total range.

Input-Current Variation with Temperature

The input current of the CA3130 Series circuits is typically
5pA at 25

o

C. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor-junction device, including
op amps with a junction-FET input stage, the leakage current
approximately doubles for every 10

o

C increase in tempera­ture. Figure 4 provides data on the typical variation of input
bias current as a function of temperature in the CA3130.

In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects, it is suggested that an appropriate heat sink be used
with the CA3130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In such cases, heat­sinking can also very markedly reduce and stabilize input
current variations.

Input Offset Voltage (V

IO

) Variation with DC Bias and

Device Operating Life

It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magni­tude of the change is increased at high temperatures. Users
of the CA3130 should be alert to the possible impacts of this
effect if the application of the device involves extended oper­ation at high temperatures with a significant differential DC
bias voltage applied across Terminals 2 and 3. Figure 5
shows typical data pertinent to shifts in offset voltage
encountered with CA3130 devices (metal can package) dur­ing life testing. At lower temperatures (metal can and plas­tic), for example at 85

o

C, this change in voltage is
considerably less. In typical linear applications where the dif­ferential voltage is small and symmetrical, these incremental
changes are of about the same magnitude as those encoun­tered in an operational amplifier employing a bipolar transis­tor input stage. The 2V

DC

differential voltage example
represents conditions when the amplifier output stage is
“toggled”, e.g., as in comparator applications.

o

10

7.5

5

2.5

0

-101234567
INPUT CURRENT (pA)

INPUT VOLTAGE (V)

TA = 25oC

3

2

7

4

8

6

PA

V

IN

CA3130

15V

TO
5V

0V

TO

-10V

V+

V-

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE

VS = ±7.5V

4000

1000

100

10

1

-80 -60 -40 -20 0 20 40 60 80 100 120 140

INPUT CURRENT (pA)

TEMPERATURE (oC)

FIGURE 4. INPUT CURRENT vs TEMPERATURE

FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE

SHIFT vs OPERATING LIFE

TA = 125oC FOR TO-5 PACKAGES

7

6

5

4

3

2

1

0 500 1000 1500 2000 2500 3000 3500 4000

OFFSET VOLTAGE SHIFT (mV)

TIME (HOURS)

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED

0

CA3130, CA3130A

3-70

Power-Supply Considerations

Because the CA3130 is very useful in single-supply applica­tions, it is pertinent to review some considerations relating to
power-supply current consumption under both single-and
dual-supply service. Figures 6A and 6B show the CA3130
connected for both dual-and single-supply operation.

Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q

8

and Q12 are driven
increasingly positive with respect to ground, current flow
through Q

12

(from the negative supply) to the load is

increased and current flow through Q

8

(from the positive
supply) decreases correspondingly. When the gate terminals
of Q

8

and Q12 are driven increasingly negative with respect

to ground, current flow through Q

8

is increased and current

flow through Q

12

is decreased accordingly.

Single-supply Operation: Initially, let it be assumed that the
value of R

L

is very high (or disconnected), and that the input­terminal bias (T erminals 2 and 3) is such that the output termi­nal (No. 6) voltage is at V+/2, i.e ., the v oltage drops across Q

8

and Q12 are of equal magnitude. Figure 20 shows typical qui­escent supply-current vs supply-voltage for the CA3130 oper­ated under these conditions. Since the output stage is
operating as a Class A amplifier, the supply-current will
remain constant under dynamic operating conditions as long
as the transistors are operated in the linear portion of their
voltage-transfer characteristics (see Figure 2). If either Q

8

or

Q

12

are swung out of their linear regions toward cut-off (a
non-linear region), there will be a corresponding reduction in
supply-current. In the extreme case, e.g., with Terminal 8

swung down to ground potential (or tied to ground), NMOS
transistor Q

12

is completely cut off and the supply-current to

series-connected transistors Q

8

, Q12 goes essentially to zero.
The two preceding stages in the CA3130, however, continue
to draw modest supply-current (see the lower curve in Figure

20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming R

L

= ∞ by pulling the poten-

tial of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal

value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 6B. Let it be assumed again
that the input-terminal bias (Ter minals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q

8

must now supply quiescent current to both R

L

and transistor Q12, it should be apparent that under these
conditions the supply-current must increase as an inverse
function of the R

L

magnitude. Figure 22 shows the voltage-

drop across PMOS transistor Q

8

as a function of load cur­rent at several supply voltages. Figure 2 shows the voltage­transfer characteristics of the output stage for several values
of load resistance.

Wideband Noise

From the standpoint of low-noise performance consider­ations, the use of the CA3130 is most advantageous in appli­cations where in the source resistance of the input signal is
on the order of 1MΩ or more. In this case, the total input­referred noise voltage is typically only 23µV when the test­circuit amplifier of Figure 7 is operated at a total supply volt­age of 15V. This value of total input-referred noise remains
essentially constant, even though the value of source resis­tance is raised by an order of magnitude. This characteristic
is due to the fact that reactance of the input capacitance
becomes a significant factor in shunting the source resis­tance. It should be noted, however, that for values of source
resistance very much greater than 1MΩ, the total noise volt­age generated can be dominated by the thermal noise con­tributions of both the feedback and source resistors.

FIGURE 6A. DUAL POWER SUPPLY OPERATION

FIGURE 6B. SINGLE POWER SUPPLY OPERATION

FIGURE 6. CA3130 OUTPUT STA GE IN DU AL AND SINGLE

POWER SUPPLY OPERATION

3

2

8

4

7

6

R

L

Q

8

Q

12

CA3130

+

-

V+

V-

3

2

8

4

7

6

R

L

Q

8

Q

12

CA3130

+

-

V+

3

2

1

8

4

7

6

+

-

R

s

1MΩ

47pF -7.5V

0.01
µF

+7.5V

0.01µF

NOISE

VOLTAGE

OUTPUT

30.1kΩ

1kΩ

BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)

FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED

FOR WIDEBAND NOISE MEASUREMENTS

CA3130, CA3130A

3-71

Typical Applications

Voltage Followers

Operational amplifiers with very high input resistances, like
the CA3130, are particularly suited to service as voltage
followers. Figure 8 sho ws the circuit of a classical v oltage fol­lower, together with pertinent waveforms using the CA3130
in a split-supply configuration.

A voltage follow er, operated from a single supply, is shown in
Figure 9, together with related waveforms. This follower cir­cuit is linear over a wide dynamic range, as illustrated by the
reproduction of the output waveform in Figure 9A with input­signal ramping. The wavefor ms in Figure 9B show that the
follower does not lose its input-to-output phase-sense, even
though the input is being swung 7.5V below ground poten­tial. This unique characteristic is an important attribute in
both operational amplifier and comparator applications. Fig­ure 9B also shows the manner in which the CMOS output
stage permits the output signal to swing down to the nega­tive supply-rail potential (i.e., ground in the case shown). The
digital-to-analog converter (DAC) circuit, described later,
illustrates the practical use of the CA3130 in a single-supply
voltage-follower application.

9-Bit CMOS DAC

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 10. This system combines the concepts of
multiple-switch CMOS lCs, a low-cost ladder network of dis­crete metal-oxide-film resistors, a CA3130 op amp con­nected as a follower, and an inexpensive monolithic
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced
with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 10.

The circuit uses an R/2R voltage-ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power-supply ter­minal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.

A single 15V supply provides a positive bus for the CA3130
follower amplifier and feeds the CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line­voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to par­ticular needs.

Single-Supply, Absolute-Value, Ideal Full-Wave Rectifier

The absolute-value circuit using the CA3130 is shown in
Figure 11. During positive excursions, the input signal is fed
through the feedback network directly to the output.
Simultaneously, the positive excursion of the input signal
also drives the output terminal (No. 6) of the inverting
amplifier in a negative-going excursion such that the 1N914
diode effectively disconnects the amplifier from the signal
path. During a negative-going excursion of the input signal,
the CA3130 functions as a normal inverting amplifier with a
gain equal to -R

2/R1

. When the equality of the two equations
shown in Figure 11 is satisfied, the full-wave output is
symmetrical.

Peak Detectors

Peak-detector circuits are easily implemented with the
CA3130, as illustrated in Figure 12 for both the peak-positive
and the peak-negative circuit. It should be noted that with
large-signal inputs, the bandwidth of the peak-negative cir­cuit is much less than that of the peak-positive circuit. The
second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a pos­itive-going signal excursion at the collector of transistor Q

11

,
which is loaded by the intrinsic capacitance of the associ­ated circuitry in this mode. On the other hand, during a neg­ative-going signal excursion at the collector of Q

11

, the
transistor functions in an active “pull-down” mode so that the
intrinsic capacitance can be discharged more expeditiously.

CA3130, CA3130A

3-72

3

2

1

8

4

7

6

+

-

10kΩ

C

C

= 56pF

-7.5V

0.01µF

+7.5V

0.01µF

2kΩ

2kΩ

BW (-3dB) = 4MHz

SR = 10V/µs

25pF

0.1µF

Top Trace: Output

Center Trace: Input

FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV.,

200ns/DIV.)

Top Trace: Output Signal; 2V/Div., 5µs/Div.

Center Trace: Difference Signa; 5mV/Div., 5µs/Div.

Bottom Trace: Input Signal; 2V/Div., 5µs/Div.

FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING

SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)

FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS

3

2

8

1

4

7

6

+

-

10kΩ

56pF

OFFSET

+15V

0.01µF

2kΩ

0.1µF

5

ADJUST

100kΩ

FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL

RAMPING (2V/DIV., 500µs/DIV.)

Top Trace:Output; 5V/Div., 200µs/Div.

Bottom Trace:Input Signal; 5V/Div., 200µs/Div.

FIGURE 9B. OUTPUT WAVEFORM WITH GROUND

REFERENCE SINE-WAVE INPUT

FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS. (e.g., FOR USE IN
SINGLE-SUPPL Y D/A CONVERTER; SEE FIGURE 9
IN AN6080)

CA3130, CA3130A

3-73

FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130

FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

6 3 101036

4

8

36

7

9

4

10

2

3

13

8

12 12

1

58

1313 1 12

8 5

14
11

2

6

5

1

7

7

1

6

8

4

3

2

10V LOGIC INPUTS

+10.010V

LSB

987 654 321

MSB

806K
1%

PARALLELED

RESISTORS

+15V

VOLTAGE
FOLLOWER

CA3130

OUTPUT

LOAD

100K

OFFSET

NULL

56pF

2K

0.1µF

REGULATED

VOLTAGE

ADJ

22.1k
1%

1K

3.83k
1%

0.001µF

CA3085

VOLTAGE

REGULATOR

+15V

2µF
25V

+

-

+10.010V

CD4007A

“SWITCHES”

CD4007A

“SWITCHES”

402K1%200K

1%

100K1%806K1%806K

1%

806K1%750K

1%

806K

1%

806K1%806K1%806K

1%

(2)

(4)

(8)

806K
1%

+

-

62

BIT

1
2
3
4
5

6 - 9

REQUIRED

RATIO-MATCH

STANDARD

±0.1%
±0.2%
±0.4%
±0.8%
±1% ABS

NOTE: All resistances are in ohms.

CD4007A

“SWITCHES”

1

5

10K

2

3

4

6

8

1

5

7

R

2

2kΩ

+15V

0.01
µF

1N914

R

3

5.1kΩ

PEAK

ADJUST

2kΩ

100kΩ

OFFSET
ADJUST

20pF

CA3130

R

1

4kΩ

+

-

20V

P-P

Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V

1V

P-P

Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV

Gain =

R

2

R

1

------ -

= X =

R

3

R1+R2+R

3

------------------------------------- -

R

3=R1

X+X

2

1 - X

------------------





For X = 0.5:

2KΩ

4kΩ

----------- -

=

R

2

R

1

------ -

R

3

= 4kΩ

0.75

0.5

-----------





= 6kΩ

Top Trace: Output Signal; 2V/Div.

Bottom Trace: Input Signal; 10V/Div.

Time base on both traces: 0.2ms/Div.

0V

0V

CA3130, CA3130A

3-74

FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT

FIGURE 12. PEAK-DETECTOR CIRCUITS

FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)

3

2

6

4

7

CA3130

+7.5V

0.01µF

+DC

OUTPUT

5µF

+

-

100

kΩ

1N914

0.01µF

-7.5V

2kΩ

10kΩ

+

-

6V

P-P

INPUT;

BW (-3dB) = 1.3MHz

0.3V

P-P

INPUT;

BW (-3dB) = 240kHz

3

2

6

4

7

CA3130

+7.5V

0.01µF

-DC

OUTPUT

5µF

+

-

100

kΩ

1N914

0.01µF

-7.5V

2kΩ

10kΩ

+

-

6V

P-P

INPUT;

BW (-3dB) = 360kHz

0.3V

P-P

INPUT;

BW (-3dB) = 320kHz

6

3

2

1

8

7

4

CA3086

CURRENT

LIMIT

ADJ

3Ω

R

2

1kΩ

Q

5

13

14

12

Q

1

Q

2

Q

3

Q

4

10 7 3

4269

11815

390Ω

1kΩ

20kΩ

+

-

5µF
25V

56pF

ERROR
AMPLIFIER

CA3130

30kΩ

100kΩ

IC1

0.01

VOLTAGE
ADJUST

50kΩ

R

1

14

13

Q

5

12

62kΩ

IC

3

OUTPUT
0 TO 13V

AT

40mA

+

-

0.01µF

+20V

INPUT

2.2kΩ

+

-

25µF

IC

2

CA3086

10

11

1, 2

Q

4

Q

1

8, 7

5

Q

3

Q

2

6

4

REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz

+

-

+

-

1kΩ

9

µF

3

CA3130, CA3130A

3-75

Error-Amplifier in Regulated-Power Supplies

The CA3130 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an error­amplifier when the regulated output voltage is required to
approach zero. Figure 13 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment over the range from 0V to
13V. Q

3

and Q4 in lC2 (a CA3086 transistor-array lC) func­tion as zeners to provide supply-voltage for the CA3130
comparator (IC

1

). Q1, Q2, and Q5 in IC2 are configured as a
low impedance, temperature-compensated source of adjust­able reference voltage for the error amplifier. Transistors Q

1

,

Q

2

, Q3, and Q4 in lC3 (another CA3086 transistor-array lC)
are connected in parallel as the series-pass element. Tran­sistor Q

5

in lC3 functions as a current-limiting device by
diverting base drive from the series-pass transistors, in
accordance with the adjustment of resistor R

2

.

Figure 14 contains the schematic diagram of a regulated
power-supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC

1

) and circuitry

associated with lC

2

function as previously described,

although the output of lC

1

is boosted by a discrete transistor

(Q

4

) to provide adequate base drive for the Darlington-con-

nected series-pass transistors Q

1

, Q2. Transistor Q3 func-

tions in the previously described current-limiting circuit.

Multivibrators

The exceptionally high input resistance presented by the
CA3130 is an attractive feature for multivibrator circuit
design because it permits the use of timing circuits with high
R/C ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
“on” and “off” periods, is shown in Figure 15. Resistors R

1

and R2 are used to bias the CA3130 to the mid-point of the
supply-voltage and R

3

is the feedback resistor. The pulse

repetition rate is selected by positioning S

1

to the desired
position and the rate remains essentially constant when the
resistors which determine “on-period” and “off-period” are
adjusted.

Function Generator

Figure 16 contains a schematic diagram of a function genera­tor using the CA3130 in the integrator and threshold detector
functions. This circuit generates a triangular or square-wave
output that can be swept over a 1,000,000:1 range (0.1Hz to
100kHz) by means of a single control, R

1

. A voltage-control

input is also available for remote sweep-control.
The heart of the frequency-determining system is an opera-

tional-transconductance-amplifier (OTA) (see Note 10), lC

1

,
operated as a voltage-controlled current-source. The output,
I

O

, is a current applied directly to the integrating capacitor, C1,

in the feedback loop of the integrator lC

2

, using a CA3130, to

provide the triangular-wave output. Potentiometer R

2

is used

FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)

6

2

3

1

8

7

4

4.3kΩ

1Ω

+

-

43kΩ

100µF

ERROR
AMPLIFIER

IC

1

VOLTAGE
ADJUST

14

13

100µF

+55V

INPUT

2.2kΩ

+

-

IC

2

CA3086 10, 11

Q

4

Q

1

Q

2

6

REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µV

RMS

UP TO 100kHz

+

-

+

-

CA3130

+

-

+

-

1W

3.3kΩ

1W

5µF

9
8, 7

Q

3

1, 2

3
5

4

1kΩ

62kΩ

Q

5

12

10kΩ

Q

2

Q

1

50kΩ

Q

3

1kΩ

2N3055

2N2102

CURRENT
LIMIT
ADJUST

2N5294

2N2102

Q

4

1000pF

10kΩ

8.2kΩ

OUTPUT:

0.1 TO 50V
AT 1A

CA3130, CA3130A

3-76

to adjust the circuit for slope symmetry of positive-going and
negative-going signal excursions.

Another CA3130, IC

3

, is used as a controlled switch to set
the excursion limits of the triangular output from the integra­tor circuit. Capacitor C

2

is a “peaking adjustment” to opti­mize the high-frequency square-wave performance of the
circuit.

Potentiometer R

3

is adjustable to perfect the “amplitude
symmetry” of the square-wave output signals. Output from
the threshold detector is fed back via resistor R

4

to the input

of lC

1

so as to toggle the current source from plus to minus

in generating the linear triangular wave.

Operation with Output-Stage Power-Booster

The current-sourcing and-sinking capability of the CA3130
output stage is easily supplemented to provide power-boost
capability. In the circuit of Figure 17, three CMOS transistor­pairs in a single CA3600E (see Note 12) lC array are shown
parallel connected with the output stage in the CA3130. In
the Class A mode of CA3600E shown, a typical device con­sumes 20mA of supply current at 15V operation. This
arrangement boosts the current-handling capability of the
CA3130 output stage by about 2.5X.

The amplifier circuit in Figure 17 employs feedback to estab­lish a closed-loop gain of 48dB. The typical large-signal
bandwidth (-3dB) is 50kHz.

NOTE:

9. See file number 619 for technical information.

7

4

6

3

2

R

1

100kΩ

R

2

100kΩ

R

3

100kΩ

ON-PERIOD

ADJUST

1MΩ

2kΩ 2kΩ

OFF-PERIOD

ADJUST

1MΩ

+15V

0.01µF

OUTPUT

2kΩ

0.001µF

0.01µF

0.1µF

1µF

S

1

CA3130

+

-

FIGURE 15. PULSE GENERAT OR (ASTABLE MULTIVIBRAT OR)

WITH PROVISIONS FOR INDEPENDENT CONTR OL
OF “ON” AND “OFF” PERIODS

FREQUENCY RANGE:

POSITION OF S

1

0.001µF

0.01µF

0.1µF
1µF

PULSE PERIOD
4µs to 1ms
40µs to 10ms

0.4ms to 100ms
4ms to 1s

NOTE:

10. See file number 475 and AN6668 for technical information.

FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)

6

3

2

1

4

7

5

6

2

3

4

7

8

1

5

4

6

7

3

2

R

4

270kΩ

+7.5V

VOLTAGE-CONTROLLED

CURRENT SOURCE

IC

1

3kΩ

3kΩ

10MΩ

+7.5V

R

2

100kΩ

SLOPE
SYMMETRY
ADJUST

VOLTAGE
CONTROLLED
INPUT

-7.5V

10kΩ

10kΩ

R

1

-7.5V

FREQUENCY
ADJUST
(100kHz MAX)

-7.5V
+7.5V

I

O

IC

2

+7.5V

C

1

100pF

INTEGRATOR

-7.5V

56pF

CA3130

+

-

CA3080A

+

-

39kΩ

3 - 30pF

C

2

ADJUST

HIGH - FREQ.

DETECTOR

THRESHOLD

150kΩ

IC

3

+7.5V

CA3130

+

-

R

3

100kΩ

AMPLITUDE
SYMMETRY
ADJUST

22kΩ

-7.5V

(NOTE 10)

CA3130, CA3130A

3-77

NOTES:

11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.

12. See file number 619.

FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130

8

7

3

2

+15V

2kΩ

CA3130

+

-

4

1036

4 97

6

14

750kΩ

1µF

2 11

13 1

12

58

1µF

1MΩ

0.01µF

510kΩ

500µF

Q

P3

Q

N1

Q

N2

Q

N3

Q

P2

Q

P1

CA3600E

A

V(CL)

= 48dB

LARGE SIGNAL
BW (-3 dB) = 50kHz

R

L

= 100Ω

(P

O

= 150mW

AT THD = 10%)

(NOTE 12)

INPUT

Typical Performance Curves

FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE

FIGURE 19. OPEN-LOOP RESPONSE

LOAD RESISTANCE = 2kΩ

150

140

130

120

110

100

90

80

-100 -50 0 50 100

OPEN LOOP VOLTAGE GAIN (dB)

TEMPERATURE (oC)

SUPPLY VOLTAGE: V+ = 15V; V- = 0
T

A

= 25oC

φ OL

3

2

1

1

2

3

4

4

AOL

1 - C

L

= 9pF, CC = 0pF, RL = ∞

2 - CL = 30pF, CC = 15pF, RL = 2kΩ
3 - CL = 30pF, CC = 47pF, RL = 2kΩ
4 - C

L

= 30pF, CC = 150pF, RL = 2kΩ

120

100

80

60

40

20

0

OPEN LOOP VOLTAGE GAIN (dB)

-100

-200

-300

OPEN LOOP PHASE (DEGREES)

10210310410510610710

8

FREQUENCY (Hz)

10

1

CA3130, CA3130A

3-78

All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Harris Semiconductor products are sold by description only. Harris Semiconductor reser ves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
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SEMICONDUCTOR

FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR

(Q

8

) vs LOAD CURRENT

FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR

(Q12) vs LOAD CURRENT

Typical Performance Curves

(Continued)

LOAD RESISTANCE =

∞

TA = 25oC
V- = 0

OUTPUT VOLTAGE BALANCED = V+/2

OUTPUT VOLTAGE HIGH = V+
OR LOW = V-

17.5

12.5

10

7.5

5

2.5

0

6 8 10 12 14 16 18

TOTAL SUPPLY VOLTAGE (V)

QUIESCENT SUPPLY CURRENT (mA)

4

OUTPUT VOLTAGE = V+/2
V- = 0

14

12

10

8

6

4

2

0246810121416

QUIESCENT SUPPLY CURRENT (mA)

TOTAL SUPPLY VOLTAGE (V)

TA = -55oC

25oC

125oC

0

50

10

1

0.1

0.01

0.001

0.001 0.01 0.1 1.0 10 100
MAGNITUDE OF LOAD CURRENT (mA)

VOLTAGE DROP ACROSS PMOS OUTPUT

STAGE TRANSISTOR (V)

15V

10V

NEGATIVE SUPPLY VOLTAGE = 0V

T

A

= 25oC

POSITIVE SUPPLY VOLTAGE = 5V

NEGATIVE SUPPLY VOLTAGE = 0V
TA = 25oC

50

10

1

0.1

0.01

0.001

0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)

VOLTAGE DROP ACROSS NMOS OUTPUT

STAGE TRANSISTOR (V)

15V

10V

POSITIVE SUPPLY VOLTAGE = 5V

CA3130, CA3130A