Datasheet CA3130EZ Specification

CA3130, CA3130A

Data Sheet September 1998 File Number 817.4

15MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output

CA3130A and CA3130 are op amps that combine the
advantage of both CMOS and bipolar transistors.

Gate-protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance.TheuseofPMOStransistors in the input stage
results in common-mode input-voltage capability down to

0.5V below the negative-supply terminal, an important
attribute in single-supply applications.

A CMOS transistor-pair, capable of swinging the output
voltage to within 10mV of either supply-voltage terminal (at
very high values of load impedance), is employed as the
output circuit.

The CA3130 Series circuits operate at supply voltages
ranging from 5V to 16V, (±2.5V to ±8V). They can be phase
compensated with a single external capacitor, and have
terminals for adjustment of offset voltage for applications
requiring offset-null capability. Terminal provisions are also
made to permit strobing of the output stage.

The CA3130A offers superior input characteristics over
those of the CA3130.

Pinouts

CA3130, CA3130A

(PDIP, SOIC)

TOP VIEW

Features

• MOSFET Input Stage Provides:

- Very High Z

- Very Low I

= 1.5 TΩ (1.5 x 1012Ω) (Typ)

I

. . . . . . . . . . . . . 5pA (Typ) at 15V Operation

I

. . . . . . . . . . . . . . . . . . . . . = 2pA (Typ) at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals can be Swung 0.5V
Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either (or
both) Supply Rails

Applications

• Ground-Referenced Single Supply Amplifiers

• Fast Sample-Hold Amplifiers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators
(Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Amplifiers

• Voltage Followers (e.g. Follower for Single-Supply D/A
Converter)

• Voltage Regulators (Permits Control of Output Voltage
Down to 0V)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectifiers

• Photo-Diode Sensor Amplifiers

OFFSET

NON-INV.

PHASE
COMPENSATION

OFFSET

INPUT

NON-INV.

1

NULL

INV.

2

INPUT

3

INPUT

4

V-

CA3130, CA3130A

1

NULL

2

INV.

3

INPUT

(METAL CAN)

-

+

TOP VIEW

TAB

8

-

+

4
V- AND CASE

1

8

STROBE

7

V+

6

OUTPUT

5

OFFSET
NULL

STROBE

+

7

V

6

OUTPUT

OFFSET

5

NULL

Ordering Information

TEMP.

PART NO.

(BRAND)

CA3130AE -55 to 125 8 Ld PDIP E8.3
CA3130AM

(3130A)

CA3130AM96

(3130A)

CA3130AT -55 to 125 8 Pin Metal Can T8.C
CA3130E -55 to 125 8 Ld PDIP E8.3
CA3130M

(3130)

CA3130M96

(3130)

CA3130T -55 to 125

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

RANGE

(oC) PACKAGE

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC
Tape and Reel

-55 to 125 8 Ld SOIC M8.15

-55 to 125 8 Ld SOIC
Tape and Reel

8 Pin Metal Can

| Copyright © Intersil Corporation 1999

PKG.

NO.

M8.15

M8.15

T8.C

CA3130, CA3130A

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (Between V+ And V- Terminals) . . . . . . . . . .16V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)

Input-Terminal Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Output Short-Circuit Duration (Note 1) . . . . . . . . . . . . . . . Indefinite

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -50oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Short circuit may be applied to ground or to either supply.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A

SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A

Metal Can Package . . . . . . . . . . . . . . . 170 85

Maximum Junction Temperature (Metal Can Package) . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

PARAMETER SYMBOL

Input Offset Voltage |VIO|VS = ±7.5V - 8 15 - 2 5 mV
Input Offset Voltage

Temperature Drift
Input Offset Current |IIO|VS = ±7.5V - 0.5 30 - 0.5 20 pA
Input Current I
Large-Signal Voltage Gain A

Common-Mode
Rejection Ratio

Common-Mode Input
Voltage Range

Power-Supply
Rejection Ratio

Maximum Output Voltage VOM+RL = 2kΩ 12 13.3 - 12 13.3 - V

Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA

Supply Current I+ VO = 7.5V,

= 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified

A

TEST

CONDITIONS

∆VIO/∆T - 10 - - 10 - µV/oC

I

OL

CMRR 70 90 - 80 90 - dB

V

ICR

∆VIO/∆VSVS = ±7.5V - 32 320 - 32 150 µV/V

VOM-RL = 2kΩ - 0.002 0.01 - 0.002 0.01 V

VOM+RL = ∞ 14.99 15 - 14.99 15 - V

VOM-RL = ∞ - 0 0.01 - 0 0.01 V

IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA

I+ VO = 0V,

VS = ±7.5V - 5 50 - 5 30 pA
VO = 10V

RL = 2kΩ

RL = ∞

RL = ∞

P-P

50 320 - 50 320 - kV/V
94 110 - 94 110 - dB

CA3130 CA3130A

UNITSMIN TYP MAX MIN TYP MAX

0 -0.5 to 12 10 0 -0.5 to 12 10 V

- 10 15 - 10 15 mA

-23-23mA

2

CA3130, CA3130A

Electrical Specifications Typical Values Intended Only for Design Guidance, V

Unless Otherwise Specified

SUPPLY

= ±7.5V, TA = 25oC

CA3130,

PARAMETER SYMBOL TEST CONDITIONS

Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4and 5 or

CA3130A UNITS

±22 mV

4 and 1
Input Resistance R
Input Capacitance C
Equivalent Input Noise Voltage e

I
I

N

f = 1MHz 4.3 pF

BW = 0.2MHz, RS = 1MΩ

1.5 TΩ

23 µV

(Note 3)
Open Loop Unity Gain Crossover Frequency

(For Unity Gain Stability ≥47pF Required.)

f

T

CC = 0 15 MHz

CC = 47pF 4 MHz
Slew Rate: SR

CC = 0 30 V/µsOpen Loop

Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF,

r

Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4V

)t

P-P

S

RL = 2kΩ

(Voltage Follower)

CL = 25pF,

0.09 µsRise Time t

1.2 µs

NOTE:

3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, T

= 25oC

A

Unless Otherwise Specified (Note 4)

PARAMETER SYMBOL TEST CONDITIONS CA3130 CA3130A UNITS

Input Offset Voltage V
Input Offset Current I
Input Current I

IO

IO

I

82mV

0.1 0.1 pA
22pA

Common-Mode Rejection Ratio CMRR 80 90 dB
Large-Signal Voltage Gain A

OL

VO = 4V

, RL = 5kΩ 100 100 kV/V

P-P

100 100 dB

Common-Mode Input Voltage Range V

ICR

0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞ 300 300 µA

VO = 2.5V, RL = ∞ 500 500 µA

Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V

NOTE:

4. Operation at 5V is not recommended for temperatures below 25oC.

3

Schematic Diagram

CA3130, CA3130A

BIAS CIRCUIT

Z

1

8.3V

R

1

40kΩ

R

2

5kΩ

NON-INV.

INPUT

3

+

INV.-INPUT

2

-

Q

D

1

D

2

D

3

D

4

1

INPUT STAGE

D5D

CURRENT SOURCE FOR

Q6AND Q

Q

2

Q

4

6

Q

6

R

3

1kΩ

Q

(NOTE 5)

Q

10

9

7

D7D

Q

7

R

4

1kΩ

“CURRENT SOURCE

LOAD” FOR Q

Q

3

Q

5

SECOND
STAGE

8

Q

11

11

OUTPUT
STAGE

Q

Q

V+

7

8

OUTPUT

6

12

R

5

1kΩ

5

R

6

1kΩ

OFFSET NULL

1 8 4

NOTE:

5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.

Application Information

Circuit Description

Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the
output stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentiallyrises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the

COMPENSATION STROBING

V-

ohmic load resistance presented tothe amplifier isvery high
(e.g.,when the amplifier output is used todrive CMOS digital
circuits in Comparator applications).

Input Stage

The circuit of the CA3130is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
transistors (Q
with resistors R
function as a differential-to-single-ended conv erter to provide
base drive to the second-stage bipolar transistor (Q
nulling, when desired, can be effected by connecting a
100,000Ω potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade-connected
PMOS transistors Q
the input stage. The biasing circuit for the constant-current
source is subsequently described. The small diodes D

, Q7) working into a mirror-pair of bipolar

6

, Q10) functioning as load resistors together

9

through R6. The mirror-pair transistors also

3

11

, Q4 are the constant-current source for

2

). Offset

5

4

CA3130, CA3130A

through D8provide gate-oxide protection against high-voltage
transients, including static electricity during handling for Q

6

and Q7.

CA3130

+

3

INPUT

2

200µA 200µA

AV≈ 5X

1.35mA

BIAS CKT.

AV≈

6000X

8mA
(NOTE 5)
0mA
(NOTE 7)

≈

A

V

30X

-

C

C

COMPENSATION

OFFSET

NULL

NOTES:

6. Totalsupplyvoltage(forindicatedvoltagegains)=15Vwithinput
terminals biased so that Terminal 6 potential is +7.5V above Ter­minal 4.

7. Total supply voltage (for indicated voltage gains) = 15V with out­put terminal driven to either supply rail.

FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES

(WHEN REQUIRED)

STROBE

815

V+

7

OUTPUT

6

V-

4

Second-Stage

Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q

11

and its cascade-connected load resistance provided by
PMOS transistors Q

and Q5. The source of bias potentials

3

forthese PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, somewhat abo ve 8.3V, resistor R
and zener diode Z1serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
D

through D4, and PMOS transistor Q1. A tap at the junction

1

of resistor R
about 4.5V for PMOS transistors Q

and diode D4 provides a gate-bias potential of

1

and Q5 with respect to

4

Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
7 to provide gate bias for PMOS transistors Q
should be noted that Q
both Q

and Q3. Since transistors Q1,Q2,Q3are designed to

2

is “mirror-connected (see Note 8)” to

1

with respect to Terminal

1

and Q3. It

2

be identical, the approximately 200µA current in Q
establishes a similar current in Q2and Q3as constant current
sources for both the first and second amplifier stages,
respectively.

, diodes

1

1

2

At total supply voltages somewhat less than 8.3V, zener
diode Z
developed across series-connected R

becomes nonconductive and the potential,

1

, D1-D4, and Q1,

1

varies directly with variations in supply voltage.
Consequently, the gate bias for Q

and Q2,Q3varies in

4,Q5

accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.

Output Stage

The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier,its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large­signal excursionsare non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve

0.01% accuracy levels, including the negative supply rail.

NOTE:

8. For general information on the characteristics of CMOS transis­tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.

17.5
SUPPLY VOLTAGE: V+ = 15, V- = 0V

T

= 25oC

A

15

12.5

10

500Ω

7.5

5

2.5

0

OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)

FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF

LOAD RESISTANCE = 5kΩ

2kΩ

1kΩ

GATE VOLTAGE (TERMINALS 4 AND 8) (V)

CMOS OUTPUT STAGE

17.5 2012.5 15107.52.5 50

22.5

Input Current Variation with Common Mode Input
Voltage

As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T

= 25oC when Terminals 2 and 3 are at a common-mode

A

potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T

=25oC.

A

5

CA3130, CA3130A

These data show that circuit designers can advantageously
exploit these characteristics to design circuits which typically
require an input current of less than 1pA, provided the
common-mode input voltage does not exceed 2V. As
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in the
input circuit and, therefore, a function of the applied voltage.
Although the finite resistance of the glass terminal-to-case
insulator of the metal can package also contributes an
increment of leakage current, there are useful compensating
factors. Because the gate-protection network functions as if it
is connected to Terminal 4 potential, and the Metal Can case
of the CA3130 is also internally tied to Terminal 4, input
Terminal 3 is essentially “guarded” from spurious leakage
currents.

10

TA = 25oC

7.5

5

PA

INPUT VOLTAGE (V)

2.5

0

-101234567

FIGURE 3. INPUT CURRENT vs COMMON-MODE VOLTAGE

INPUT CURRENT (pA)

2

CA3130

3

V

IN

4

V+

15V

TO
5V

7

6

8

0V

TO

-10V

V-

Offset Nulling

Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the sliderarm positionedin the mid-point of the
potentiometer’s total range.

Input-Current Variation with Temperature

The input current of the CA3130 Series circuits is typically
5pA at 25
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor-junction device, including
op amps with a junction-FET input stage, the leakage current
approximately doubles f or every 10
temperature. Figure 4provides data on the typical v ariationof
input bias current as a function of temperature in the CA3130.

o

C. The major portion of this input current is due to

o

C increase in

4000

VS = ±7.5V

1000

100

10

INPUT CURRENT (pA)

1

-80 -60 -40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (oC)

FIGURE 4. INPUT CURRENT vs TEMPERATURE

In applications requiring the lowest practical input current
and incremental increases in current because of “warm-up”
effects,it is suggested thatan appropriate heatsink be used
with the CA3130. In addition, when “sinking” or “sourcing”
significant output current the chip temperature increases,
causing an increase in the input current. In suchcases, heat­sinking can also very markedly reduce and stabilize input
current variations.

Input Offset Voltage (VIO) Variation with DC Bias
and Device Operating Life

It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The
magnitude of the change is increased at high temperatures.
Users of the CA3130 shouldbe alert to the possible impacts
of this effect if the application of the device involves
extended operation at high temperatures with a significant
differential DC bias voltage applied across Terminals 2 and

3. Figure 5 shows typical data pertinent to shifts in offset
voltage encountered with CA3130 devices (metal can
package) during life testing. At lower temperatures (metal
can and plastic), for example at 85
is considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The 2V
example represents conditions when the amplifier output
stage is “toggled”, e.g., as in comparator applications.

o

C, this changein voltage

differential voltage

DC

6

CA3130, CA3130A

o

7

6

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V

5

OUTPUT STAGE TOGGLED

4

3

2

OFFSET VOLTAGE SHIFT (mV)

1

0

0 500 1000 1500 2000 2500 3000 3500 4000

FIGURE 5. TYPICALINCREMENTAL OFFSET-VOLTAGE

FIGURE 6A. DUAL POWER SUPPLY OPERATION

DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2

SHIFT vs OPERATING LIFE

3

2

CA3130

+

-

TA = 125oC FOR TO-5 PACKAGES

TIME (HOURS)

V+

7

Q

8

Q

12

4

8

V-

6

R

through Q
increased and current flow through Q

(from the negative supply) to the load is

12

(from the positive

8

supply) decreases correspondingly.When the gate terminals
of Q

and Q12 are driven increasingly negative with respect

8

to ground, current flow through Q
flow through Q

is decreased accordingly.

12

is increased and current

8

Single-supply Operation: Initially, let it be assumed that the
value of R

is very high (or disconnected), and that the input-

L

terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the v oltage drops
across Q

and Q12 are of equal magnitude. Figure 20 shows

8

typical quiescent supply-current vs supply-voltage for the
CA3130 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage-transfer char acteristics (see Figure 2). If either
Q

or Q12 are swung out of their linear regions toward cut-off

8

(a non-linear region), there will be a corresponding reduction
in supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q

L

series-connected transistorsQ

is completely cut off and the supply-current to

12

goes essentially to zero.

8,Q12

The two preceding stages in the CA3130, however, continue
to draw modest supply-current (see the lower curve in Figure

20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming R

= ∞ by pulling the

L

potential of Terminal 8 down to that of Terminal 4.

7

V+

3

2

FIGURE 6B. SINGLE POWER SUPPLY OPERATION

FIGURE 6. CA3130 OUTPUT STAGE IN DUAL AND SINGLE

CA3130

+

-

POWER SUPPLY OPERATION

Q

8

Q

12

4

8

6

R

L

Power-Supply Considerations

Because the CA3130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 6A and 6B showthe
CA3130 connected for both dual-and single-supply
operation.

Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q
increasingly positive with respect to ground, current flow

and Q12 are driven

8

Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 6B. Let it be assumed again
that the input-terminal bias (Terminals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q

must now supply quiescent current to both R

8

and transistor Q12, it should be apparent that under these
conditions the supply-current must increase as an inverse
function of the R
drop across PMOS transistor Q

magnitude. Figure 22 shows the voltage-

L

as a function of load

8

current at several supply voltages. Figure 2 shows the
voltage-transfer characteristics of the output stage for
several values of load resistance.

Wideband Noise

From the standpoint of low-noise performance
considerations, the use of the CA3130 is most
advantageous in applications where in the source resistance
of the input signal is on the order of 1MΩ or more. In this
case, the total input-referred noise voltage is typically only
23µV when the test-circuit amplifier of Figure 7 is operated
at a total supply voltage of 15V. This value of total input­referred noise remains essentially constant, even though the
value of source resistance is raised by an order of
magnitude. This characteristic is due to the fact that
reactance of the input capacitance becomes a significant

L

7

CA3130, CA3130A

factor in shunting the source resistance. It should be noted,
however, that for values of source resistance very much
greater than 1MΩ, the total noise voltage generated can be
dominated by the thermal noise contributions of both the
feedback and source resistors.

+7.5V

6

0.01µF

NOISE

VOLTAGE

OUTPUT

30.1kΩ

0.01
µF

1kΩ

R

s

1MΩ

BW (-3dB) = 200kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) = 23µV (TYP)

FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED

3

2

FOR WIDEBAND NOISE MEASUREMENTS

7

+

-

4

8

1

47pF -7.5V

Typical Applications

Voltage Followers

Operational amplifiers with very high input resistances, like
the CA3130, are particularly suited to service as voltage
followers. Figure 8 shows the circuit of a classical voltage
follower, together with pertinent waveforms using the
CA3130 in a split-supply configuration.

A voltage follower,operated from a single supply, is shown in
Figure 9, together with related waveforms. This follower
circuit is linear over a wide dynamic range, as illustrated by
the reproduction of the output waveform in Figure 9A with
input-signal ramping. The waveforms in Figure 9B show that
the follower does not lose its input-to-output phase-sense,
even though the input is being swung 7.5V below ground
potential. This unique characteristic is an important attribute
in both operational amplifier and comparator applications.
Figure 9B also shows the manner in whichthe CMOS output
stage permits the output signal to swing down to the
negative supply-rail potential (i.e., ground in the case
shown). The digital-to-analog converter (DAC) circuit,
described later, illustrates the practical use of theCA3130 in
a single-supply voltage-follower application.

9-Bit CMOS DAC

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)
is shown in Figure 10. This system combines the concepts of
multiple-switch CMOS lCs, a low-cost ladder network of
discrete metal-oxide-film resistors, a CA3130 op amp
connected as a follower, and an inexpensive monolithic
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced

with CMOS input logic, e.g., 10V logic levels are used in the
circuit of Figure 10.

The circuit uses an R/2R voltage-ladder network, with the
output potential obtained directly by terminating the ladder
arms at either the positive or the negative power-supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
or negative power-supply terminal. The resistor ladder is an
assembly of 1% tolerance metal-oxide film resistors. The five
arms requiring the highest accuracy are assembled with
series and parallel combinations of 806,000Ω resistors from
the same manufacturing lot.

A single 15V supply provides a positive bus for the CA3130
followeramplifier and feedsthe CA3085 voltage regulator. A
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line­voltage regulation (approximately 0.2%) permits a 9-bit
accuracy to be maintained with variations of several volts in
the supply. The flexibility afforded by the CMOS building
blocks simplifies the design of DAC systems tailored to
particular needs.

Single-Supply, Absolute-Value, Ideal Full-Wave
Rectifier

The absolute-value circuit using the CA3130 is shown in
Figure 11. During positive excursions, the input signal is fed
through the feedback network directly to the output.
Simultaneously, the positive excursion of the input signal
also drives the output terminal (No. 6) of the inverting
amplifier in a negative-going excursion such that the 1N914
diode effectively disconnects the amplifier from the signal
path. During a negative-going excursion of the input signal,
the CA3130 functions as a normal inverting amplifier with a
gain equal to -R

. When the equality of the two equations

2/R1

shown in Figure 11 is satisfied, the full-wave output is
symmetrical.

Peak Detectors

Peak-detector circuits are easily implemented with the
CA3130, as illustrated in Figure 12 for both the peak-positive
and the peak-negative circuit. It should be noted that with
large-signal inputs, the bandwidth of the peak-negative
circuit is much less than that of the peak-positive circuit. The
second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a
positive-going signal excursion at the collector of transistor
Q

, which is loaded by the intrinsic capacitance of the

11

associated circuitry in this mode. On the other hand, during
a negative-going signal excursion at the collector of Q
transistor functions in an active “pull-down” mode so that the
intrinsic capacitance can be discharged more expeditiously.

11

, the

8

CA3130, CA3130A

10kΩ

BW (-3dB) = 4MHz

3

2

SR = 10V/µs

C

C

+

-

1

= 56pF

8

-7.5V

2kΩ

0.1µF

7

4

+7.5V

0.01µF

6

0.01µF

25pF

2kΩ

10kΩ

3

2

56pF

+15V

+

7

0.01µF

6

-

4

5

1

8

100kΩ

OFFSET
ADJUST

2kΩ

0.1µF

Top Trace: Output

Center Trace: Input

FIGURE 8A. SMALL-SIGNAL RESPONSE (50mV/DIV.,

200ns/DIV.)

Top Trace: Output Signal; 2V/Div., 5µs/Div.

Center Trace: Difference Signa; 5mV/Div., 5µs/Div.

Bottom Trace: Input Signal; 2V/Div., 5µs/Div.

FIGURE 8B. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING

SETTLING TIME (MEASUREMENT MADE WITH
TEKTRONIX 7A13 DIFFERENTIAL AMPLIFIER)

FIGURE 8. SPLIT SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS

FIGURE 9A. OUTPUT WAVEFORM WITH INPUT SIGNAL

RAMPING (2V/DIV., 500µs/DIV.)

Top Trace:Output; 5V/Div., 200µs/Div.

Bottom Trace:Input Signal; 5V/Div., 200µs/Div.

FIGURE 9B. OUTPUT WAVEFORM WITH GROUND

REFERENCE SINE-WAVE INPUT

FIGURE 9. SINGLE SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS. (e.g., FOR USE IN
SINGLE-SUPPLY D/A CONVERTER; SEE FIGURE 9
IN AN6080)

9

+10.010V

9

7

4

CA3130, CA3130A

10V LOGIC INPUTS

LSB

987 654 321

36

CD4007A

“SWITCHES”

13

1

8

5

402K1%200K

806K
1%

14
11

10

2

CD4007A

“SWITCHES”

12 12

1%

8 5

100K1%806K1%806K

806K

1%

1%

6 3 101036

CD4007A

“SWITCHES”

1313 1 12

(2)

806K1%806K1%806K

MSB

1

58

(4)

1%

BIT

1
2
3
4
5

6 - 9

STANDARD

±0.1%
±0.2%
±0.4%
±0.8%
±1% ABS

REQUIRED

RATIO-MATCH

NOTE: All resistances are in ohms.

(8)

806K1%750K

OUTPUT

LOAD

VOLTAGE

ADJ

+15V

+

-

VOLTAGE

REGULATOR

2

3

2µF
25V

806K
1%

CA3085

7

4

0.001µF

62

1

6

+10.010V

8

22.1k
1%

REGULATED

1K

3.83k
1%

FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130

R

2

1

5

100kΩ

OFFSET

ADJUST

2KΩ

----------- -

4kΩ

7

4

+15V

=

R

------ -

R

6

2
1

0.01
µF

1N914

2kΩ

R

1

4kΩ

R

2

------ -

ain =

R3=R

R

3

20V

1V

= X =

R

1

X+X



------------------

1



1 - X

0.75



-----------

= 4kΩ



0.5

Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V

P-P

Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV

P-P

R

3

------------------------------------- -

R1+R2+R

2

= 6kΩ

-

2

CA3130

+

3

8

20pF

3

For X = 0.5:

1%

6

5.1kΩ

R

3

ADJUST

OFFSET

PEAK

2kΩ

PARALLELED

RESISTORS

CA3130

4

100K

NULL

0.1µF

+15V

7

+

-

5

1

8

2K

10K

3

VOLTAGE
FOLLOWER

2

56pF

0V

0V

Top Trace: Output Signal; 2V/Div.

Bottom Trace: Input Signal; 10V/Div.

Time base on both traces: 0.2ms/Div.

FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

10

CA3130, CA3130A

6V

INPUT;

6V

INPUT;

P-P

BW (-3dB) = 1.3MHz

0.3V

INPUT;

P-P

BW (-3dB) = 240kHz

10kΩ

+7.5V

0.01µF

7

+

3

CA3130

-

2

2kΩ

4

-7.5V

6

1N914

0.01µF

100

kΩ

OUTPUT

+

-

+DC

5µF

P-P

BW (-3dB) = 360kHz

0.3V

INPUT;

P-P

BW (-3dB) = 320kHz

10kΩ

+

3

CA3130

-

2

2kΩ

FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT

FIGURE 12. PEAK-DETECTOR CIRCUITS

CURRENT

LIMIT

3Ω

ADJ

R

1kΩ

2

7

4

-7.5V

+7.5V

6

0.01µF

1N914

0.01µF

+

100

kΩ

OUTPUT

-

+

-DC

5µF

+

+20V

INPUT

-

390Ω

0.01µF

IC

2

CA3086

IC

3

CA3086

10 7 3

Q

4

11815

2.2kΩ

+

-

11

1, 2

10

Q

9

8, 7

Q

6

Q

4

3

5

Q

2

3

4

62kΩ

1kΩ

Q

5

13

12

Q

R

1

4269

1

14

1kΩ

6

VOLTAGE
ADJUST

7

IC1

56pF

8

CA3130

4

1

-

+

100kΩ

20kΩ

ERROR
AMPLIFIER

2

3

0.01
µF

5µF
25V

30kΩ

OUTPUT

0 TO 13V

AT

40mA

+

-

Q

Q

2

3

25µF

1

14

Q

5

13

12

50kΩ

-

REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz

FIGURE 13. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)

11

CA3130, CA3130A

+

4.3kΩ

1W

+

100µF

+55V

INPUT

-

IC

2

CA3086 10, 11

Q

Q

4

3

9
8, 7

6

2.2kΩ

1, 2

Q

3
5

Q

4

1kΩ

62kΩ

1

2

5µF

+

-

Q

5

12

-

REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µV

FIGURE 14. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A)

UP TO 100kHz

RMS

2N2102

3.3kΩ

1W

14

13

50kΩ

2N3055

VOLTAGE
ADJUST

Q

2N2102

Q

4

1

1kΩ

6

7

IC

1

1Ω

10kΩ

Q

3

1000pF

8

CA3130

4

CURRENT
LIMIT
ADJUST

2N5294

1

ERROR
AMPLIFIER

+

-

+

43kΩ

3

10kΩ

2

8.2kΩ

+

-

100µF

OUTPUT:

0.1 TO 50V
AT 1A

Q

2

-

Error-Amplifier in Regulated-Power Supplies

The CA3130 is an ideal choice for error-amplifier service in
regulated power supplies since it can function as an error­amplifier when the regulated output voltage is required to
approach zero. Figure 13 shows the schematic diagram of a
40mA power supply capable of providing regulated output
voltage by continuous adjustment over the range from 0V to
13V. Q
function as zeners to provide supply-voltagefor the CA3130
comparator (IC
low impedance, temperature-compensated source of
adjustable reference voltage for the error amplifier.
Transistors Q
transistor-array lC) are connected in parallel as the series­pass element. Transistor Q
limiting device by diverting base drive from the series-pass
transistors, in accordance with the adjustment of resistor R

Figure 14 contains the schematic diagram of a regulated
power-supply capable of providing regulated output voltage
by continuous adjustment over the range from 0.1V to 50V
and currents up to 1A. The error amplifier (lC
associated with lC
although the output of lC
(Q

and Q4 in lC2 (a CA3086 transistor-array lC)

3

). Q1,Q2, and Q5in IC2are configured as a

1

, Q2, Q3, and Q4 in lC3 (another CA3086

1

in lC3 functions as a current-

5

) and circuitry

function as previously described,

2

) to provide adequate base drive for the Darlington-

4

is boosted by a discrete transistor

1

1

connected series-pass transistors Q

, Q2. Transistor Q

1

3

functions in the previously described current-limiting circuit.

Multivibrators

The exceptionally high input resistance presented by the
CA3130 is an attractive feature for multivibrator circuit
design because it permits the use of timing circuits with high
R/C ratios. The circuit diagram of a pulse generator (astable
multivibrator), with provisions for independent control of the
“on” and “off” periods, is shown in Figure 15. Resistors R
and R2 are used to bias the CA3130 to the mid-point of the
supply-voltage and R
repetition rate is selected by positioning S

is the feedback resistor. The pulse

3

to the desired

1

position and the rate remains essentially constant when the
resistors which determine “on-period” and “off-period” are
adjusted.

.

2

Function Generator

Figure 16 contains a schematic diagram of a function
generator using the CA3130 in the integrator and threshold
detector functions. This circuit generates a triangular or
square-wave output that can be swept over a 1,000,000:1
range (0.1Hz to 100kHz) by means of a single control, R
voltage-control input is also available for remote sw eep­control.

1

. A

1

12

CA3130, CA3130A

The heart of the frequency-determining system is an
operational-transconductance-amplifier (OTA) (see Note 10),
lC

, operated as a voltage-controlled current-source. The

1

output, I
capacitor,C

, is a current applied directly to the integrating

O

, in the feedback loop of the integrator lC2, using

1

a CA3130, to provide the triangular-wave output.
Potentiometer R

is used to adjust the circuit for slope

2

symmetry of positive-going and negative-going signal
excursions.

Another CA3130, IC

, is used as a controlled switch to set

3

the excursion limits of the triangular output from the
integrator circuit. Capacitor C

is a “peaking adjustment” to

2

optimize the high-frequency square-wave performance of
the circuit.

Potentiometer R

is adjustable to perfect the “amplitude

3

symmetry” of the square-wave output signals. Output from
the threshold detector is fed back via resistor R
of lC

so as to toggle the current source from plus to minus

1

to the input

4

in generating the linear triangular wave.

Operation with Output-Stage Power-Booster

The current-sourcing and-sinking capability of the CA3130
output stage is easily supplemented to provide power-boost
capability. In the circuit of Figure 17, three CMOS transistor­pairs in a single CA3600E (see Note 12) lC arrayare shown
parallel connected with the output stage in the CA3130. In
the Class A mode of CA3600E shown, a typical device
consumes 20mA of supply current at 15V operation. This
arrangement boosts the current-handling capability of the
CA3130 output stage by about 2.5X.

+15V

0.01µF

ON-PERIOD

R

1

100kΩ

R

2

100kΩ

FREQUENCY RANGE:

FIGURE 15. PULSEGENERATOR (ASTABLEMULTIVIBRATOR)

ADJUST

1MΩ

2kΩ 2kΩ

R

3

100kΩ

1µF

0.1µF

0.01µF

POSITION OF S

0.001µF

WITH PROVISIONS FOR INDEPENDENT CONTROL
OF “ON” AND “OFF” PERIODS

S

1

0.01µF

0.1µF
1µF

OFF-PERIOD

ADJUST

1MΩ

3

+
CA3130

-

2

0.001µF

PULSE PERIOD

1

4µs to 1ms
40µs to 10ms

0.4ms to 100ms
4ms to 1s

7

6

4

OUTPUT

2kΩ

The amplifier circuit in Figure 17 employs feedback to
establisha closed-loop gain of 48dB. The typical large-signal
bandwidth (-3dB) is 50kHz.

NOTE:

9. See file number 619 for technical information.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

13

CA3130, CA3130A

R

4

VOLTAGE-CONTROLLED

CURRENT SOURCE

IC

1

3

2

10MΩ

10kΩ

+

-

10kΩ

R

100kΩ

-7.5V

3kΩ

+7.5V

2

SLOPE
SYMMETRY
ADJUST

VOLTAGE
CONTROLLED
INPUT

3kΩ

NOTE:

10. See file number 475 and AN6668 for technical information.

FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)

270kΩ

+7.5V

7

I

O

6

CA3080A

4

(NOTE 10)

5

-7.5V
+7.5V

22kΩ

FREQUENCY

1

ADJUST
(100kHz MAX)

-7.5V

R

INTEGRATOR

C

100pF

IC

2

-

2

CA3130

+

3

1

56pF

+15V

1

7

8

+7.5V

4

6

-7.5V

HIGH - FREQ.

ADJUST

3 - 30pF

C

2

39kΩ

AMPLITUDE
SYMMETRY
ADJUST

THRESHOLD

DETECTOR

150kΩ

IC

3

+

3

CA3130

-

2

1

R

3

100kΩ

7

5

+7.5V

6

4

-7.5V

INPUT

= 48dB

A

V(CL)

LARGE SIGNAL
BW (-3 dB) = 50kHz

1µF

1µF

750kΩ

2kΩ

7

+

CA3130

-

4

8

0.01µF

6

CA3600E
(NOTE 12)

1MΩ

3

2

510kΩ

Q

P1

Q

N1

14

Q

P2

13 1

Q

N2

2 11

Q

P3

1036

58

Q

N3

4 97

500µF

12

R

= 100Ω

L

(P

= 150mW

O

AT THD = 10%)

NOTES:

11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.

12. See file number 619.

FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130

14

Typical Performance Curves

150

LOAD RESISTANCE = 2kΩ

140

130

120

110

CA3130, CA3130A

120

100

80

60

40

AOL

SUPPLY VOLTAGE: V+ = 15V; V- = 0
T

= 25oC

A

φ OL

1
2

3

4

4

3

2

1

-100

-200

-300

100

90

OPEN LOOP VOLTAGE GAIN (dB)

80

-100 -50 0 50 100
TEMPERATURE (oC)

20

OPEN LOOP VOLTAGE GAIN (dB)

0

1

10

10210310410510610710

FREQUENCY (Hz)

= 9pF, CC = 0pF, RL = ∞

1 - C

L

= 30pF, CC = 15pF, RL = 2kΩ

2 - C

L

= 30pF, CC = 47pF, RL = 2kΩ

3 - C

L

4 - CL = 30pF, CC = 150pF, RL = 2kΩ

FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE FIGURE 19. OPEN-LOOP RESPONSE

17.5
LOAD RESISTANCE =

TA = 25oC

12.5

V- = 0

10

7.5

5

2.5

QUIESCENT SUPPLY CURRENT (mA)

0

6 8 10 12 14 16 18

4

∞

OUTPUT VOLTAGE BALANCED = V+/2

OUTPUT VOLTAGE HIGH = V+
OR LOW = V-

TOTAL SUPPLY VOLTAGE (V)

FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

50

NEGATIVE SUPPLY VOLTAGE = 0V

TA = 25oC

10

1

POSITIVE SUPPLY VOLTAGE = 5V

10V

15V

14

OUTPUT VOLTAGE = V+/2

12

V- = 0

10

8

6

4

2

QUIESCENT SUPPLY CURRENT (mA)

0

0246810121416

TOTAL SUPPLY VOLTAGE (V)

FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

50

NEGATIVE SUPPLY VOLTAGE = 0V

= 25oC

T

A

10

POSITIVE SUPPLY VOLTAGE = 5V

1

10V

OPEN LOOP PHASE (DEGREES)

8

TA = -55oC

25oC

125oC

15V

0.1

STAGE TRANSISTOR (V)

0.01

VOLTAGE DROP ACROSS PMOS OUTPUT

0.001

0.001 0.01 0.1 1.0 10 100
MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR

(Q8) vs LOAD CURRENT

15

0.1

STAGE TRANSISTOR (V)

0.01

VOLTAGE DROP ACROSS NMOS OUTPUT

0.001

0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA)

FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR

(Q12) vs LOAD CURRENT

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