Datasheet CA3096C, CA3096A, CA3096 Datasheet (Intersil Corporation)

CA3096, CA3096A,

CA3096C

December 1997

Applications

• Five-Independent Transistors

- Three NPN and

- Two PNP

• Differential Amplifiers

• DC Amplifiers

• Sense Amplifiers

• Level Shifters

• Timers

• Lamp and Relay Drivers

• Thyristor Firing Circuits

• Temperature Compensated Amplifiers

• Operational Amplifiers

Ordering Information

PART NUMBER

(BRAND)

CA3096AE -55 to 125 16 Ld PDIP E16.3
CA3096AM

(3096A)
CA3096AM96

(3096A)
CA3096CE -55 to 125 16 Ld PDIP E16.3
CA3096E -55 to 125 16 Ld PDIP E16.3
CA3096M

(3096)
CA3096M96

(3096)

TEMP.

RANGE (oC) PACKAGE

-55 to 125 16 Ld SOIC M16.15

-55 to 125 16 Ld SOIC Tape
and Reel

-55 to 125 16 Ld SOIC M16.15

-55 to 125 16 Ld SOIC Tape
and Reel

Pinout

CA3096, CA3096A, CA3096C

(PDIP, SOIC)

TOP VIEW

16

1

2

Q

1

3

4

5

6

7

8

Q

5

Q

2

Q

4

Q

3

SUBSTRATE

15

14

13

12

11

10

9

PKG.

NO.

M16.15

M16.15

NPN/PNP Transistor Arrays

Description

The CA3096C, CA3096, and CA3096A are general purpose
high voltage silicon transistor arrays. Each array consists of
five independent transistors (two PNP and three NPN types)
on a common substrate, which has a separate connection.
Independent connections for each transistor permit maxi­mum flexibility in circuit design.

Types CA3096A, CA3096, and CA3096C are identical, except
that the CA3096A specifications include parameter matching
and greater stringency in I
CA3096C is a relaxed version of the CA3096.

CA3096, CA3096A, CA3096C
Essential Differences

CHARACTERISTIC CA3096A CA3096 CA3096C

V

(BR)CEO

V

(BR)CBO

hFE at 1mA

hFE at 100µA

I

CBO

I

CEO

V

CE SAT

|VIO| (mV) (Max)

|IIO| (µA) (Max)

(V) (Min)

NPN 35 35 24
PNP -40 -40 -24

(V) (Min)

NPN 45 45 30
PNP -40 -40 -24

NPN 150-500 150-500 100-670
PNP 20-200 20-200 15-200

PNP 40-250 40-250 30-300

(nA) (Max)

NPN 40 100 100
PNP -40 -100 -100

(nA) (Max)

NPN 100 1000 1000
PNP -100 -1000 -1000

(V) (Max)

NPN 0.5 0.7 0.7

NPN 5 - ­PNP 5 - -

NPN 0.6 - ­PNP 0.25 - -

CBO

, I

, and VCE(SAT). The

CEO

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

1

File Number 595.4

CA3096, CA3096A, CA3096C

Absolute Maximum Ratings Operating Conditions

NPN PNP

Collector-to-Emitter Voltage, V

CEO

CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 35V -40V

CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V -24V

Collector-to-Base Voltage, V

CBO

CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V -40V

CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V -24V

Collector-to-Substrate Voltage, V

CIO

(Note 1)

CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . 45V -

CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V -

Emitter-to-Substrate Voltage, V

EIO

CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . - -40V

CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - -24V

Emitter-to-Base Voltage, V

EBO

CA3096, CA3096A . . . . . . . . . . . . . . . . . . . . . . 6V -40V

CA3096C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V -24V

Collector Current, IC (All Types). . . . . . . . . . . . 50mA -10mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The collector of each transistor of the CA3096 is isolated from the substrate by an integral diode. The substrate (Terminal 16) must be
connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor
action.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

3. Care must be taken to avoid exceeding the maximum junction temperature. Use the total power dissipation (all transistors) and thermal
resistances to calculate the junction temperature.

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC

Thermal Information

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Maximum Pow er Dissipation (Each Transistor, Note 3) . . . . . 200mW

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Electrical Specifications For Equipment Design, At T

CA3096 CA3096A CA3096C

PARAMETER

TEST

CONDITIONS

= 25oC

A

DC CHARACTERISTICS FOR EACH NPN TRANSISTOR

I

CBO

VCB = 10V,

- 0.001 100 - 0.001 40 - 0.001 100 nA

IE = 0

I

CEO

VCE = 10V,

- 0.006 1000 - 0.006 100 - 0.006 1000 nA

IB = 0

V

(BR)CEO

V

(BR)CBO

IC = 1mA, IB = 0 35 50 - 35 50 - 24 35 - V
IC = 10µA,

45 100 - 45 100 - 30 80 - V

IE = 0

V

(BR)CIO

ICI = 10µA,

45 100 - 45 100 - 30 80 - V

IB = IE = 0

V

(BR)EBO

IE = 10µA,

68-68-68 - V

IC = 0

V

Z

V

CE SAT

IZ = 10µA 6 7.9 9.8 6 7.9 9.8 6 7.9 9.8 V
lC = 10mA,

- 0.24 0.7 - 0.24 0.5 - 0.24 0.7 V

IB = 1mA
VBE (Note 4) IC = 1mA,
hFE (Note 4) 150 390 500 150 390 500 100 390 670

VCE = 5V

|∆VBE/∆T| (Note 4) IC = 1mA,

0.6 0.69 0.78 0.6 0.69 0.78 0.6 0.69 0.78 V

- 1.9 - - 1.9 - - 1.9 - mV/oC

VCE = 5V

DC CHARACTERISTICS FOR EACH PNP TRANSISTOR

I

CBO

VCB = -10V,

- -0.06 -100 - -0.006 -40 - -0.06 -100 nA

IE = 0

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

2

CA3096, CA3096A, CA3096C

Electrical Specifications For Equipment Design, At T

TEST

PARAMETER

I

CEO

CONDITIONS

VCE = -10V,

IB = 0
V

(BR)CEO

IC = -100µA,

IB = 0
V

(BR)CBO

IC = -10µA,

IE = 0
V

(BR)EBO

IE = -10µA,

IC = 0
V

(BR)ElO

IEI = 10µA,

IB = IC = 0
V

CE SAT

IC = -1mA,

IB = -100µA
VBE (Note 4) IC = -100µA,

VCE = -5V
hFE (Note 4) IC = -100µA,

VCE = -5V

IC = -1mA,

VCE = -5V
|∆VBE/∆T| (Note 4) IC = -100µA,

VCE = -5V
I

CBO

I

CEO

V

(BR)CEO

V

(BR)CBO

V

(BR)CIO

V

(BR)EBO

Collector-Cutoff Current V
Collector-Cutoff Current V
Collector-to-Emitter Breakdown Voltage V
Collector-to-Base Breakdown Voltage h
Collector-to-Substrate Breakdown Voltage |∆VBE/∆T| Magnitude of Temperature Coefficient:
Emitter-to-Base Breakdown Voltage

NOTE:

4. Actual forcing current is via the emitter for this test.

CA3096 CA3096A CA3096C

- -0.12 -1000 - -0.12 -100 - -0.12 -1000 nA

-40 -75 - -40 -75 - -24 -30 - V

-40 -80 - -40 -80 - -24 -60 - V

-40 -100 - -40 -100 - -24 -80 - V

40 100 - 40 100 - 24 80 - V

- -0.16 -0.4 - -0.16 -0.4 - -0.16 -0.4 V

-0.5 -0.6 -0.7 -0.5 -0.6 -0.7 -0.5 -0.6 -0.7 V

40 85 250 40 85 250 30 85 300

20 47 200 20 47 200 15 47 200

- 2.2 - - 2.2 - - 2.2 - mV/oC

= 25oC (Continued)

A

Z
CE SAT
BE

FE

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Emitter-to-Base Zener Voltage
Collector-to-Emitter Saturation Voltage
Base-to-Emitter Voltage
DC Forward-Current Transfer Ratio

(for each transistor)

Electrical Specifications For Equipment Design At T

= 25oC (CA3096A Only)

A

CA3096A

PARAMETER SYMBOL TEST CONDITIONS

FOR TRANSISTORS Q1 AND Q2 (AS A DIFFERENTIAL AMPLIFIER)

Absolute Input Offset Voltage |VIO|VCE = 5V, IC = 1mA - 0.3 5 mV
Absolute Input Offset Current |IIO| - 0.07 0.6 µA
Absolute Input Offset Voltage

Temperature Coefficient

∆V

IO

----------------- -

∆T

- 1.1 - µV/oC

FOR TRANSISTORS Q4 AND Q5 (AS A DIFFERENTIAL AMPLIFIER)

Absolute Input Offset Voltage |VIO|VCE = -5V, IC = -100µA

- 0.15 5 mV

RS= 0

Absolute Input Offset Current |IIO| - 2 250 nA
Absolute Input Offset Voltage

Temperature Coefficient

∆V

IO

----------------- -

∆T

- 0.54 - µV/oC

3

UNITSMIN TYP MAX

CA3096, CA3096A, CA3096C

Electrical Specifications Typical Values Intended Only for Design Guidance At T

= 25oC

A

TYPICAL

PARAMETER SYMBOL TEST CONDITIONS

VALUES UNITS

DYNAMIC CHARACTERISTICS FOR EACH NPN TRANSISTOR

Noise Figure (Low Frequency) NF f = 1kHz, VCE = 5V, IC = 1mA, RS = 1kΩ 2.2 dB
Low-Frequency, Input Resistance R
Low-Frequency Output Resistance R

I

O

f = 1.0kHz, VCE = 5V IC = 1 mA 10 kΩ
f = 1.0kHz, VCE = 5V IC = 1 mA 80 kΩ

Admittance Characteristics

Forward Transfer Admittance

Input Admittance

Output Admittance

Gain-Bandwidth Product f

g

f = 1MHz, VCE = 5V, IC = 1mA 7.5 mS

y

FE

y

y

OE

FE

b

f = 1MHz, VCE = 5V, IC = 1mA -j13 mS

FE

g

f = 1MHz, VCE = 5V, IC = 1mA 2.2 mS

IE

IE

b

f = 1MHz, VCE = 5V, IC = 1mA j3.1 mS

IE

g

f = 1MHz, VCE = 5V, IC = 1mA 0.76 mS

OE

b

f = 1MHz, VCE = 5V, IC = 1mA j2.4 mS

OE

T

VCE = 5V, IC = 1.0mA 280 MHz

VCE = 5V, IC = 5mA 335 MHz
Emitter-To-Base Capacitance C
Collector-To-Base Capacitance C
Collector-To-Substrate Capacitance C

EB
CB

CI

VEB = 3V 0.75 pF

VCB = 3V 0.46 pF

VCI = 3V 3.2 pF

DYNAMIC CHARACTERISTICS FOR EACH PNP TRANSISTOR

Noise Figure (Low Frequency) NF f = 1kHz, IC = 100µA, RS = 1kΩ 3dB
Low-Frequency Input Resistance R
Low-Frequency Output Resistance R
Gain-Bandwidth Product f
Emitter-To-Base Capacitance C
Collector-To-Base Capacitance C
Base-To-Substrate Capacitance C

I

O

T
EB
CB

BI

f = 1kHz, VCE = 5V, IC = 100µA27kΩ
f = 1kHz, VCE = 5V, IC = 100µA 680 kΩ
VCE = 5V, IC = 100µA 6.8 MHz
VEB = -3V 0.85 pF
VCB = -3V 2.25 pF
VBI = 3V 3.05 pF

Typical Applications

(SUBSTRATE)

f

500Ω

1

V+ = 10V

f

500Ω

2

NOTE: F

2

1

0.1µF

3

1kΩ

1kΩ

0.1µF

6

Q

5

2

4

OR F2 < 10kHz

1

Q

Q

5

44003

4

11

8

15 10 12
14

13

3kΩ

97

16

1µF3kΩ

OUTPUT

FIGURE 1. FREQUENCY COMPARATOR USING CA3096 FIGURE 2. FREQUENCY COMPARATOR CHARACTERISTICS

9

CENTER FREQUENCY: 1kHz

8

7

6

5

4

3

OUTPUT VOLTAGE (V)

2

1

0

-20 -10 0 10 20
f

- f1 > 0 f1 = f

2

FREQUENCY DEVIATION (kHz)

2

f1 - f2 > 0

4

Typical Applications (Continued)

CA3096, CA3096A, CA3096C

120V

3

AC

6.8kΩ

2W

NTC

SENSOR

2

12V

+

-

11

100µF

Q

1

1

R

P

Q

3

16

987

5.1kΩ 10kΩ

1310

Q

5

Q

4

15

12

10kΩ10kΩ 5.1kΩ

14

5

FIGURE 3. LINE-OPERATED LEVEL SWITCH USING CA3096A OR CA3096

13

Q

14

15 10

40841
MOSFET

5

11

Q

4

1kΩ

12

20kΩ 5kΩ 5kΩ

6

3

1

Q1Q

2

5 8

20kΩ

42

6

4

+6V

9

7

Q

Q

1kΩ

2

3

G

LOAD

OUTPUT

MT

MT

1

T2300B

2

36

---------------

V

±=

T

IOR

L

IF IO = 1mA AND RL = 1kΩ

= ± 36mV

V

T

V

IN

FIGURE 5. CA3096A SMALL-SIGNAL ZERO VOLTAGE DETECTOR HAVING NOISE IMMUNITY

50MΩ

5µF

1kΩ 3.9kΩ 10kΩ

TIME DELAY CHANGES ±7%
FOR SUPPLY VOLTAGE CHANGE OF ±10%

FIGURE 4. ONE-MINUTE TIMER USING CA3096A AND A MOSFET

V+

1kΩ

R

L

E

O

2kΩ

15

Q

5

13 6

Q

2

100Ω

5

42

I

O

Q

1kΩ

3

7

V-

100Ω

1

1kΩ

10

3

Q

1kΩ

12

Q

4

11

14

1

9

8

+V

16

T

V

IN

-V

T

E

O

0

t

t

5

Typical Applications (Continued)

CA3096, CA3096A, CA3096C

INPUT

100kΩ

13

14
15

Q

5

11

1.5MΩ

500kΩ

1.5V

10

Q

4

12

1

5µF

10kΩ

3

6

Q

Q

1

2

2

4

1kΩ

5

LAMP GE 2158D
OR EQUIVALENT

2kΩ

8

2kΩ

16

(SUBSTRATE)

9

Q

3

7

FIGURE 6. TEN-SECOND TIMER OPERATED FROM 1.5V SUPPLY USING CA3096

+6V

1%

11

51kΩ

1%

100kΩ

1%

10

13

Q

Q

4

12

14

5

100kΩ

15

1%

51kΩ

1%

6.2kΩ

1%

6

5

Q2Q

300Ω

1%

6.2kΩ

1%

3

1

24

9

Q

8

3

7

1kΩ

1%

OUTPUT

1

5kΩ

1%

16

-6V

NOTES:

5. Can be operated with either dual
supply or single supply.

6. Wide-input common mode range
+5V to -5V.

7. Low bias current: <1µA.

FIGURE 7. CASCADE OF DIFFERENTIAL AMPLIFIERS USING CA3096A

70

60

50

40

30

VOLTAGE GAIN (dB)

20

10

1 10 100 1000

FREQUENCY (kHz)

FIGURE 8. FREQUENCY RESPONSE

6

Typical Performance Curves

10

CA3096, CA3096A, CA3096C

4

10

3

10

1

-1

10

ZENER CURRENT (mA)

-2

10

7 7.5 8 8.5 9

ZENER VOLTAGE (V)

V

Z

2

10

10

1

COLLECTOR CUT-OFF CURRENT (pA)

-1

10

-100 -75 -50 -25 0 25 50 75 100
TEMPERATURE (oC)

VCE = 10V

FIGURE 9. BASE-TO-EMITTER ZENER CHARACTERISTIC (NPN) FIGURE 10. COLLECTOR CUT-OFF CURRENT (I

TEMPERATURE (NPN)

3

10

2

10

VCB = 15V

10

1

VCB = 10V

VCB = 5V

500

400

300

200

TA = 85oC

TA = 25oC

TA = -40oC

VCE = 5V

) vs

CEO

-1

10

COLLECTOR CUT-OFF CURRENT (pA)

-2

10

-75 -50 -25 0 25 50 75 100
TEMPERATURE (oC)

FIGURE 11. COLLECTOR CUT-OFF CURRENT (I

TEMPERATURE (NPN)

0.9
VCE = 5V

0.8

0.7

0.6

0.5

BASE TO EMITTER VOLTAGE (V)

0.4

0.01 0.1 1 10
COLLECTOR CURRENT (mA)

CBO

) vs

100

DC FORW ARD CURRENT TRANSFER RATIO

0

0.01 0.1 1 10
COLLECTOR CURRENT (mA)

FIGURE 12. TRANSISTOR (NPN) hFE vs COLLECTOR

CURRENT

= 10mA, 1.67mV/oC

I

0.9

0.8

0.7

0.6

0.5

BASE TO EMITTER VOLTAGE (V)

0.4

-40 -20 0 20 40 60 80 100

TEMPERATURE (

C

= 5mA, 1.77mV/oC

I

C

I

= 1mA, 1.90mV/oC

C

I

= 100µA, 2.05mV/oC

C

o

C)

FIGURE 13. VBE (NPN) vs COLLECTOR CURRENT FIGURE 14. VBE (NPN) vs TEMPERATURE

7

CA3096, CA3096A, CA3096C

Typical Performance Curves (Continued)

TA = 85oC

1.0
TA = 25oC

0.8

0.6

0.4

0.2

COLLECTOR TO EMITTER

SATURATION VOLTAGE (V)

0.1

0.1 1.0 10 100
COLLECTOR CURRENT (mA)

β = 10

TA = -40oC

4

10

3

10

VCE = -10V

2

10

10

COLLECTOR CUT-OFF CURRENT (pA)

1

-50 -25 0 25 50 75 100
TEMPERATURE (

VCE = -15V

o

C)

VCE = -5V

FIGURE 15. V

3

10

2

10

10

COLLECTOR CUT-OFF CURRENT (pA)

1

-50 -25 0 25 50 75 100

(NPN) vs COLLECTOR CURRENT FIGURE 16. COLLECTOR CUT-OFF CURRENT (I

CE SAT

VCB = -15V

VCB = -10V

VCB = -5V

TEMPERATURE (

o

C)

FIGURE 17. COLLECTOR CUT -OFF CURRENT (I

TEMPERATURE (PNP)

100

IC = 100µA

80

IC = 10µA

60

IC = 1mA

40

20

DC FORWARD CURRENT TRANSFER RATIO

0

-40 -20 0 20 40 60 80

IC = 5mA

TEMPERATURE (

o

C)

CBO

) vs

VCE = 5V

) vs

CEO

TEMPERATURE (PNP)

110
100

90
80
70
60
50
40
30
20
10

DC FORWARD CURRENT TRANSFER RATIO

0

0.01 0.1 1.0 10

VCE = 5V

VCE = 1V

COLLECTOR CURRENT (mA)

VCE = 20V

FIGURE 18. TRANSISTOR (PNP) hFE vs COLLECTOR CURRENT

1.0
VCE = 5V

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

BASE TO EMITTER VOLTAGE (V)

0.1

0

0.01 0.1 1.0 10
COLLECTOR CURRENT (mA)

FIGURE 19. TRANSISTOR (PNP) hFE vs TEMPERATURE FIGURE 20. VBE (PNP) vs COLLECTOR CURRENT

8

CA3096, CA3096A, CA3096C

Typical Performance Curves (Continued)

0.9

0.8

0.7

0.6
IC = 100µA, -2.2mV/oC

0.5

BASE TO EMITTER VOLTAGE (V)

0.4

-40 -20 0 20 40 60 80

FIGURE 21. VBE (PNP) vs TEMPERATURE FIGURE 22. MAGNITUDE OF INPUT OFFSET V OLTA GE |VIO| vs

= 5mA, ∆VBE/∆T - 0.97mV/oC

I

C

IC = 1mA, -1.84mV/oC

TEMPERATURE (

o

C)

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

MAGNITUDE OF INPUT OFFSET V OLTAGE (mV)

0.01 0.1 1.0 10

COLLECTOR CURRENT (mA)

COLLECTOR CURRENT FOR NPN TRANSISTOR
Q1 - Q

2

0.5

0.4

0.3

0.2

0.1

0

MAGNITUDE OF INPUT OFFSET V OLTAGE (mV)

0.01 0.1 1 10
COLLECTOR CURRENT (mA)

FIGURE 23. MAGNITUDE OF INPUT OFFSET VOL TAGE |VIO| vs

COLLECTOR CURRENT FOR PNP TRANSISTOR
Q4 - Q

5

18
16

IC = 3mA

14
12
10

1mA

8
6

NOISE FIGURE (dB)

4
2
0

0.01 0.1 1 10 100

100µA

FREQUENCY (kHz)

10µA

R

SOURCE

= 1kΩ

18

R

16
14
12
10

1mA

8
6

NOISE FIGURE (dB)

4
2
0

0.01 0.1 1.0 10 100

SOURCE

100µA

= 500Ω

IC = 3mA

10µA

FREQUENCY (kHz)

FIGURE 24. NOISE FIGURE vs FREQUENCY FOR NPN

TRANSISTORS

28

R

24

20

16

12

NOISE FIGURE (dB)

8

4

0

0.01 0.1 1.0 10 100

SOURCE

10µA

= 10kΩ

IC = 3mA

1mA

100µA

FREQUENCY (kHz)

FIGURE 25. NOISE FIGURE vs FREQUENCY FOR NPN

TRANSISTORS

FIGURE 26. NOISE FIGURE vs FREQUENCY FOR NPN

TRANSISTORS

9

CA3096, CA3096A, CA3096C

Typical Performance Curves (Continued)

28

24

20

100µA

16

12

NOISE FIGURE (dB)

10µA

8

4

10µA

0

0.01 0.1 1 10 100

IC = 1mA

FREQUENCY (kHz)

R

SOURCE

R

100µA

SOURCE

= 100kΩ

= 1MΩ

FIGURE 27. NOISE FIGURE vs FREQUENCY FOR NPN

TRANSISTORS

4.0

3.5

3.0

2.5

C

CI

400

VCE = 5V

300

200

100

GAIN-BANDWIDTH PRODUCT (MHz)

0

0.1 1.0 10
COLLECTOR CURRENT (mA)

FIGURE 28. GAIN-BANDWIDTH PRODUCT vs COLLECTOR

CURRENT (NPN)

1000

f = 1kHz

100

NPN

2.0

1.5

CAPACITANCE (pF)

1.0

0.5

012345678910

C

EB

C

CB

BIAS VOLTAGE (V)

10

INPUT RESISTANCE (kΩ)

1

0.01 1 100.1

PNP

COLLECTOR CURRENT (mA)

FIGURE 29. CAPACITANCE vs BIAS VOLTAGE (NPN) FIGURE 30. INPUT RESISTANCE vs COLLECTOR CURRENT

4

10

3

10

2

10

10

OUTPUT RESISTANCE (kΩ)

1

0.01 1.0 100.1

f = 1kHz

NPN

PNP

COLLECTOR CURRENT (mA)

40

) OR

) (mS)

FE

FE

30

20

10

0

-10

-20

FORW ARD TRANSFER CONDUCTANCE (g

FORW ARD TRANSFER SUSCEPTANCE (b

1 10 100

gFEIC = 1mA

gFE100µA

bFE100µA

bFE1mA

FREQUENCY (MHz)

FIGURE 31. OUTPUT RESISTANCE vs COLLECTOR CURRENT FIGURE 32. FORWARD TRANSCONDUCTANCE vs FREQUENCY

10

CA3096, CA3096A, CA3096C

Typical Performance Curves (Continued)

6

g

IE

b

IE

5

) OR

) (mS)

IE

IE

4

3

2

1

INPUT CONDUCTANCE (g

INPUT SUSCEPTANCE (b

0

1 10 100

100µA

10µA
1mA

FREQUENCY (MHz)

FIGURE 33. INPUT ADMITTANCE vs FREQUENCY FIGURE 34. OUTPUT ADMITTANCE vs FREQUENCY

IC = 10mA

10mA

1mA

100µA

10µA

2.5

) OR

) (mS)

2.0

OE

OE

1.5

1.0

0.5

OUTPUT CONDUCTANCE (g

OUTPUT SUSCEPTANCE (b

100µA

0

1 10 100

FREQUENCY (MHz)

b

OE

100µA

IC = 1mA

b

OE

1mA

g

OE

g

OE

30

R

20

10

NOISE FIGURE (dB)

0

0.01 0.1 1.0 10 100

SOURCE

10µA

100µA

= 500Ω

IC = 1mA

FREQUENCY (kHz)

30

R

20

10

NOISE FIGURE (dB)

0

0.01 0.1 1 10 100

SOURCE

100µA

= 1kΩ

10µA

IC = 1mA

FREQUENCY (kHz)

FIGURE 35. NOISE FIGURE vs FREQUENCY (PNP) FIGURE 36. NOISE FIGURE vs FREQUENCY (PNP)

40

R

30

20

SOURCE

= 10kΩ

IC = 1mA

8

VCE = 5V

7

6

NOISE FIGURE (dB)

10

10µA

0

0.01 0.1 1.0 10 100

100µA

FREQUENCY (kHz)

5

GAIN-BANDWIDTH PRODUCT (MHz)

4

0.1 1.0 10
COLLECTOR CURRENT (mA)

FIGURE 37. NOISE FIGURE vs FREQUENCY (PNP) FIGURE 38. GAIN-BANDWIDTH PRODUCT vs COLLECTOR

CURRENT (PNP)

11

CA3096, CA3096A, CA3096C

Typical Performance Curves (Continued)

6

5

4

CAPACITANCE (pF)

Metallization Mask Layout

3

C

BC

2

C

1

0

012345678910

BE

BIAS VOLTAGE (V)

C

BI

FIGURE 39. CAPACITANCE vs BIAS VOLTAGE (PNP)

CA3096H

403020100

40

30

20

10

37-45

(0.940-1.143)

0

4-10 (0.102-0.254)

37-45

(0.940-1.143)

Dimensions in parentheses are in millimeters and are derived from the
basic inch dimensions as indicated. Grid graduations are in mils (10
inch).

The photographs and dimensions represent a chip when it is part of
the wafer. When the wafer is cut into chips, the cleavage angles are
57 degrees instead of 90 degrees with respect to the face of the chip .
Therefore, the isolated chip is actually 7mils (0.17mm) larger in both
dimensions.

12

-3

CA3096, CA3096A, CA3096C

Dual-In-Line Plastic Packages (PDIP)

E

C

L

e

A

C

e

B

BASE

PLANE

SEATING

PLANE

D1

B1

D

A2

A1

A

L

e

C

S

-C-

D1

e

B

0.010 (0.25) C AMB

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JE­DEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic-

e

A

ular to datum .

-C-

7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169

NOTESMIN MAX MIN MAX

Rev. 0 12/93

13

CA3096, CA3096A, CA3096C

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

0.25(0.010) B

H

E

-B-

SEATING PLANE

D

A

-C-

M

L

h x 45

M

o

α

e

B

0.25(0.010) C AMB

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

A1

0.10(0.004)

S

C

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6

N16 167

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.inter sil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

14