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Multimedia ICs
Audio digital delay (KARAOKE echo)
BU9252S / BU9252F
The BU9252S and BU9252F are digital delays specifically for Karaoke systems. Each has an internal sample hold
circuit, an 8-bit A / D and D / A converter and 2kB SRAM, and allows for the selection of one of eight delay times just
by attaching an inexpensive ceramic resonator.
A digital echo system can be formed by using either of these ICs together with the BA7725S or BA7725FS.
•
Applications
Karaoke echo system
Electronic circuits that require signal delays
•
Features
•
Block diagram
1
S / H
A
IN
AGND
A
OUT
AVDD
DCNT0
DCNT1
DCNT2
GND
V
DD
TST0
TST1
TST2
TDIN
TDO0
TDO1
OSCI
OSCO
S / H
8 × 2k SRAM
ADDRESS COUNTER
AND
MAIN TIMING
8bit
A / D
8bit
D / A
TEST CIRCUIT
2
354
6
7
8
9
18
17
16
15
14
13
12
11
10
1) Internal digital delay circuit.
2) Internal 8-bit A / D converter. Sample rate. (14.22kHz
when f
OSC = 455kHz).
3) Internal 2k bytes data SRAM.
4) Internal 8-bit D / A converter.
5) CMOS design for low power consumption.
6) Internal sample hold circuit.
7) Internal feedback resistors and capacitors for oscillator circuits.
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Multimedia ICs BU9252S / BU9252F
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Pin descriptions
Pin name
1 S / H 10 OSCO
2A
IN 11 OSCI
3 AGND 12 TDO1
4A
OUT 13 TDO0
5AV
DD 14 TDIN
6 DCNT0 15 TST2
7 DCNT1 16 TST1
8 DCNT2 17 TST0
9 GND 18 V
DD
Pin No. Function Pin No. Pin name
Analog input
Analog output
Analog circuit power supply
Delay setting input
Delay setting input
Delay setting input
Function
For attaching sample-and-hold capacitor
Analog circuit ground
Digital circuit ground
Test pin (output)
Test pin (output)
Test pin (input)
Test mode setting
Test mode setting
Test mode setting
Digital circuit power supply
Oscillator pin 1
Oscillator pin 2
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Multimedia ICs BU9252S / BU9252F
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Input / output circuits
Pin name Pin No. Internal equivalent circuit Pin name Pin No. Internal equivalent circuit
S / H 1
OSCI
OSCO
11
10
A
IN 2
TDIN
DCNT0
DCNT2
14
6
7
8
4
TDO0
TDO1
13
12
TST0
TST1
TST2
17
16
15
DCNT1
A
OUT
D / A
+
–
Built-in 0.875x
amplifier as
output buffer.
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Multimedia ICs BU9252S / BU9252F
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Absolute maximum ratings (Ta = 25°C)
Parameter Symbol Limits Unit
Power supply voltage V
DD – 0.3 ~ + 7.0 V
Power
dissipation
mW
Storage temperature – 55 ~ + 125 °C
Input voltage V
IN – 0.3 ~ VDD + 0.3 V
Output voltage V
OUT – 0.3 ~ VDD + 0.3 V
BU9252S
BU9252F
Pd
Tstg
600
∗
1
450
∗
2
∗
1 IC only. Reduce by – 6mW / °C for each in Ta of 1°C over 25°C.
∗
2 IC only. Reduce by – 4.5mW / °C for each in Ta of 1°C over 25°C.
•
Recommended operating conditions
Parameter Symbol Limits Unit
V
DD 4.5 ~ 5.5 V
AV
DD VDD V
V
IL 0.0 ~ 0.2VDD V
V
IH 0.8VDD ~ VDD V
V
AIN 0 ~ AVDD V
f
OSC 200 ~ 1000 kHz
Topr – 10 ~ + 70 °C
Power supply voltage
Analog power supply voltage
Input "L" voltage
Input "H" voltage
Analog input voltage
Clock frequency
Operating temperature
•
Electrical characteristics (unless otherwise noted, Ta = 25°C, VDD = AVDD = 5V)
Parameter Symbol Min. Typ. Max. Unit Conditions
I
DD — 3.5 12 mA
I
AOUT
14—mA
0.3 0.8 — mA
R
AIN 12 25 60 kΩ
RES — 2 — LSB
V
LOSC — 0.6 1.2 V
V
HOSC 3.8 4.4 — V IOH = – 100µA
I
OSCI 1620µAVOSCI = VDD
—— 150 — pF
I
OL = 100µA
V
AIN = AVDD, fOSC = 455kHz
V
AOUT = 1V, VAIN = 0V
V
AOUT = 0.5VDD, VAIN = VDD
∗
The bias circuit is impedance.
∗
Supply current
Analog output current
Analog input impedance
A / D to D / A precision
OSCO output "L" voltage
OSCO output "H" voltage
OSCI feedback loop current
Oscillation capacity
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Multimedia ICs BU9252S / BU9252F
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Circuit operation
(1) External capacitor for signal input pin
Audio signals compressed by the BA7725S or
BA7725FS have their DC component removed by an
AC coupling capacitor and are then input to pin 2 of
BU9252S or BU9252F. At this stage, level deviations
occur because the input signal is capacitor-divided by
this AC coupling capacitor C28 and by sampling hold
capacitor C27 connected to pin 1.
To prevent this, make sure that C27 is much lower
than C28.
(Note: The numbers of external components are the numbers used in the system application example.)
(3) Delay timer settings
The delay time (i.e., the length of time the signal is
stored in the SRAM) can be set to any of eight settings
between the maximum and minimum delay times by
setting pins 6, 7 and 8 to the combination of logic signal inputs that results in the corresponding number of
counts. The maximum and minimum delay times are
determined by the oscillation frequency of the attached
ceramic resonator.
1
2
S / H
C27
C28
The sample-held analog signal is converted to digital
by the serial 8-bit A / D converter and then temporarily
stored in the internal SRAM (2k bytes).
(2) Relationship between oscillation frequency (CLK)
and delay time
Sample rate F = f
OSC / 32 (fosc: oscillation frequency)
F = 14.22kHz at fosc = 455kHz
Sample period T = 1 / F
Delay time Dtime = T × number of counts
The delay time can be set to any of the eight settings shown below by setting the logic inputs of terminals DCNT0
through DCNT2.
Logic input Count
DCNT1 DCNT2 DCNT0 BU9252S / F
0 0 0 256 18.00
0 0 1 512 36.01
0 1 0 768 54.01
0 1 1 1024 72.02
1 0 0 1280 90.02
1 0 1 1536 108.03
1 1 0 1792 126.03
1 1 1 2048 144.04
BU9252S / F
Delay time (ms) (when f
OSC = 455kHz)
CCC
(t)
(dB)
C : Delay time (ms)
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Multimedia ICs BU9252S / BU9252F
Maximum and minimum delay times when using 300kHz, 375kHz and 455kHz ceramic oscillators
(4) Peripheral components of the ceramic oscillator
An oscillator circuit can be configured simply by attaching a 455kHz ceramic resonator.
300kHz 375kHz 455kHz
Max. Min. Max. Min. Max. Min.
218.45 27.30 174.76 21.85 144.04 18.00
Delay time (ms)
Rd
Rf
OSCO
OSCI
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External dimensions (Units: mm)
SOP18
0.51Min.
0° ~ 15°
7.62
3.95 ± 0.3
1.778
10
9
6.5 ± 0.3
19.4 ± 0.3
18
1
0.5 ± 0.1
3.4 ± 0.2
0.3 ± 0.1
SDIP18
BU9252FBU9252S
0.4 ± 0.11.27
0.3Min.
0.11
1.8 ± 0.1
5.4 ± 0.2
7.8 ± 0.3
0.15 ± 0.1
18
1
11.2 ± 0.2
10
9
0.15
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